xref: /llvm-project/clang/test/CodeGen/PowerPC/vector-compat.c (revision 7e59223ac4b045178c287a56154113d5989572f4)
1 // RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
2 // RUN:   -faltivec-src-compat=mixed -triple powerpc-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
3 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
4 // RUN:   -faltivec-src-compat=gcc -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
5 // RUN: not %clang_cc1 -target-feature +altivec -target-feature +vsx \
6 // RUN:   -faltivec-src-compat=xl -triple powerpc-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR
7 // RUN: %clang -mcpu=pwr8 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
8 // RUN: %clang -mcpu=pwr9 -faltivec-src-compat=gcc --target=powerpc-unknown-unknown -S -emit-llvm %s -o - | FileCheck %s
9 
10 // CHECK-LABEL: @ui8(
11 // CHECK:         [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
12 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
13 // CHECK-NEXT:    store <16 x i8> [[A:%.*]], ptr [[A_ADDR]], align 16
14 // CHECK-NEXT:    store <16 x i8> [[B:%.*]], ptr [[B_ADDR]], align 16
15 // CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr [[A_ADDR]], align 16
16 // CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr [[B_ADDR]], align 16
17 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
18 // CHECK-NEXT:    [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
19 // CHECK-NEXT:    ret <16 x i8> [[SEXT]]
20 //
21 // ERROR: returning 'int' from a function with incompatible result type
ui8(vector unsigned char a,vector unsigned char b)22 vector unsigned char ui8(vector unsigned char a, vector unsigned char b) {
23   return a == b;
24 }
25 
26 // CHECK-LABEL: @si8(
27 // CHECK:         [[A_ADDR:%.*]] = alloca <16 x i8>, align 16
28 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <16 x i8>, align 16
29 // CHECK-NEXT:    store <16 x i8> [[A:%.*]], ptr [[A_ADDR]], align 16
30 // CHECK-NEXT:    store <16 x i8> [[B:%.*]], ptr [[B_ADDR]], align 16
31 // CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i8>, ptr [[A_ADDR]], align 16
32 // CHECK-NEXT:    [[TMP1:%.*]] = load <16 x i8>, ptr [[B_ADDR]], align 16
33 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
34 // CHECK-NEXT:    [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
35 // CHECK-NEXT:    ret <16 x i8> [[SEXT]]
36 //
37 // ERROR: returning 'int' from a function with incompatible result type
si8(vector signed char a,vector signed char b)38 vector signed char si8(vector signed char a, vector signed char b) {
39   return a == b;
40 }
41 
42 // CHECK-LABEL: @ui16(
43 // CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
44 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
45 // CHECK-NEXT:    store <8 x i16> [[A:%.*]], ptr [[A_ADDR]], align 16
46 // CHECK-NEXT:    store <8 x i16> [[B:%.*]], ptr [[B_ADDR]], align 16
47 // CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, ptr [[A_ADDR]], align 16
48 // CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, ptr [[B_ADDR]], align 16
49 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
50 // CHECK-NEXT:    [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
51 // CHECK-NEXT:    ret <8 x i16> [[SEXT]]
52 //
53 // ERROR: returning 'int' from a function with incompatible result type
ui16(vector unsigned short a,vector unsigned short b)54 vector unsigned short ui16(vector unsigned short a, vector unsigned short b) {
55   return a == b;
56 }
57 
58 // CHECK-LABEL: @si16(
59 // CHECK:         [[A_ADDR:%.*]] = alloca <8 x i16>, align 16
60 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <8 x i16>, align 16
61 // CHECK-NEXT:    store <8 x i16> [[A:%.*]], ptr [[A_ADDR]], align 16
62 // CHECK-NEXT:    store <8 x i16> [[B:%.*]], ptr [[B_ADDR]], align 16
63 // CHECK-NEXT:    [[TMP0:%.*]] = load <8 x i16>, ptr [[A_ADDR]], align 16
64 // CHECK-NEXT:    [[TMP1:%.*]] = load <8 x i16>, ptr [[B_ADDR]], align 16
65 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <8 x i16> [[TMP0]], [[TMP1]]
66 // CHECK-NEXT:    [[SEXT:%.*]] = sext <8 x i1> [[CMP]] to <8 x i16>
67 // CHECK-NEXT:    ret <8 x i16> [[SEXT]]
68 //
69 // ERROR: returning 'int' from a function with incompatible result type
si16(vector signed short a,vector signed short b)70 vector signed short si16(vector signed short a, vector signed short b) {
71   return a == b;
72 }
73 
74 // CHECK-LABEL: @ui32(
75 // CHECK:         [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
76 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
77 // CHECK-NEXT:    store <4 x i32> [[A:%.*]], ptr [[A_ADDR]], align 16
78 // CHECK-NEXT:    store <4 x i32> [[B:%.*]], ptr [[B_ADDR]], align 16
79 // CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, ptr [[A_ADDR]], align 16
80 // CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr [[B_ADDR]], align 16
81 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]]
82 // CHECK-NEXT:    [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
83 // CHECK-NEXT:    ret <4 x i32> [[SEXT]]
84 //
85 // ERROR: returning 'int' from a function with incompatible result type
ui32(vector unsigned int a,vector unsigned int b)86 vector unsigned int ui32(vector unsigned int a, vector unsigned int b) {
87   return a == b;
88 }
89 
90 // CHECK-LABEL: @si32(
91 // CHECK:         [[A_ADDR:%.*]] = alloca <4 x i32>, align 16
92 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x i32>, align 16
93 // CHECK-NEXT:    store <4 x i32> [[A:%.*]], ptr [[A_ADDR]], align 16
94 // CHECK-NEXT:    store <4 x i32> [[B:%.*]], ptr [[B_ADDR]], align 16
95 // CHECK-NEXT:    [[TMP0:%.*]] = load <4 x i32>, ptr [[A_ADDR]], align 16
96 // CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr [[B_ADDR]], align 16
97 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> [[TMP0]], [[TMP1]]
98 // CHECK-NEXT:    [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
99 // CHECK-NEXT:    ret <4 x i32> [[SEXT]]
100 //
101 // ERROR: returning 'int' from a function with incompatible result type
si32(vector signed int a,vector signed int b)102 vector signed int si32(vector signed int a, vector signed int b) {
103   return a == b;
104 }
105 
106 // CHECK-LABEL: @si64(
107 // CHECK:         [[A_ADDR:%.*]] = alloca <2 x i64>, align 16
108 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x i64>, align 16
109 // CHECK-NEXT:    store <2 x i64> [[A:%.*]], ptr [[A_ADDR]], align 16
110 // CHECK-NEXT:    store <2 x i64> [[B:%.*]], ptr [[B_ADDR]], align 16
111 // CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, ptr [[A_ADDR]], align 16
112 // CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[B_ADDR]], align 16
113 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <2 x i64> [[TMP0]], [[TMP1]]
114 // CHECK-NEXT:    [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64>
115 // CHECK-NEXT:    ret <2 x i64> [[SEXT]]
116 //
117 // ERROR: returning 'int' from a function with incompatible result type
si64(vector long long a,vector long long b)118 vector long long si64(vector long long a, vector long long b) {
119   return a == b;
120 }
121 
122 // CHECK-LABEL: @f32(
123 // CHECK:         [[A_ADDR:%.*]] = alloca <4 x float>, align 16
124 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <4 x float>, align 16
125 // CHECK-NEXT:    store <4 x float> [[A:%.*]], ptr [[A_ADDR]], align 16
126 // CHECK-NEXT:    store <4 x float> [[B:%.*]], ptr [[B_ADDR]], align 16
127 // CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, ptr [[A_ADDR]], align 16
128 // CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, ptr [[B_ADDR]], align 16
129 // CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq <4 x float> [[TMP0]], [[TMP1]]
130 // CHECK-NEXT:    [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
131 // CHECK-NEXT:    ret <4 x i32> [[SEXT]]
132 //
133 // ERROR: returning 'int' from a function with incompatible result type
f32(vector float a,vector float b)134 vector int f32(vector float a, vector float b) {
135   return a == b;
136 }
137 
138 // CHECK-LABEL: @f64(
139 // CHECK:         [[A_ADDR:%.*]] = alloca <2 x double>, align 16
140 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca <2 x double>, align 16
141 // CHECK-NEXT:    store <2 x double> [[A:%.*]], ptr [[A_ADDR]], align 16
142 // CHECK-NEXT:    store <2 x double> [[B:%.*]], ptr [[B_ADDR]], align 16
143 // CHECK-NEXT:    [[TMP0:%.*]] = load <2 x double>, ptr [[A_ADDR]], align 16
144 // CHECK-NEXT:    [[TMP1:%.*]] = load <2 x double>, ptr [[B_ADDR]], align 16
145 // CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq <2 x double> [[TMP0]], [[TMP1]]
146 // CHECK-NEXT:    [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i64>
147 // CHECK-NEXT:    ret <2 x i64> [[SEXT]]
148 //
149 // ERROR: returning 'int' from a function with incompatible result type
f64(vector double a,vector double b)150 vector long long f64(vector double a, vector double b) {
151   return a == b;
152 }
153