1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals 2 // RUN: %clang_cc1 -triple aarch64 -emit-llvm %s -o - | FileCheck %s 3 4 __attribute__((target("arch=armv8.2-a"))) 5 // CHECK-LABEL: define {{[^@]+}}@v82 6 // CHECK-SAME: () #[[ATTR0:[0-9]+]] { 7 // CHECK-NEXT: entry: 8 // CHECK-NEXT: ret void 9 // 10 void v82() {} 11 __attribute__((target("arch=armv8.2-a+sve"))) 12 // CHECK-LABEL: define {{[^@]+}}@v82sve 13 // CHECK-SAME: () #[[ATTR1:[0-9]+]] { 14 // CHECK-NEXT: entry: 15 // CHECK-NEXT: ret void 16 // 17 void v82sve() {} 18 __attribute__((target("arch=armv8.2-a+sve2"))) 19 // CHECK-LABEL: define {{[^@]+}}@v82sve2 20 // CHECK-SAME: () #[[ATTR2:[0-9]+]] { 21 // CHECK-NEXT: entry: 22 // CHECK-NEXT: ret void 23 // 24 void v82sve2() {} 25 __attribute__((target("arch=armv8.2-a+sve+sve2"))) 26 // CHECK-LABEL: define {{[^@]+}}@v82svesve2 27 // CHECK-SAME: () #[[ATTR2]] { 28 // CHECK-NEXT: entry: 29 // CHECK-NEXT: ret void 30 // 31 void v82svesve2() {} 32 __attribute__((target("arch=armv8.6-a+sve2"))) 33 // CHECK-LABEL: define {{[^@]+}}@v86sve2 34 // CHECK-SAME: () #[[ATTR3:[0-9]+]] { 35 // CHECK-NEXT: entry: 36 // CHECK-NEXT: ret void 37 // 38 void v86sve2() {} 39 40 __attribute__((target("cpu=cortex-a710"))) 41 // CHECK-LABEL: define {{[^@]+}}@a710 42 // CHECK-SAME: () #[[ATTR4:[0-9]+]] { 43 // CHECK-NEXT: entry: 44 // CHECK-NEXT: ret void 45 // 46 void a710() {} 47 __attribute__((target("tune=cortex-a710"))) 48 // CHECK-LABEL: define {{[^@]+}}@tunea710 49 // CHECK-SAME: () #[[ATTR5:[0-9]+]] { 50 // CHECK-NEXT: entry: 51 // CHECK-NEXT: ret void 52 // 53 void tunea710() {} 54 __attribute__((target("cpu=generic"))) 55 // CHECK-LABEL: define {{[^@]+}}@generic 56 // CHECK-SAME: () #[[ATTR6:[0-9]+]] { 57 // CHECK-NEXT: entry: 58 // CHECK-NEXT: ret void 59 // 60 void generic() {} 61 __attribute__((target("tune=generic"))) 62 // CHECK-LABEL: define {{[^@]+}}@tune 63 // CHECK-SAME: () #[[ATTR7:[0-9]+]] { 64 // CHECK-NEXT: entry: 65 // CHECK-NEXT: ret void 66 // 67 void tune() {} 68 69 __attribute__((target("cpu=neoverse-n1,tune=cortex-a710"))) 70 // CHECK-LABEL: define {{[^@]+}}@n1tunea710 71 // CHECK-SAME: () #[[ATTR8:[0-9]+]] { 72 // CHECK-NEXT: entry: 73 // CHECK-NEXT: ret void 74 // 75 void n1tunea710() {} 76 __attribute__((target("sve,tune=cortex-a710"))) 77 // CHECK-LABEL: define {{[^@]+}}@svetunea710 78 // CHECK-SAME: () #[[ATTR9:[0-9]+]] { 79 // CHECK-NEXT: entry: 80 // CHECK-NEXT: ret void 81 // 82 void svetunea710() {} 83 __attribute__((target("+sve,tune=cortex-a710"))) 84 // CHECK-LABEL: define {{[^@]+}}@plussvetunea710 85 // CHECK-SAME: () #[[ATTR9]] { 86 // CHECK-NEXT: entry: 87 // CHECK-NEXT: ret void 88 // 89 void plussvetunea710() {} 90 __attribute__((target("cpu=neoverse-v1,+sve2"))) 91 // CHECK-LABEL: define {{[^@]+}}@v1plussve2 92 // CHECK-SAME: () #[[ATTR10:[0-9]+]] { 93 // CHECK-NEXT: entry: 94 // CHECK-NEXT: ret void 95 // 96 void v1plussve2() {} 97 __attribute__((target("cpu=neoverse-v1+sve2"))) 98 // CHECK-LABEL: define {{[^@]+}}@v1sve2 99 // CHECK-SAME: () #[[ATTR10]] { 100 // CHECK-NEXT: entry: 101 // CHECK-NEXT: ret void 102 // 103 void v1sve2() {} 104 __attribute__((target("cpu=neoverse-v1,+nosve"))) 105 // CHECK-LABEL: define {{[^@]+}}@v1minussve 106 // CHECK-SAME: () #[[ATTR11:[0-9]+]] { 107 // CHECK-NEXT: entry: 108 // CHECK-NEXT: ret void 109 // 110 void v1minussve() {} 111 __attribute__((target("cpu=neoverse-v1,no-sve"))) 112 // CHECK-LABEL: define {{[^@]+}}@v1nosve 113 // CHECK-SAME: () #[[ATTR11]] { 114 // CHECK-NEXT: entry: 115 // CHECK-NEXT: ret void 116 // 117 void v1nosve() {} 118 __attribute__((target("cpu=neoverse-v1+nosve"))) 119 // CHECK-LABEL: define {{[^@]+}}@v1msve 120 // CHECK-SAME: () #[[ATTR11]] { 121 // CHECK-NEXT: entry: 122 // CHECK-NEXT: ret void 123 // 124 void v1msve() {} 125 126 __attribute__((target("+sve"))) 127 // CHECK-LABEL: define {{[^@]+}}@plussve 128 // CHECK-SAME: () #[[ATTR12:[0-9]+]] { 129 // CHECK-NEXT: entry: 130 // CHECK-NEXT: ret void 131 // 132 void plussve() {} 133 __attribute__((target("+sve+nosve2"))) 134 // CHECK-LABEL: define {{[^@]+}}@plussveplussve2 135 // CHECK-SAME: () #[[ATTR12]] { 136 // CHECK-NEXT: entry: 137 // CHECK-NEXT: ret void 138 // 139 void plussveplussve2() {} 140 __attribute__((target("sve,no-sve2"))) 141 // CHECK-LABEL: define {{[^@]+}}@plussveminusnosve2 142 // CHECK-SAME: () #[[ATTR12]] { 143 // CHECK-NEXT: entry: 144 // CHECK-NEXT: ret void 145 // 146 void plussveminusnosve2() {} 147 __attribute__((target("+fp16"))) 148 // CHECK-LABEL: define {{[^@]+}}@plusfp16 149 // CHECK-SAME: () #[[ATTR13:[0-9]+]] { 150 // CHECK-NEXT: entry: 151 // CHECK-NEXT: ret void 152 // 153 void plusfp16() {} 154 155 __attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2"))) 156 // CHECK-LABEL: define {{[^@]+}}@all 157 // CHECK-SAME: () #[[ATTR14:[0-9]+]] { 158 // CHECK-NEXT: entry: 159 // CHECK-NEXT: ret void 160 // 161 void all() {} 162 __attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2,branch-protection=standard"))) 163 // CHECK-LABEL: define {{[^@]+}}@allplusbranchprotection 164 // CHECK-SAME: () #[[ATTR15:[0-9]+]] { 165 // CHECK-NEXT: entry: 166 // CHECK-NEXT: ret void 167 // 168 void allplusbranchprotection() {} 169 170 __attribute__((target("+nosimd"))) 171 // CHECK-LABEL: define {{[^@]+}}@plusnosimd 172 // CHECK-SAME: () #[[ATTR16:[0-9]+]] { 173 // CHECK-NEXT: entry: 174 // CHECK-NEXT: ret void 175 // 176 void plusnosimd() {} 177 __attribute__((target("no-simd"))) 178 // CHECK-LABEL: define {{[^@]+}}@nosimd 179 // CHECK-SAME: () #[[ATTR16]] { 180 // CHECK-NEXT: entry: 181 // CHECK-NEXT: ret void 182 // 183 void nosimd() {} 184 185 // This isn't part of the standard interface, but test that -arch features should not apply anything else. 186 __attribute__((target("no-v9.3a"))) 187 // CHECK-LABEL: define {{[^@]+}}@minusarch 188 // CHECK-SAME: () #[[ATTR17:[0-9]+]] { 189 // CHECK-NEXT: entry: 190 // CHECK-NEXT: ret void 191 // 192 void minusarch() {} 193 194 __attribute__((target("cpu=apple-m4"))) 195 // CHECK-LABEL: define {{[^@]+}}@applem4 196 // CHECK-SAME: () #[[ATTR18:[0-9]+]] { 197 // CHECK-NEXT: entry: 198 // CHECK-NEXT: ret void 199 // 200 void applem4() {} 201 202 //. 203 // CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" } 204 // CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" } 205 // CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" } 206 // CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" } 207 // CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve-bitperm,+sve2,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" } 208 // CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" } 209 // CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" } 210 // CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" } 211 // CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" } 212 // CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" } 213 // CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" } 214 // CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" } 215 // CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" } 216 // CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" } 217 // CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } 218 // CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } 219 // CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } 220 // CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" } 221 // CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+spe-eef,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" } 222 //. 223 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} 224 // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} 225 //. 226