xref: /llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpe.c (revision 207e5ccceec8d3cc3f32723e78f2a142bc61b07d)
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: aarch64-registered-target
3 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
4 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
6 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
8 // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
9 
10 #include <arm_sve.h>
11 
12 #if defined __ARM_FEATURE_SME
13 #define MODE_ATTR __arm_streaming
14 #else
15 #define MODE_ATTR
16 #endif
17 
18 #ifdef SVE_OVERLOADED_FORMS
19 // A simple used,unused... macro, long enough to represent any SVE builtin.
20 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
21 #else
22 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
23 #endif
24 
25 // CHECK-LABEL: @test_svrecpe_f16(
26 // CHECK-NEXT:  entry:
27 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> [[OP:%.*]])
28 // CHECK-NEXT:    ret <vscale x 8 x half> [[TMP0]]
29 //
30 // CPP-CHECK-LABEL: @_Z16test_svrecpe_f16u13__SVFloat16_t(
31 // CPP-CHECK-NEXT:  entry:
32 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.frecpe.x.nxv8f16(<vscale x 8 x half> [[OP:%.*]])
33 // CPP-CHECK-NEXT:    ret <vscale x 8 x half> [[TMP0]]
34 //
35 svfloat16_t test_svrecpe_f16(svfloat16_t op) MODE_ATTR
36 {
37   return SVE_ACLE_FUNC(svrecpe,_f16,,)(op);
38 }
39 
40 // CHECK-LABEL: @test_svrecpe_f32(
41 // CHECK-NEXT:  entry:
42 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> [[OP:%.*]])
43 // CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
44 //
45 // CPP-CHECK-LABEL: @_Z16test_svrecpe_f32u13__SVFloat32_t(
46 // CPP-CHECK-NEXT:  entry:
47 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frecpe.x.nxv4f32(<vscale x 4 x float> [[OP:%.*]])
48 // CPP-CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
49 //
50 svfloat32_t test_svrecpe_f32(svfloat32_t op) MODE_ATTR
51 {
52   return SVE_ACLE_FUNC(svrecpe,_f32,,)(op);
53 }
54 
55 // CHECK-LABEL: @test_svrecpe_f64(
56 // CHECK-NEXT:  entry:
57 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> [[OP:%.*]])
58 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP0]]
59 //
60 // CPP-CHECK-LABEL: @_Z16test_svrecpe_f64u13__SVFloat64_t(
61 // CPP-CHECK-NEXT:  entry:
62 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frecpe.x.nxv2f64(<vscale x 2 x double> [[OP:%.*]])
63 // CPP-CHECK-NEXT:    ret <vscale x 2 x double> [[TMP0]]
64 //
65 svfloat64_t test_svrecpe_f64(svfloat64_t op) MODE_ATTR
66 {
67   return SVE_ACLE_FUNC(svrecpe,_f64,,)(op);
68 }
69