1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 2 // REQUIRES: aarch64-registered-target 3 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s 4 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK 5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s 6 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK 7 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s 8 // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s 9 10 #include <arm_sve.h> 11 12 #if defined __ARM_FEATURE_SME 13 #define MODE_ATTR __arm_streaming 14 #else 15 #define MODE_ATTR 16 #endif 17 18 #ifdef SVE_OVERLOADED_FORMS 19 // A simple used,unused... macro, long enough to represent any SVE builtin. 20 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 21 #else 22 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 23 #endif 24 25 // CHECK-LABEL: @test_svqdech_n_s32( 26 // CHECK-NEXT: entry: 27 // CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqdech.n32(i32 [[OP:%.*]], i32 31, i32 1) 28 // CHECK-NEXT: ret i32 [[TMP0]] 29 // 30 // CPP-CHECK-LABEL: @_Z18test_svqdech_n_s32i( 31 // CPP-CHECK-NEXT: entry: 32 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqdech.n32(i32 [[OP:%.*]], i32 31, i32 1) 33 // CPP-CHECK-NEXT: ret i32 [[TMP0]] 34 // 35 int32_t test_svqdech_n_s32(int32_t op) MODE_ATTR 36 { 37 return SVE_ACLE_FUNC(svqdech,_n_s32,,)(op, 1); 38 } 39 40 // CHECK-LABEL: @test_svqdech_n_s32_1( 41 // CHECK-NEXT: entry: 42 // CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqdech.n32(i32 [[OP:%.*]], i32 31, i32 16) 43 // CHECK-NEXT: ret i32 [[TMP0]] 44 // 45 // CPP-CHECK-LABEL: @_Z20test_svqdech_n_s32_1i( 46 // CPP-CHECK-NEXT: entry: 47 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqdech.n32(i32 [[OP:%.*]], i32 31, i32 16) 48 // CPP-CHECK-NEXT: ret i32 [[TMP0]] 49 // 50 int32_t test_svqdech_n_s32_1(int32_t op) MODE_ATTR 51 { 52 return SVE_ACLE_FUNC(svqdech,_n_s32,,)(op, 16); 53 } 54 55 // CHECK-LABEL: @test_svqdech_n_s64( 56 // CHECK-NEXT: entry: 57 // CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.sqdech.n64(i64 [[OP:%.*]], i32 31, i32 1) 58 // CHECK-NEXT: ret i64 [[TMP0]] 59 // 60 // CPP-CHECK-LABEL: @_Z18test_svqdech_n_s64l( 61 // CPP-CHECK-NEXT: entry: 62 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.sqdech.n64(i64 [[OP:%.*]], i32 31, i32 1) 63 // CPP-CHECK-NEXT: ret i64 [[TMP0]] 64 // 65 int64_t test_svqdech_n_s64(int64_t op) MODE_ATTR 66 { 67 return SVE_ACLE_FUNC(svqdech,_n_s64,,)(op, 1); 68 } 69 70 // CHECK-LABEL: @test_svqdech_n_u32( 71 // CHECK-NEXT: entry: 72 // CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.uqdech.n32(i32 [[OP:%.*]], i32 31, i32 16) 73 // CHECK-NEXT: ret i32 [[TMP0]] 74 // 75 // CPP-CHECK-LABEL: @_Z18test_svqdech_n_u32j( 76 // CPP-CHECK-NEXT: entry: 77 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.uqdech.n32(i32 [[OP:%.*]], i32 31, i32 16) 78 // CPP-CHECK-NEXT: ret i32 [[TMP0]] 79 // 80 uint32_t test_svqdech_n_u32(uint32_t op) MODE_ATTR 81 { 82 return SVE_ACLE_FUNC(svqdech,_n_u32,,)(op, 16); 83 } 84 85 // CHECK-LABEL: @test_svqdech_n_u64( 86 // CHECK-NEXT: entry: 87 // CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uqdech.n64(i64 [[OP:%.*]], i32 31, i32 1) 88 // CHECK-NEXT: ret i64 [[TMP0]] 89 // 90 // CPP-CHECK-LABEL: @_Z18test_svqdech_n_u64m( 91 // CPP-CHECK-NEXT: entry: 92 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uqdech.n64(i64 [[OP:%.*]], i32 31, i32 1) 93 // CPP-CHECK-NEXT: ret i64 [[TMP0]] 94 // 95 uint64_t test_svqdech_n_u64(uint64_t op) MODE_ATTR 96 { 97 return SVE_ACLE_FUNC(svqdech,_n_u64,,)(op, 1); 98 } 99 100 // CHECK-LABEL: @test_svqdech_pat_n_s32( 101 // CHECK-NEXT: entry: 102 // CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqdech.n32(i32 [[OP:%.*]], i32 10, i32 16) 103 // CHECK-NEXT: ret i32 [[TMP0]] 104 // 105 // CPP-CHECK-LABEL: @_Z22test_svqdech_pat_n_s32i( 106 // CPP-CHECK-NEXT: entry: 107 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqdech.n32(i32 [[OP:%.*]], i32 10, i32 16) 108 // CPP-CHECK-NEXT: ret i32 [[TMP0]] 109 // 110 int32_t test_svqdech_pat_n_s32(int32_t op) MODE_ATTR 111 { 112 return SVE_ACLE_FUNC(svqdech_pat,_n_s32,,)(op, SV_VL32, 16); 113 } 114 115 // CHECK-LABEL: @test_svqdech_pat_n_s64( 116 // CHECK-NEXT: entry: 117 // CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.sqdech.n64(i64 [[OP:%.*]], i32 11, i32 1) 118 // CHECK-NEXT: ret i64 [[TMP0]] 119 // 120 // CPP-CHECK-LABEL: @_Z22test_svqdech_pat_n_s64l( 121 // CPP-CHECK-NEXT: entry: 122 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.sqdech.n64(i64 [[OP:%.*]], i32 11, i32 1) 123 // CPP-CHECK-NEXT: ret i64 [[TMP0]] 124 // 125 int64_t test_svqdech_pat_n_s64(int64_t op) MODE_ATTR 126 { 127 return SVE_ACLE_FUNC(svqdech_pat,_n_s64,,)(op, SV_VL64, 1); 128 } 129 130 // CHECK-LABEL: @test_svqdech_pat_n_u32( 131 // CHECK-NEXT: entry: 132 // CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.uqdech.n32(i32 [[OP:%.*]], i32 12, i32 16) 133 // CHECK-NEXT: ret i32 [[TMP0]] 134 // 135 // CPP-CHECK-LABEL: @_Z22test_svqdech_pat_n_u32j( 136 // CPP-CHECK-NEXT: entry: 137 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.uqdech.n32(i32 [[OP:%.*]], i32 12, i32 16) 138 // CPP-CHECK-NEXT: ret i32 [[TMP0]] 139 // 140 uint32_t test_svqdech_pat_n_u32(uint32_t op) MODE_ATTR 141 { 142 return SVE_ACLE_FUNC(svqdech_pat,_n_u32,,)(op, SV_VL128, 16); 143 } 144 145 // CHECK-LABEL: @test_svqdech_pat_n_u64( 146 // CHECK-NEXT: entry: 147 // CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uqdech.n64(i64 [[OP:%.*]], i32 13, i32 1) 148 // CHECK-NEXT: ret i64 [[TMP0]] 149 // 150 // CPP-CHECK-LABEL: @_Z22test_svqdech_pat_n_u64m( 151 // CPP-CHECK-NEXT: entry: 152 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uqdech.n64(i64 [[OP:%.*]], i32 13, i32 1) 153 // CPP-CHECK-NEXT: ret i64 [[TMP0]] 154 // 155 uint64_t test_svqdech_pat_n_u64(uint64_t op) MODE_ATTR 156 { 157 return SVE_ACLE_FUNC(svqdech_pat,_n_u64,,)(op, SV_VL256, 1); 158 } 159 160 // CHECK-LABEL: @test_svqdech_s16( 161 // CHECK-NEXT: entry: 162 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> [[OP:%.*]], i32 31, i32 16) 163 // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] 164 // 165 // CPP-CHECK-LABEL: @_Z16test_svqdech_s16u11__SVInt16_t( 166 // CPP-CHECK-NEXT: entry: 167 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> [[OP:%.*]], i32 31, i32 16) 168 // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] 169 // 170 svint16_t test_svqdech_s16(svint16_t op) MODE_ATTR 171 { 172 return SVE_ACLE_FUNC(svqdech,_s16,,)(op, 16); 173 } 174 175 // CHECK-LABEL: @test_svqdech_u16( 176 // CHECK-NEXT: entry: 177 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> [[OP:%.*]], i32 31, i32 1) 178 // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] 179 // 180 // CPP-CHECK-LABEL: @_Z16test_svqdech_u16u12__SVUint16_t( 181 // CPP-CHECK-NEXT: entry: 182 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> [[OP:%.*]], i32 31, i32 1) 183 // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] 184 // 185 svuint16_t test_svqdech_u16(svuint16_t op) MODE_ATTR 186 { 187 return SVE_ACLE_FUNC(svqdech,_u16,,)(op, 1); 188 } 189 190 // CHECK-LABEL: @test_svqdech_pat_s16( 191 // CHECK-NEXT: entry: 192 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> [[OP:%.*]], i32 29, i32 16) 193 // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] 194 // 195 // CPP-CHECK-LABEL: @_Z20test_svqdech_pat_s16u11__SVInt16_t( 196 // CPP-CHECK-NEXT: entry: 197 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.sqdech.nxv8i16(<vscale x 8 x i16> [[OP:%.*]], i32 29, i32 16) 198 // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] 199 // 200 svint16_t test_svqdech_pat_s16(svint16_t op) MODE_ATTR 201 { 202 return SVE_ACLE_FUNC(svqdech_pat,_s16,,)(op, SV_MUL4, 16); 203 } 204 205 // CHECK-LABEL: @test_svqdech_pat_u16( 206 // CHECK-NEXT: entry: 207 // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> [[OP:%.*]], i32 30, i32 1) 208 // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] 209 // 210 // CPP-CHECK-LABEL: @_Z20test_svqdech_pat_u16u12__SVUint16_t( 211 // CPP-CHECK-NEXT: entry: 212 // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> [[OP:%.*]], i32 30, i32 1) 213 // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] 214 // 215 svuint16_t test_svqdech_pat_u16(svuint16_t op) MODE_ATTR 216 { 217 return SVE_ACLE_FUNC(svqdech_pat,_u16,,)(op, SV_MUL3, 1); 218 } 219