1 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ 2 // RUN: -target-feature +neon -O1 -o - -emit-llvm %s | FileCheck %s 3 4 // Tests to check that all sve datatypes can be passed in as input operands 5 // and passed out as output operands. 6 7 #define SVINT_TEST(DT, KIND)\ 8 DT func_int_##DT##KIND(DT in)\ 9 {\ 10 DT out;\ 11 asm volatile (\ 12 "ptrue p0.b\n"\ 13 "mov %[out]." #KIND ", p0/m, %[in]." #KIND "\n"\ 14 : [out] "=w" (out)\ 15 : [in] "w" (in)\ 16 : "p0"\ 17 );\ 18 return out;\ 19 } 20 21 SVINT_TEST(__SVUint8_t,b); 22 // CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in) 23 SVINT_TEST(__SVUint8_t,h); 24 // CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in) 25 SVINT_TEST(__SVUint8_t,s); 26 // CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in) 27 SVINT_TEST(__SVUint8_t,d); 28 // CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in) 29 30 SVINT_TEST(__SVUint16_t,b); 31 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in) 32 SVINT_TEST(__SVUint16_t,h); 33 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in) 34 SVINT_TEST(__SVUint16_t,s); 35 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in) 36 SVINT_TEST(__SVUint16_t,d); 37 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in) 38 39 SVINT_TEST(__SVUint32_t,b); 40 // CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in) 41 SVINT_TEST(__SVUint32_t,h); 42 // CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in) 43 SVINT_TEST(__SVUint32_t,s); 44 // CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in) 45 SVINT_TEST(__SVUint32_t,d); 46 // CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in) 47 48 SVINT_TEST(__SVUint64_t,b); 49 // CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in) 50 SVINT_TEST(__SVUint64_t,h); 51 // CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in) 52 SVINT_TEST(__SVUint64_t,s); 53 // CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in) 54 SVINT_TEST(__SVUint64_t,d); 55 // CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in) 56 57 SVINT_TEST(__SVInt8_t,b); 58 // CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in) 59 SVINT_TEST(__SVInt8_t,h); 60 // CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in) 61 SVINT_TEST(__SVInt8_t,s); 62 // CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in) 63 SVINT_TEST(__SVInt8_t,d); 64 // CHECK: call <vscale x 16 x i8> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 16 x i8> %in) 65 66 SVINT_TEST(__SVInt16_t,b); 67 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in) 68 SVINT_TEST(__SVInt16_t,h); 69 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in) 70 SVINT_TEST(__SVInt16_t,s); 71 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in) 72 SVINT_TEST(__SVInt16_t,d); 73 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 8 x i16> %in) 74 75 SVINT_TEST(__SVInt32_t,b); 76 // CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in) 77 SVINT_TEST(__SVInt32_t,h); 78 // CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in) 79 SVINT_TEST(__SVInt32_t,s); 80 // CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in) 81 SVINT_TEST(__SVInt32_t,d); 82 // CHECK: call <vscale x 4 x i32> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in) 83 84 SVINT_TEST(__SVInt64_t,b); 85 // CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in) 86 SVINT_TEST(__SVInt64_t,h); 87 // CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in) 88 SVINT_TEST(__SVInt64_t,s); 89 // CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in) 90 SVINT_TEST(__SVInt64_t,d); 91 // CHECK: call <vscale x 2 x i64> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x i64> %in) 92 93 94 //Test that floats can also be used as datatypes for integer instructions 95 //and check all the variants which would not be possible with a float 96 //instruction 97 SVINT_TEST(__SVFloat16_t,b); 98 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in) 99 SVINT_TEST(__SVFloat16_t,h); 100 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in) 101 SVINT_TEST(__SVFloat16_t,s); 102 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in) 103 SVINT_TEST(__SVFloat16_t,d); 104 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in) 105 106 SVINT_TEST(__SVFloat32_t,b); 107 // CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in) 108 SVINT_TEST(__SVFloat32_t,h); 109 // CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in) 110 SVINT_TEST(__SVFloat32_t,s); 111 // CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in) 112 SVINT_TEST(__SVFloat32_t,d); 113 // CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in) 114 115 SVINT_TEST(__SVFloat64_t,b); 116 // CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.b\0Amov $0.b, p0/m, $1.b\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in) 117 SVINT_TEST(__SVFloat64_t,h); 118 // CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.b\0Amov $0.h, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in) 119 SVINT_TEST(__SVFloat64_t,s); 120 // CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.b\0Amov $0.s, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in) 121 SVINT_TEST(__SVFloat64_t,d); 122 // CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.b\0Amov $0.d, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in) 123 124 125 #define SVBOOL_TEST(KIND)\ 126 __SVBool_t func_bool_##KIND(__SVBool_t in1, __SVBool_t in2)\ 127 {\ 128 __SVBool_t out;\ 129 asm volatile (\ 130 "zip1 %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND "\n"\ 131 : [out] "=Upa" (out)\ 132 : [in1] "Upa" (in1),\ 133 [in2] "Upa" (in2)\ 134 :);\ 135 return out;\ 136 } 137 138 SVBOOL_TEST(b) ; 139 // CHECK: call <vscale x 16 x i1> asm sideeffect "zip1 $0.b, $1.b, $2.b\0A", "=@3Upa,@3Upa,@3Upa"(<vscale x 16 x i1> %in1, <vscale x 16 x i1> %in2) 140 SVBOOL_TEST(h) ; 141 // CHECK: call <vscale x 16 x i1> asm sideeffect "zip1 $0.h, $1.h, $2.h\0A", "=@3Upa,@3Upa,@3Upa"(<vscale x 16 x i1> %in1, <vscale x 16 x i1> %in2) 142 SVBOOL_TEST(s) ; 143 // CHECK: call <vscale x 16 x i1> asm sideeffect "zip1 $0.s, $1.s, $2.s\0A", "=@3Upa,@3Upa,@3Upa"(<vscale x 16 x i1> %in1, <vscale x 16 x i1> %in2) 144 SVBOOL_TEST(d) ; 145 // CHECK: call <vscale x 16 x i1> asm sideeffect "zip1 $0.d, $1.d, $2.d\0A", "=@3Upa,@3Upa,@3Upa"(<vscale x 16 x i1> %in1, <vscale x 16 x i1> %in2) 146 147 148 #define SVBOOL_TEST_UPL(DT, KIND)\ 149 __SVBool_t func_bool_upl_##KIND(__SVBool_t in1, DT in2, DT in3)\ 150 {\ 151 __SVBool_t out;\ 152 asm volatile (\ 153 "fadd %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND ", %[in3]." #KIND "\n"\ 154 : [out] "=w" (out)\ 155 : [in1] "Upl" (in1),\ 156 [in2] "w" (in2),\ 157 [in3] "w" (in3)\ 158 :);\ 159 return out;\ 160 } 161 162 SVBOOL_TEST_UPL(__SVInt8_t, b) ; 163 // CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.b, $1.b, $2.b, $3.b\0A", "=w,@3Upl,w,w"(<vscale x 16 x i1> %in1, <vscale x 16 x i8> %in2, <vscale x 16 x i8> %in3) 164 SVBOOL_TEST_UPL(__SVInt16_t, h) ; 165 // CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.h, $1.h, $2.h, $3.h\0A", "=w,@3Upl,w,w"(<vscale x 16 x i1> %in1, <vscale x 8 x i16> %in2, <vscale x 8 x i16> %in3) 166 SVBOOL_TEST_UPL(__SVInt32_t, s) ; 167 // CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.s, $1.s, $2.s, $3.s\0A", "=w,@3Upl,w,w"(<vscale x 16 x i1> %in1, <vscale x 4 x i32> %in2, <vscale x 4 x i32> %in3) 168 SVBOOL_TEST_UPL(__SVInt64_t, d) ; 169 // CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.d, $1.d, $2.d, $3.d\0A", "=w,@3Upl,w,w"(<vscale x 16 x i1> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3) 170 171 #define SVBOOL_TEST_UPH(DT, KIND)\ 172 __SVBool_t func_bool_uph_##KIND(__SVBool_t in1, DT in2, DT in3)\ 173 {\ 174 __SVBool_t out;\ 175 asm volatile (\ 176 "fadd %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND ", %[in3]." #KIND "\n"\ 177 : [out] "=w" (out)\ 178 : [in1] "Uph" (in1),\ 179 [in2] "w" (in2),\ 180 [in3] "w" (in3)\ 181 :);\ 182 return out;\ 183 } 184 185 SVBOOL_TEST_UPH(__SVInt8_t, b) ; 186 // CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.b, $1.b, $2.b, $3.b\0A", "=w,@3Uph,w,w"(<vscale x 16 x i1> %in1, <vscale x 16 x i8> %in2, <vscale x 16 x i8> %in3) 187 SVBOOL_TEST_UPH(__SVInt16_t, h) ; 188 // CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.h, $1.h, $2.h, $3.h\0A", "=w,@3Uph,w,w"(<vscale x 16 x i1> %in1, <vscale x 8 x i16> %in2, <vscale x 8 x i16> %in3) 189 SVBOOL_TEST_UPH(__SVInt32_t, s) ; 190 // CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.s, $1.s, $2.s, $3.s\0A", "=w,@3Uph,w,w"(<vscale x 16 x i1> %in1, <vscale x 4 x i32> %in2, <vscale x 4 x i32> %in3) 191 SVBOOL_TEST_UPH(__SVInt64_t, d) ; 192 // CHECK: call <vscale x 16 x i1> asm sideeffect "fadd $0.d, $1.d, $2.d, $3.d\0A", "=w,@3Uph,w,w"(<vscale x 16 x i1> %in1, <vscale x 2 x i64> %in2, <vscale x 2 x i64> %in3) 193 194 195 #define SVFLOAT_TEST(DT,KIND)\ 196 DT func_float_##DT##KIND(DT inout1, DT in2)\ 197 {\ 198 asm volatile (\ 199 "ptrue p0." #KIND ", #1 \n"\ 200 "fsub %[inout1]." #KIND ", p0/m, %[inout1]." #KIND ", %[in2]." #KIND "\n"\ 201 : [inout1] "=w" (inout1)\ 202 : "[inout1]" (inout1),\ 203 [in2] "w" (in2)\ 204 : "p0");\ 205 return inout1 ;\ 206 }\ 207 208 SVFLOAT_TEST(__SVFloat16_t,s); 209 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.s, #1 \0Afsub $0.s, p0/m, $0.s, $2.s\0A", "=w,0,w,~{p0}"(<vscale x 8 x half> %inout1, <vscale x 8 x half> %in2) 210 SVFLOAT_TEST(__SVFloat16_t,d); 211 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.d, #1 \0Afsub $0.d, p0/m, $0.d, $2.d\0A", "=w,0,w,~{p0}"(<vscale x 8 x half> %inout1, <vscale x 8 x half> %in2) 212 213 SVFLOAT_TEST(__SVFloat32_t,s); 214 // CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.s, #1 \0Afsub $0.s, p0/m, $0.s, $2.s\0A", "=w,0,w,~{p0}"(<vscale x 4 x float> %inout1, <vscale x 4 x float> %in2) 215 SVFLOAT_TEST(__SVFloat32_t,d); 216 // CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.d, #1 \0Afsub $0.d, p0/m, $0.d, $2.d\0A", "=w,0,w,~{p0}"(<vscale x 4 x float> %inout1, <vscale x 4 x float> %in2) 217 218 SVFLOAT_TEST(__SVFloat64_t,s); 219 // CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.s, #1 \0Afsub $0.s, p0/m, $0.s, $2.s\0A", "=w,0,w,~{p0}"(<vscale x 2 x double> %inout1, <vscale x 2 x double> %in2) 220 SVFLOAT_TEST(__SVFloat64_t,d); 221 // CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.d, #1 \0Afsub $0.d, p0/m, $0.d, $2.d\0A", "=w,0,w,~{p0}"(<vscale x 2 x double> %inout1, <vscale x 2 x double> %in2) 222 223 #define SVFLOAT_TEST_Y(DT, KIND)\ 224 __SVBool_t func_float_y_##KIND(DT in1, DT in2)\ 225 {\ 226 __SVBool_t out;\ 227 asm volatile (\ 228 "fmul %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND "\n"\ 229 : [out] "=w" (out)\ 230 : [in1] "w" (in1),\ 231 [in2] "y" (in2)\ 232 :);\ 233 return out;\ 234 } 235 236 SVFLOAT_TEST_Y(__SVFloat16_t,h); 237 // CHECK: call <vscale x 16 x i1> asm sideeffect "fmul $0.h, $1.h, $2.h\0A", "=w,w,y"(<vscale x 8 x half> %in1, <vscale x 8 x half> %in2) 238 SVFLOAT_TEST_Y(__SVFloat32_t,s); 239 // CHECK: call <vscale x 16 x i1> asm sideeffect "fmul $0.s, $1.s, $2.s\0A", "=w,w,y"(<vscale x 4 x float> %in1, <vscale x 4 x float> %in2) 240 SVFLOAT_TEST_Y(__SVFloat64_t,d); 241 // CHECK: call <vscale x 16 x i1> asm sideeffect "fmul $0.d, $1.d, $2.d\0A", "=w,w,y"(<vscale x 2 x double> %in1, <vscale x 2 x double> %in2) 242 243 244 // Another test for floats to include h suffix 245 246 #define SVFLOAT_CVT_TEST(DT1,KIND1,DT2,KIND2)\ 247 DT1 func_float_cvt_##DT1##KIND1##DT2##KIND2(DT2 in1)\ 248 {\ 249 DT1 out1 ;\ 250 asm volatile (\ 251 "ptrue p0." #KIND2 ", #1 \n"\ 252 "fcvt %[out1]." #KIND1 ", p0/m, %[in1]." #KIND2 "\n"\ 253 : [out1] "=w" (out1)\ 254 : [in1] "w" (in1)\ 255 : "p0");\ 256 return out1 ;\ 257 }\ 258 259 SVFLOAT_CVT_TEST(__SVFloat64_t,d,__SVFloat32_t,s); 260 // CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.s, #1 \0Afcvt $0.d, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in1) 261 SVFLOAT_CVT_TEST(__SVFloat64_t,d,__SVFloat16_t,h); 262 // CHECK: call <vscale x 2 x double> asm sideeffect "ptrue p0.h, #1 \0Afcvt $0.d, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in1) 263 SVFLOAT_CVT_TEST(__SVFloat32_t,s,__SVFloat16_t,h); 264 // CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.h, #1 \0Afcvt $0.s, p0/m, $1.h\0A", "=w,w,~{p0}"(<vscale x 8 x half> %in1) 265 SVFLOAT_CVT_TEST(__SVFloat32_t,s,__SVFloat64_t,d); 266 // CHECK: call <vscale x 4 x float> asm sideeffect "ptrue p0.d, #1 \0Afcvt $0.s, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in1) 267 SVFLOAT_CVT_TEST(__SVFloat16_t,h,__SVFloat64_t,d); 268 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.d, #1 \0Afcvt $0.h, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 2 x double> %in1) 269 SVFLOAT_CVT_TEST(__SVFloat16_t,h,__SVFloat32_t,s); 270 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.s, #1 \0Afcvt $0.h, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in1) 271 272 //Test a mix of float and ints 273 SVFLOAT_CVT_TEST(__SVInt16_t,h,__SVFloat32_t,s); 274 // CHECK: call <vscale x 8 x i16> asm sideeffect "ptrue p0.s, #1 \0Afcvt $0.h, p0/m, $1.s\0A", "=w,w,~{p0}"(<vscale x 4 x float> %in1) 275 SVFLOAT_CVT_TEST(__SVFloat16_t,s,__SVUint32_t,d); 276 // CHECK: call <vscale x 8 x half> asm sideeffect "ptrue p0.d, #1 \0Afcvt $0.s, p0/m, $1.d\0A", "=w,w,~{p0}"(<vscale x 4 x i32> %in1) 277