1 //===--- X86.cpp - Implement X86 target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements X86 TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 #include "clang/Basic/Builtins.h" 15 #include "clang/Basic/Diagnostic.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/TargetParser/X86TargetParser.h" 21 #include <optional> 22 23 namespace clang { 24 namespace targets { 25 26 static constexpr Builtin::Info BuiltinInfoX86[] = { 27 #define BUILTIN(ID, TYPE, ATTRS) \ 28 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 29 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 30 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 31 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 32 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, 33 #include "clang/Basic/BuiltinsX86.inc" 34 35 #define BUILTIN(ID, TYPE, ATTRS) \ 36 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 37 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 38 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 39 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 40 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, 41 #include "clang/Basic/BuiltinsX86_64.inc" 42 }; 43 44 static const char *const GCCRegNames[] = { 45 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 46 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 47 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", 48 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", 49 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", 50 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", 51 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", 52 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", 53 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", 54 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", 55 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", 56 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", 57 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", 58 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", 59 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", 60 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", 61 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", 62 "k2", "k3", "k4", "k5", "k6", "k7", 63 "cr0", "cr2", "cr3", "cr4", "cr8", 64 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", 65 "bnd0", "bnd1", "bnd2", "bnd3", 66 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", 67 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 68 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 69 }; 70 71 const TargetInfo::AddlRegName AddlRegNames[] = { 72 {{"al", "ah", "eax", "rax"}, 0}, 73 {{"bl", "bh", "ebx", "rbx"}, 3}, 74 {{"cl", "ch", "ecx", "rcx"}, 2}, 75 {{"dl", "dh", "edx", "rdx"}, 1}, 76 {{"esi", "rsi"}, 4}, 77 {{"edi", "rdi"}, 5}, 78 {{"esp", "rsp"}, 7}, 79 {{"ebp", "rbp"}, 6}, 80 {{"r8d", "r8w", "r8b"}, 38}, 81 {{"r9d", "r9w", "r9b"}, 39}, 82 {{"r10d", "r10w", "r10b"}, 40}, 83 {{"r11d", "r11w", "r11b"}, 41}, 84 {{"r12d", "r12w", "r12b"}, 42}, 85 {{"r13d", "r13w", "r13b"}, 43}, 86 {{"r14d", "r14w", "r14b"}, 44}, 87 {{"r15d", "r15w", "r15b"}, 45}, 88 {{"r16d", "r16w", "r16b"}, 165}, 89 {{"r17d", "r17w", "r17b"}, 166}, 90 {{"r18d", "r18w", "r18b"}, 167}, 91 {{"r19d", "r19w", "r19b"}, 168}, 92 {{"r20d", "r20w", "r20b"}, 169}, 93 {{"r21d", "r21w", "r21b"}, 170}, 94 {{"r22d", "r22w", "r22b"}, 171}, 95 {{"r23d", "r23w", "r23b"}, 172}, 96 {{"r24d", "r24w", "r24b"}, 173}, 97 {{"r25d", "r25w", "r25b"}, 174}, 98 {{"r26d", "r26w", "r26b"}, 175}, 99 {{"r27d", "r27w", "r27b"}, 176}, 100 {{"r28d", "r28w", "r28b"}, 177}, 101 {{"r29d", "r29w", "r29b"}, 178}, 102 {{"r30d", "r30w", "r30b"}, 179}, 103 {{"r31d", "r31w", "r31b"}, 180}, 104 }; 105 } // namespace targets 106 } // namespace clang 107 108 using namespace clang; 109 using namespace clang::targets; 110 111 bool X86TargetInfo::setFPMath(StringRef Name) { 112 if (Name == "387") { 113 FPMath = FP_387; 114 return true; 115 } 116 if (Name == "sse") { 117 FPMath = FP_SSE; 118 return true; 119 } 120 return false; 121 } 122 123 bool X86TargetInfo::initFeatureMap( 124 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 125 const std::vector<std::string> &FeaturesVec) const { 126 // FIXME: This *really* should not be here. 127 // X86_64 always has SSE2. 128 if (getTriple().getArch() == llvm::Triple::x86_64) 129 setFeatureEnabled(Features, "sse2", true); 130 131 using namespace llvm::X86; 132 133 SmallVector<StringRef, 16> CPUFeatures; 134 getFeaturesForCPU(CPU, CPUFeatures); 135 for (auto &F : CPUFeatures) 136 setFeatureEnabled(Features, F, true); 137 138 std::vector<std::string> UpdatedFeaturesVec; 139 std::vector<std::string> UpdatedAVX10FeaturesVec; 140 enum { FE_NOSET = -1, FE_FALSE, FE_TRUE }; 141 int HasEVEX512 = FE_NOSET; 142 bool HasAVX512F = Features.lookup("avx512f"); 143 bool HasAVX10 = Features.lookup("avx10.1-256"); 144 bool HasAVX10_512 = Features.lookup("avx10.1-512"); 145 std::string LastAVX10; 146 std::string LastAVX512; 147 for (const auto &Feature : FeaturesVec) { 148 // Expand general-regs-only to -x86, -mmx and -sse 149 if (Feature == "+general-regs-only") { 150 UpdatedFeaturesVec.push_back("-x87"); 151 UpdatedFeaturesVec.push_back("-mmx"); 152 UpdatedFeaturesVec.push_back("-sse"); 153 continue; 154 } 155 156 if (Feature.substr(1, 6) == "avx10.") { 157 if (Feature[0] == '+') { 158 HasAVX10 = true; 159 if (StringRef(Feature).ends_with("512")) 160 HasAVX10_512 = true; 161 LastAVX10 = Feature; 162 } else if (HasAVX10 && Feature == "-avx10.1-256") { 163 HasAVX10 = false; 164 HasAVX10_512 = false; 165 } else if (HasAVX10_512 && Feature == "-avx10.1-512") { 166 HasAVX10_512 = false; 167 } 168 // Postpone AVX10 features handling after AVX512 settled. 169 UpdatedAVX10FeaturesVec.push_back(Feature); 170 continue; 171 } else if (!HasAVX512F && StringRef(Feature).starts_with("+avx512")) { 172 HasAVX512F = true; 173 LastAVX512 = Feature; 174 } else if (HasAVX512F && Feature == "-avx512f") { 175 HasAVX512F = false; 176 } else if (HasEVEX512 != FE_TRUE && Feature == "+evex512") { 177 HasEVEX512 = FE_TRUE; 178 continue; 179 } else if (HasEVEX512 != FE_FALSE && Feature == "-evex512") { 180 HasEVEX512 = FE_FALSE; 181 continue; 182 } 183 184 UpdatedFeaturesVec.push_back(Feature); 185 } 186 llvm::append_range(UpdatedFeaturesVec, UpdatedAVX10FeaturesVec); 187 // HasEVEX512 is a three-states flag. We need to turn it into [+-]evex512 188 // according to other features. 189 if (!HasAVX10_512 && HasAVX512F) { 190 UpdatedFeaturesVec.push_back(HasEVEX512 == FE_FALSE ? "-evex512" 191 : "+evex512"); 192 if (HasAVX10 && HasEVEX512 != FE_FALSE) 193 Diags.Report(diag::warn_invalid_feature_combination) 194 << LastAVX512 + " " + LastAVX10 + "; will be promoted to avx10.1-512"; 195 } else if (HasAVX10) { 196 if (!HasAVX512F && HasEVEX512 != FE_NOSET) 197 Diags.Report(diag::warn_invalid_feature_combination) 198 << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512"); 199 UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512"); 200 } 201 202 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) 203 return false; 204 205 // Can't do this earlier because we need to be able to explicitly enable 206 // or disable these features and the things that they depend upon. 207 208 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 209 auto I = Features.find("sse4.2"); 210 if (I != Features.end() && I->getValue() && 211 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) 212 Features["popcnt"] = true; 213 214 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 215 // then enable MMX. 216 I = Features.find("sse"); 217 if (I != Features.end() && I->getValue() && 218 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) 219 Features["mmx"] = true; 220 221 // Enable xsave if avx is enabled and xsave is not explicitly disabled. 222 I = Features.find("avx"); 223 if (I != Features.end() && I->getValue() && 224 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) 225 Features["xsave"] = true; 226 227 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled. 228 I = Features.find("sse4.2"); 229 if (I != Features.end() && I->getValue() && 230 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) 231 Features["crc32"] = true; 232 233 return true; 234 } 235 236 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 237 StringRef Name, bool Enabled) const { 238 if (Name == "sse4") { 239 // We can get here via the __target__ attribute since that's not controlled 240 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 241 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 242 // disabled. 243 if (Enabled) 244 Name = "sse4.2"; 245 else 246 Name = "sse4.1"; 247 } 248 249 Features[Name] = Enabled; 250 llvm::X86::updateImpliedFeatures(Name, Enabled, Features); 251 } 252 253 /// handleTargetFeatures - Perform initialization based on the user 254 /// configured set of features. 255 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 256 DiagnosticsEngine &Diags) { 257 for (const auto &Feature : Features) { 258 if (Feature[0] != '+') 259 continue; 260 261 if (Feature == "+mmx") { 262 HasMMX = true; 263 } else if (Feature == "+aes") { 264 HasAES = true; 265 } else if (Feature == "+vaes") { 266 HasVAES = true; 267 } else if (Feature == "+pclmul") { 268 HasPCLMUL = true; 269 } else if (Feature == "+vpclmulqdq") { 270 HasVPCLMULQDQ = true; 271 } else if (Feature == "+lzcnt") { 272 HasLZCNT = true; 273 } else if (Feature == "+rdrnd") { 274 HasRDRND = true; 275 } else if (Feature == "+fsgsbase") { 276 HasFSGSBASE = true; 277 } else if (Feature == "+bmi") { 278 HasBMI = true; 279 } else if (Feature == "+bmi2") { 280 HasBMI2 = true; 281 } else if (Feature == "+popcnt") { 282 HasPOPCNT = true; 283 } else if (Feature == "+rtm") { 284 HasRTM = true; 285 } else if (Feature == "+prfchw") { 286 HasPRFCHW = true; 287 } else if (Feature == "+rdseed") { 288 HasRDSEED = true; 289 } else if (Feature == "+adx") { 290 HasADX = true; 291 } else if (Feature == "+tbm") { 292 HasTBM = true; 293 } else if (Feature == "+lwp") { 294 HasLWP = true; 295 } else if (Feature == "+fma") { 296 HasFMA = true; 297 } else if (Feature == "+f16c") { 298 HasF16C = true; 299 } else if (Feature == "+gfni") { 300 HasGFNI = true; 301 } else if (Feature == "+evex512") { 302 HasEVEX512 = true; 303 } else if (Feature == "+avx10.1-256") { 304 HasAVX10_1 = true; 305 } else if (Feature == "+avx10.1-512") { 306 HasAVX10_1_512 = true; 307 } else if (Feature == "+avx10.2-256") { 308 HasAVX10_2 = true; 309 HasFullBFloat16 = true; 310 } else if (Feature == "+avx10.2-512") { 311 HasAVX10_2_512 = true; 312 } else if (Feature == "+avx512cd") { 313 HasAVX512CD = true; 314 } else if (Feature == "+avx512vpopcntdq") { 315 HasAVX512VPOPCNTDQ = true; 316 } else if (Feature == "+avx512vnni") { 317 HasAVX512VNNI = true; 318 } else if (Feature == "+avx512bf16") { 319 HasAVX512BF16 = true; 320 } else if (Feature == "+avx512fp16") { 321 HasAVX512FP16 = true; 322 HasLegalHalfType = true; 323 } else if (Feature == "+avx512dq") { 324 HasAVX512DQ = true; 325 } else if (Feature == "+avx512bitalg") { 326 HasAVX512BITALG = true; 327 } else if (Feature == "+avx512bw") { 328 HasAVX512BW = true; 329 } else if (Feature == "+avx512vl") { 330 HasAVX512VL = true; 331 } else if (Feature == "+avx512vbmi") { 332 HasAVX512VBMI = true; 333 } else if (Feature == "+avx512vbmi2") { 334 HasAVX512VBMI2 = true; 335 } else if (Feature == "+avx512ifma") { 336 HasAVX512IFMA = true; 337 } else if (Feature == "+avx512vp2intersect") { 338 HasAVX512VP2INTERSECT = true; 339 } else if (Feature == "+sha") { 340 HasSHA = true; 341 } else if (Feature == "+sha512") { 342 HasSHA512 = true; 343 } else if (Feature == "+shstk") { 344 HasSHSTK = true; 345 } else if (Feature == "+sm3") { 346 HasSM3 = true; 347 } else if (Feature == "+sm4") { 348 HasSM4 = true; 349 } else if (Feature == "+movbe") { 350 HasMOVBE = true; 351 } else if (Feature == "+movrs") { 352 HasMOVRS = true; 353 } else if (Feature == "+sgx") { 354 HasSGX = true; 355 } else if (Feature == "+cx8") { 356 HasCX8 = true; 357 } else if (Feature == "+cx16") { 358 HasCX16 = true; 359 } else if (Feature == "+fxsr") { 360 HasFXSR = true; 361 } else if (Feature == "+xsave") { 362 HasXSAVE = true; 363 } else if (Feature == "+xsaveopt") { 364 HasXSAVEOPT = true; 365 } else if (Feature == "+xsavec") { 366 HasXSAVEC = true; 367 } else if (Feature == "+xsaves") { 368 HasXSAVES = true; 369 } else if (Feature == "+mwaitx") { 370 HasMWAITX = true; 371 } else if (Feature == "+pku") { 372 HasPKU = true; 373 } else if (Feature == "+clflushopt") { 374 HasCLFLUSHOPT = true; 375 } else if (Feature == "+clwb") { 376 HasCLWB = true; 377 } else if (Feature == "+wbnoinvd") { 378 HasWBNOINVD = true; 379 } else if (Feature == "+prefetchi") { 380 HasPREFETCHI = true; 381 } else if (Feature == "+clzero") { 382 HasCLZERO = true; 383 } else if (Feature == "+cldemote") { 384 HasCLDEMOTE = true; 385 } else if (Feature == "+rdpid") { 386 HasRDPID = true; 387 } else if (Feature == "+rdpru") { 388 HasRDPRU = true; 389 } else if (Feature == "+kl") { 390 HasKL = true; 391 } else if (Feature == "+widekl") { 392 HasWIDEKL = true; 393 } else if (Feature == "+retpoline-external-thunk") { 394 HasRetpolineExternalThunk = true; 395 } else if (Feature == "+sahf") { 396 HasLAHFSAHF = true; 397 } else if (Feature == "+waitpkg") { 398 HasWAITPKG = true; 399 } else if (Feature == "+movdiri") { 400 HasMOVDIRI = true; 401 } else if (Feature == "+movdir64b") { 402 HasMOVDIR64B = true; 403 } else if (Feature == "+pconfig") { 404 HasPCONFIG = true; 405 } else if (Feature == "+ptwrite") { 406 HasPTWRITE = true; 407 } else if (Feature == "+invpcid") { 408 HasINVPCID = true; 409 } else if (Feature == "+enqcmd") { 410 HasENQCMD = true; 411 } else if (Feature == "+hreset") { 412 HasHRESET = true; 413 } else if (Feature == "+amx-bf16") { 414 HasAMXBF16 = true; 415 } else if (Feature == "+amx-fp16") { 416 HasAMXFP16 = true; 417 } else if (Feature == "+amx-int8") { 418 HasAMXINT8 = true; 419 } else if (Feature == "+amx-tile") { 420 HasAMXTILE = true; 421 } else if (Feature == "+amx-complex") { 422 HasAMXCOMPLEX = true; 423 } else if (Feature == "+amx-fp8") { 424 HasAMXFP8 = true; 425 } else if (Feature == "+amx-movrs") { 426 HasAMXMOVRS = true; 427 } else if (Feature == "+amx-transpose") { 428 HasAMXTRANSPOSE = true; 429 } else if (Feature == "+amx-avx512") { 430 HasAMXAVX512 = true; 431 } else if (Feature == "+amx-tf32") { 432 HasAMXTF32 = true; 433 } else if (Feature == "+cmpccxadd") { 434 HasCMPCCXADD = true; 435 } else if (Feature == "+raoint") { 436 HasRAOINT = true; 437 } else if (Feature == "+avxifma") { 438 HasAVXIFMA = true; 439 } else if (Feature == "+avxneconvert") { 440 HasAVXNECONVERT= true; 441 } else if (Feature == "+avxvnni") { 442 HasAVXVNNI = true; 443 } else if (Feature == "+avxvnniint16") { 444 HasAVXVNNIINT16 = true; 445 } else if (Feature == "+avxvnniint8") { 446 HasAVXVNNIINT8 = true; 447 } else if (Feature == "+serialize") { 448 HasSERIALIZE = true; 449 } else if (Feature == "+tsxldtrk") { 450 HasTSXLDTRK = true; 451 } else if (Feature == "+uintr") { 452 HasUINTR = true; 453 } else if (Feature == "+usermsr") { 454 HasUSERMSR = true; 455 } else if (Feature == "+crc32") { 456 HasCRC32 = true; 457 } else if (Feature == "+x87") { 458 HasX87 = true; 459 } else if (Feature == "+fullbf16") { 460 HasFullBFloat16 = true; 461 } else if (Feature == "+egpr") { 462 HasEGPR = true; 463 } else if (Feature == "+inline-asm-use-gpr32") { 464 HasInlineAsmUseGPR32 = true; 465 } else if (Feature == "+push2pop2") { 466 HasPush2Pop2 = true; 467 } else if (Feature == "+ppx") { 468 HasPPX = true; 469 } else if (Feature == "+ndd") { 470 HasNDD = true; 471 } else if (Feature == "+ccmp") { 472 HasCCMP = true; 473 } else if (Feature == "+nf") { 474 HasNF = true; 475 } else if (Feature == "+cf") { 476 HasCF = true; 477 } else if (Feature == "+zu") { 478 HasZU = true; 479 } else if (Feature == "+branch-hint") { 480 HasBranchHint = true; 481 } 482 483 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 484 .Case("+avx512f", AVX512F) 485 .Case("+avx2", AVX2) 486 .Case("+avx", AVX) 487 .Case("+sse4.2", SSE42) 488 .Case("+sse4.1", SSE41) 489 .Case("+ssse3", SSSE3) 490 .Case("+sse3", SSE3) 491 .Case("+sse2", SSE2) 492 .Case("+sse", SSE1) 493 .Default(NoSSE); 494 SSELevel = std::max(SSELevel, Level); 495 496 HasFloat16 = SSELevel >= SSE2; 497 498 // X86 target has bfloat16 emulation support in the backend, where 499 // bfloat16 is treated as a 32-bit float, arithmetic operations are 500 // performed in 32-bit, and the result is converted back to bfloat16. 501 // Truncation and extension between bfloat16 and 32-bit float are supported 502 // by the compiler-rt library. However, native bfloat16 support is currently 503 // not available in the X86 target. Hence, HasFullBFloat16 will be false 504 // until native bfloat16 support is available. HasFullBFloat16 is used to 505 // determine whether to automatically use excess floating point precision 506 // for bfloat16 arithmetic operations in the front-end. 507 HasBFloat16 = SSELevel >= SSE2; 508 509 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 510 .Case("+xop", XOP) 511 .Case("+fma4", FMA4) 512 .Case("+sse4a", SSE4A) 513 .Default(NoXOP); 514 XOPLevel = std::max(XOPLevel, XLevel); 515 } 516 517 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 518 // matches the selected sse level. 519 if ((FPMath == FP_SSE && SSELevel < SSE1) || 520 (FPMath == FP_387 && SSELevel >= SSE1)) { 521 Diags.Report(diag::err_target_unsupported_fpmath) 522 << (FPMath == FP_SSE ? "sse" : "387"); 523 return false; 524 } 525 526 // FIXME: We should allow long double type on 32-bits to match with GCC. 527 // This requires backend to be able to lower f80 without x87 first. 528 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended()) 529 HasLongDouble = false; 530 531 return true; 532 } 533 534 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 535 /// definitions for this particular subtarget. 536 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 537 MacroBuilder &Builder) const { 538 // Inline assembly supports X86 flag outputs. 539 Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); 540 541 std::string CodeModel = getTargetOpts().CodeModel; 542 if (CodeModel == "default") 543 CodeModel = "small"; 544 Builder.defineMacro("__code_model_" + CodeModel + "__"); 545 546 // Target identification. 547 if (getTriple().getArch() == llvm::Triple::x86_64) { 548 Builder.defineMacro("__amd64__"); 549 Builder.defineMacro("__amd64"); 550 Builder.defineMacro("__x86_64"); 551 Builder.defineMacro("__x86_64__"); 552 if (getTriple().getArchName() == "x86_64h") { 553 Builder.defineMacro("__x86_64h"); 554 Builder.defineMacro("__x86_64h__"); 555 } 556 } else { 557 DefineStd(Builder, "i386", Opts); 558 } 559 560 Builder.defineMacro("__SEG_GS"); 561 Builder.defineMacro("__SEG_FS"); 562 Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); 563 Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); 564 565 // Subtarget options. 566 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 567 // truly should be based on -mtune options. 568 using namespace llvm::X86; 569 switch (CPU) { 570 case CK_None: 571 break; 572 case CK_i386: 573 // The rest are coming from the i386 define above. 574 Builder.defineMacro("__tune_i386__"); 575 break; 576 case CK_i486: 577 case CK_WinChipC6: 578 case CK_WinChip2: 579 case CK_C3: 580 defineCPUMacros(Builder, "i486"); 581 break; 582 case CK_PentiumMMX: 583 Builder.defineMacro("__pentium_mmx__"); 584 Builder.defineMacro("__tune_pentium_mmx__"); 585 [[fallthrough]]; 586 case CK_i586: 587 case CK_Pentium: 588 defineCPUMacros(Builder, "i586"); 589 defineCPUMacros(Builder, "pentium"); 590 break; 591 case CK_Pentium3: 592 case CK_PentiumM: 593 Builder.defineMacro("__tune_pentium3__"); 594 [[fallthrough]]; 595 case CK_Pentium2: 596 case CK_C3_2: 597 Builder.defineMacro("__tune_pentium2__"); 598 [[fallthrough]]; 599 case CK_PentiumPro: 600 case CK_i686: 601 defineCPUMacros(Builder, "i686"); 602 defineCPUMacros(Builder, "pentiumpro"); 603 break; 604 case CK_Pentium4: 605 defineCPUMacros(Builder, "pentium4"); 606 break; 607 case CK_Yonah: 608 case CK_Prescott: 609 case CK_Nocona: 610 defineCPUMacros(Builder, "nocona"); 611 break; 612 case CK_Core2: 613 case CK_Penryn: 614 defineCPUMacros(Builder, "core2"); 615 break; 616 case CK_Bonnell: 617 defineCPUMacros(Builder, "atom"); 618 break; 619 case CK_Silvermont: 620 defineCPUMacros(Builder, "slm"); 621 break; 622 case CK_Goldmont: 623 defineCPUMacros(Builder, "goldmont"); 624 break; 625 case CK_GoldmontPlus: 626 defineCPUMacros(Builder, "goldmont_plus"); 627 break; 628 case CK_Tremont: 629 defineCPUMacros(Builder, "tremont"); 630 break; 631 // Gracemont and later atom-cores use P-core cpu macros. 632 case CK_Gracemont: 633 case CK_Nehalem: 634 case CK_Westmere: 635 case CK_SandyBridge: 636 case CK_IvyBridge: 637 case CK_Haswell: 638 case CK_Broadwell: 639 case CK_SkylakeClient: 640 case CK_SkylakeServer: 641 case CK_Cascadelake: 642 case CK_Cooperlake: 643 case CK_Cannonlake: 644 case CK_IcelakeClient: 645 case CK_Rocketlake: 646 case CK_IcelakeServer: 647 case CK_Tigerlake: 648 case CK_SapphireRapids: 649 case CK_Alderlake: 650 case CK_Raptorlake: 651 case CK_Meteorlake: 652 case CK_Arrowlake: 653 case CK_ArrowlakeS: 654 case CK_Lunarlake: 655 case CK_Pantherlake: 656 case CK_Sierraforest: 657 case CK_Grandridge: 658 case CK_Graniterapids: 659 case CK_GraniterapidsD: 660 case CK_Emeraldrapids: 661 case CK_Clearwaterforest: 662 case CK_Diamondrapids: 663 // FIXME: Historically, we defined this legacy name, it would be nice to 664 // remove it at some point. We've never exposed fine-grained names for 665 // recent primary x86 CPUs, and we should keep it that way. 666 defineCPUMacros(Builder, "corei7"); 667 break; 668 case CK_KNL: 669 defineCPUMacros(Builder, "knl"); 670 break; 671 case CK_KNM: 672 break; 673 case CK_Lakemont: 674 defineCPUMacros(Builder, "i586", /*Tuning*/false); 675 defineCPUMacros(Builder, "pentium", /*Tuning*/false); 676 Builder.defineMacro("__tune_lakemont__"); 677 break; 678 case CK_K6_2: 679 Builder.defineMacro("__k6_2__"); 680 Builder.defineMacro("__tune_k6_2__"); 681 [[fallthrough]]; 682 case CK_K6_3: 683 if (CPU != CK_K6_2) { // In case of fallthrough 684 // FIXME: GCC may be enabling these in cases where some other k6 685 // architecture is specified but -m3dnow is explicitly provided. The 686 // exact semantics need to be determined and emulated here. 687 Builder.defineMacro("__k6_3__"); 688 Builder.defineMacro("__tune_k6_3__"); 689 } 690 [[fallthrough]]; 691 case CK_K6: 692 defineCPUMacros(Builder, "k6"); 693 break; 694 case CK_Athlon: 695 case CK_AthlonXP: 696 defineCPUMacros(Builder, "athlon"); 697 if (SSELevel != NoSSE) { 698 Builder.defineMacro("__athlon_sse__"); 699 Builder.defineMacro("__tune_athlon_sse__"); 700 } 701 break; 702 case CK_K8: 703 case CK_K8SSE3: 704 case CK_x86_64: 705 defineCPUMacros(Builder, "k8"); 706 break; 707 case CK_x86_64_v2: 708 case CK_x86_64_v3: 709 case CK_x86_64_v4: 710 break; 711 case CK_AMDFAM10: 712 defineCPUMacros(Builder, "amdfam10"); 713 break; 714 case CK_BTVER1: 715 defineCPUMacros(Builder, "btver1"); 716 break; 717 case CK_BTVER2: 718 defineCPUMacros(Builder, "btver2"); 719 break; 720 case CK_BDVER1: 721 defineCPUMacros(Builder, "bdver1"); 722 break; 723 case CK_BDVER2: 724 defineCPUMacros(Builder, "bdver2"); 725 break; 726 case CK_BDVER3: 727 defineCPUMacros(Builder, "bdver3"); 728 break; 729 case CK_BDVER4: 730 defineCPUMacros(Builder, "bdver4"); 731 break; 732 case CK_ZNVER1: 733 defineCPUMacros(Builder, "znver1"); 734 break; 735 case CK_ZNVER2: 736 defineCPUMacros(Builder, "znver2"); 737 break; 738 case CK_ZNVER3: 739 defineCPUMacros(Builder, "znver3"); 740 break; 741 case CK_ZNVER4: 742 defineCPUMacros(Builder, "znver4"); 743 break; 744 case CK_ZNVER5: 745 defineCPUMacros(Builder, "znver5"); 746 break; 747 case CK_Geode: 748 defineCPUMacros(Builder, "geode"); 749 break; 750 } 751 752 // Target properties. 753 Builder.defineMacro("__REGISTER_PREFIX__", ""); 754 755 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 756 // functions in glibc header files that use FP Stack inline asm which the 757 // backend can't deal with (PR879). 758 Builder.defineMacro("__NO_MATH_INLINES"); 759 760 if (HasAES) 761 Builder.defineMacro("__AES__"); 762 763 if (HasVAES) 764 Builder.defineMacro("__VAES__"); 765 766 if (HasPCLMUL) 767 Builder.defineMacro("__PCLMUL__"); 768 769 if (HasVPCLMULQDQ) 770 Builder.defineMacro("__VPCLMULQDQ__"); 771 772 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, 773 // the feature flag only applies to 64-bit mode. 774 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86) 775 Builder.defineMacro("__LAHF_SAHF__"); 776 777 if (HasLZCNT) 778 Builder.defineMacro("__LZCNT__"); 779 780 if (HasRDRND) 781 Builder.defineMacro("__RDRND__"); 782 783 if (HasFSGSBASE) 784 Builder.defineMacro("__FSGSBASE__"); 785 786 if (HasBMI) 787 Builder.defineMacro("__BMI__"); 788 789 if (HasBMI2) 790 Builder.defineMacro("__BMI2__"); 791 792 if (HasPOPCNT) 793 Builder.defineMacro("__POPCNT__"); 794 795 if (HasRTM) 796 Builder.defineMacro("__RTM__"); 797 798 if (HasPRFCHW) 799 Builder.defineMacro("__PRFCHW__"); 800 801 if (HasRDSEED) 802 Builder.defineMacro("__RDSEED__"); 803 804 if (HasADX) 805 Builder.defineMacro("__ADX__"); 806 807 if (HasTBM) 808 Builder.defineMacro("__TBM__"); 809 810 if (HasLWP) 811 Builder.defineMacro("__LWP__"); 812 813 if (HasMWAITX) 814 Builder.defineMacro("__MWAITX__"); 815 816 if (HasMOVBE) 817 Builder.defineMacro("__MOVBE__"); 818 819 switch (XOPLevel) { 820 case XOP: 821 Builder.defineMacro("__XOP__"); 822 [[fallthrough]]; 823 case FMA4: 824 Builder.defineMacro("__FMA4__"); 825 [[fallthrough]]; 826 case SSE4A: 827 Builder.defineMacro("__SSE4A__"); 828 [[fallthrough]]; 829 case NoXOP: 830 break; 831 } 832 833 if (HasFMA) 834 Builder.defineMacro("__FMA__"); 835 836 if (HasF16C) 837 Builder.defineMacro("__F16C__"); 838 839 if (HasGFNI) 840 Builder.defineMacro("__GFNI__"); 841 842 if (HasEVEX512) 843 Builder.defineMacro("__EVEX512__"); 844 if (HasAVX10_1) 845 Builder.defineMacro("__AVX10_1__"); 846 if (HasAVX10_1_512) 847 Builder.defineMacro("__AVX10_1_512__"); 848 if (HasAVX10_2) 849 Builder.defineMacro("__AVX10_2__"); 850 if (HasAVX10_2_512) 851 Builder.defineMacro("__AVX10_2_512__"); 852 if (HasAVX512CD) 853 Builder.defineMacro("__AVX512CD__"); 854 if (HasAVX512VPOPCNTDQ) 855 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 856 if (HasAVX512VNNI) 857 Builder.defineMacro("__AVX512VNNI__"); 858 if (HasAVX512BF16) 859 Builder.defineMacro("__AVX512BF16__"); 860 if (HasAVX512FP16) 861 Builder.defineMacro("__AVX512FP16__"); 862 if (HasAVX512DQ) 863 Builder.defineMacro("__AVX512DQ__"); 864 if (HasAVX512BITALG) 865 Builder.defineMacro("__AVX512BITALG__"); 866 if (HasAVX512BW) 867 Builder.defineMacro("__AVX512BW__"); 868 if (HasAVX512VL) { 869 Builder.defineMacro("__AVX512VL__"); 870 Builder.defineMacro("__EVEX256__"); 871 } 872 if (HasAVX512VBMI) 873 Builder.defineMacro("__AVX512VBMI__"); 874 if (HasAVX512VBMI2) 875 Builder.defineMacro("__AVX512VBMI2__"); 876 if (HasAVX512IFMA) 877 Builder.defineMacro("__AVX512IFMA__"); 878 if (HasAVX512VP2INTERSECT) 879 Builder.defineMacro("__AVX512VP2INTERSECT__"); 880 if (HasSHA) 881 Builder.defineMacro("__SHA__"); 882 if (HasSHA512) 883 Builder.defineMacro("__SHA512__"); 884 885 if (HasFXSR) 886 Builder.defineMacro("__FXSR__"); 887 if (HasXSAVE) 888 Builder.defineMacro("__XSAVE__"); 889 if (HasXSAVEOPT) 890 Builder.defineMacro("__XSAVEOPT__"); 891 if (HasXSAVEC) 892 Builder.defineMacro("__XSAVEC__"); 893 if (HasXSAVES) 894 Builder.defineMacro("__XSAVES__"); 895 if (HasPKU) 896 Builder.defineMacro("__PKU__"); 897 if (HasCLFLUSHOPT) 898 Builder.defineMacro("__CLFLUSHOPT__"); 899 if (HasCLWB) 900 Builder.defineMacro("__CLWB__"); 901 if (HasWBNOINVD) 902 Builder.defineMacro("__WBNOINVD__"); 903 if (HasSHSTK) 904 Builder.defineMacro("__SHSTK__"); 905 if (HasSGX) 906 Builder.defineMacro("__SGX__"); 907 if (HasSM3) 908 Builder.defineMacro("__SM3__"); 909 if (HasSM4) 910 Builder.defineMacro("__SM4__"); 911 if (HasPREFETCHI) 912 Builder.defineMacro("__PREFETCHI__"); 913 if (HasCLZERO) 914 Builder.defineMacro("__CLZERO__"); 915 if (HasKL) 916 Builder.defineMacro("__KL__"); 917 if (HasWIDEKL) 918 Builder.defineMacro("__WIDEKL__"); 919 if (HasRDPID) 920 Builder.defineMacro("__RDPID__"); 921 if (HasRDPRU) 922 Builder.defineMacro("__RDPRU__"); 923 if (HasCLDEMOTE) 924 Builder.defineMacro("__CLDEMOTE__"); 925 if (HasWAITPKG) 926 Builder.defineMacro("__WAITPKG__"); 927 if (HasMOVDIRI) 928 Builder.defineMacro("__MOVDIRI__"); 929 if (HasMOVDIR64B) 930 Builder.defineMacro("__MOVDIR64B__"); 931 if (HasMOVRS) 932 Builder.defineMacro("__MOVRS__"); 933 if (HasPCONFIG) 934 Builder.defineMacro("__PCONFIG__"); 935 if (HasPTWRITE) 936 Builder.defineMacro("__PTWRITE__"); 937 if (HasINVPCID) 938 Builder.defineMacro("__INVPCID__"); 939 if (HasENQCMD) 940 Builder.defineMacro("__ENQCMD__"); 941 if (HasHRESET) 942 Builder.defineMacro("__HRESET__"); 943 if (HasAMXTILE) 944 Builder.defineMacro("__AMX_TILE__"); 945 if (HasAMXINT8) 946 Builder.defineMacro("__AMX_INT8__"); 947 if (HasAMXBF16) 948 Builder.defineMacro("__AMX_BF16__"); 949 if (HasAMXFP16) 950 Builder.defineMacro("__AMX_FP16__"); 951 if (HasAMXCOMPLEX) 952 Builder.defineMacro("__AMX_COMPLEX__"); 953 if (HasAMXFP8) 954 Builder.defineMacro("__AMX_FP8__"); 955 if (HasAMXMOVRS) 956 Builder.defineMacro("__AMX_MOVRS__"); 957 if (HasAMXTRANSPOSE) 958 Builder.defineMacro("__AMX_TRANSPOSE__"); 959 if (HasAMXAVX512) 960 Builder.defineMacro("__AMX_AVX512__"); 961 if (HasAMXTF32) 962 Builder.defineMacro("__AMX_TF32__"); 963 if (HasCMPCCXADD) 964 Builder.defineMacro("__CMPCCXADD__"); 965 if (HasRAOINT) 966 Builder.defineMacro("__RAOINT__"); 967 if (HasAVXIFMA) 968 Builder.defineMacro("__AVXIFMA__"); 969 if (HasAVXNECONVERT) 970 Builder.defineMacro("__AVXNECONVERT__"); 971 if (HasAVXVNNI) 972 Builder.defineMacro("__AVXVNNI__"); 973 if (HasAVXVNNIINT16) 974 Builder.defineMacro("__AVXVNNIINT16__"); 975 if (HasAVXVNNIINT8) 976 Builder.defineMacro("__AVXVNNIINT8__"); 977 if (HasSERIALIZE) 978 Builder.defineMacro("__SERIALIZE__"); 979 if (HasTSXLDTRK) 980 Builder.defineMacro("__TSXLDTRK__"); 981 if (HasUINTR) 982 Builder.defineMacro("__UINTR__"); 983 if (HasUSERMSR) 984 Builder.defineMacro("__USERMSR__"); 985 if (HasCRC32) 986 Builder.defineMacro("__CRC32__"); 987 if (HasEGPR) 988 Builder.defineMacro("__EGPR__"); 989 if (HasPush2Pop2) 990 Builder.defineMacro("__PUSH2POP2__"); 991 if (HasPPX) 992 Builder.defineMacro("__PPX__"); 993 if (HasNDD) 994 Builder.defineMacro("__NDD__"); 995 if (HasCCMP) 996 Builder.defineMacro("__CCMP__"); 997 if (HasNF) 998 Builder.defineMacro("__NF__"); 999 if (HasCF) 1000 Builder.defineMacro("__CF__"); 1001 if (HasZU) 1002 Builder.defineMacro("__ZU__"); 1003 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF && 1004 HasCF && HasZU) 1005 Builder.defineMacro("__APX_F__"); 1006 if (HasEGPR && HasInlineAsmUseGPR32) 1007 Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__"); 1008 1009 // Each case falls through to the previous one here. 1010 switch (SSELevel) { 1011 case AVX512F: 1012 Builder.defineMacro("__AVX512F__"); 1013 [[fallthrough]]; 1014 case AVX2: 1015 Builder.defineMacro("__AVX2__"); 1016 [[fallthrough]]; 1017 case AVX: 1018 Builder.defineMacro("__AVX__"); 1019 [[fallthrough]]; 1020 case SSE42: 1021 Builder.defineMacro("__SSE4_2__"); 1022 [[fallthrough]]; 1023 case SSE41: 1024 Builder.defineMacro("__SSE4_1__"); 1025 [[fallthrough]]; 1026 case SSSE3: 1027 Builder.defineMacro("__SSSE3__"); 1028 [[fallthrough]]; 1029 case SSE3: 1030 Builder.defineMacro("__SSE3__"); 1031 [[fallthrough]]; 1032 case SSE2: 1033 Builder.defineMacro("__SSE2__"); 1034 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 1035 [[fallthrough]]; 1036 case SSE1: 1037 Builder.defineMacro("__SSE__"); 1038 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 1039 [[fallthrough]]; 1040 case NoSSE: 1041 break; 1042 } 1043 1044 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 1045 switch (SSELevel) { 1046 case AVX512F: 1047 case AVX2: 1048 case AVX: 1049 case SSE42: 1050 case SSE41: 1051 case SSSE3: 1052 case SSE3: 1053 case SSE2: 1054 Builder.defineMacro("_M_IX86_FP", Twine(2)); 1055 break; 1056 case SSE1: 1057 Builder.defineMacro("_M_IX86_FP", Twine(1)); 1058 break; 1059 default: 1060 Builder.defineMacro("_M_IX86_FP", Twine(0)); 1061 break; 1062 } 1063 } 1064 1065 // Each case falls through to the previous one here. 1066 if (HasMMX) { 1067 Builder.defineMacro("__MMX__"); 1068 } 1069 1070 if (CPU >= CK_i486 || CPU == CK_None) { 1071 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1072 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1073 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1074 } 1075 if (HasCX8) 1076 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1077 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) 1078 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 1079 1080 if (HasFloat128) 1081 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 1082 } 1083 1084 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 1085 return llvm::StringSwitch<bool>(Name) 1086 .Case("adx", true) 1087 .Case("aes", true) 1088 .Case("amx-avx512", true) 1089 .Case("amx-bf16", true) 1090 .Case("amx-complex", true) 1091 .Case("amx-fp16", true) 1092 .Case("amx-fp8", true) 1093 .Case("amx-int8", true) 1094 .Case("amx-movrs", true) 1095 .Case("amx-tf32", true) 1096 .Case("amx-tile", true) 1097 .Case("amx-transpose", true) 1098 .Case("avx", true) 1099 .Case("avx10.1-256", true) 1100 .Case("avx10.1-512", true) 1101 .Case("avx10.2-256", true) 1102 .Case("avx10.2-512", true) 1103 .Case("avx2", true) 1104 .Case("avx512f", true) 1105 .Case("avx512cd", true) 1106 .Case("avx512vpopcntdq", true) 1107 .Case("avx512vnni", true) 1108 .Case("avx512bf16", true) 1109 .Case("avx512fp16", true) 1110 .Case("avx512dq", true) 1111 .Case("avx512bitalg", true) 1112 .Case("avx512bw", true) 1113 .Case("avx512vl", true) 1114 .Case("avx512vbmi", true) 1115 .Case("avx512vbmi2", true) 1116 .Case("avx512ifma", true) 1117 .Case("avx512vp2intersect", true) 1118 .Case("avxifma", true) 1119 .Case("avxneconvert", true) 1120 .Case("avxvnni", true) 1121 .Case("avxvnniint16", true) 1122 .Case("avxvnniint8", true) 1123 .Case("bmi", true) 1124 .Case("bmi2", true) 1125 .Case("cldemote", true) 1126 .Case("clflushopt", true) 1127 .Case("clwb", true) 1128 .Case("clzero", true) 1129 .Case("cmpccxadd", true) 1130 .Case("crc32", true) 1131 .Case("cx16", true) 1132 .Case("enqcmd", true) 1133 .Case("evex512", true) 1134 .Case("f16c", true) 1135 .Case("fma", true) 1136 .Case("fma4", true) 1137 .Case("fsgsbase", true) 1138 .Case("fxsr", true) 1139 .Case("general-regs-only", true) 1140 .Case("gfni", true) 1141 .Case("hreset", true) 1142 .Case("invpcid", true) 1143 .Case("kl", true) 1144 .Case("widekl", true) 1145 .Case("lwp", true) 1146 .Case("lzcnt", true) 1147 .Case("mmx", true) 1148 .Case("movbe", true) 1149 .Case("movrs", true) 1150 .Case("movdiri", true) 1151 .Case("movdir64b", true) 1152 .Case("mwaitx", true) 1153 .Case("pclmul", true) 1154 .Case("pconfig", true) 1155 .Case("pku", true) 1156 .Case("popcnt", true) 1157 .Case("prefer-256-bit", true) 1158 .Case("prefetchi", true) 1159 .Case("prfchw", true) 1160 .Case("ptwrite", true) 1161 .Case("raoint", true) 1162 .Case("rdpid", true) 1163 .Case("rdpru", true) 1164 .Case("rdrnd", true) 1165 .Case("rdseed", true) 1166 .Case("rtm", true) 1167 .Case("sahf", true) 1168 .Case("serialize", true) 1169 .Case("sgx", true) 1170 .Case("sha", true) 1171 .Case("sha512", true) 1172 .Case("shstk", true) 1173 .Case("sm3", true) 1174 .Case("sm4", true) 1175 .Case("sse", true) 1176 .Case("sse2", true) 1177 .Case("sse3", true) 1178 .Case("ssse3", true) 1179 .Case("sse4", true) 1180 .Case("sse4.1", true) 1181 .Case("sse4.2", true) 1182 .Case("sse4a", true) 1183 .Case("tbm", true) 1184 .Case("tsxldtrk", true) 1185 .Case("uintr", true) 1186 .Case("usermsr", true) 1187 .Case("vaes", true) 1188 .Case("vpclmulqdq", true) 1189 .Case("wbnoinvd", true) 1190 .Case("waitpkg", true) 1191 .Case("x87", true) 1192 .Case("xop", true) 1193 .Case("xsave", true) 1194 .Case("xsavec", true) 1195 .Case("xsaves", true) 1196 .Case("xsaveopt", true) 1197 .Case("egpr", true) 1198 .Case("push2pop2", true) 1199 .Case("ppx", true) 1200 .Case("ndd", true) 1201 .Case("ccmp", true) 1202 .Case("nf", true) 1203 .Case("cf", true) 1204 .Case("zu", true) 1205 .Default(false); 1206 } 1207 1208 bool X86TargetInfo::hasFeature(StringRef Feature) const { 1209 return llvm::StringSwitch<bool>(Feature) 1210 .Case("adx", HasADX) 1211 .Case("aes", HasAES) 1212 .Case("amx-avx512", HasAMXAVX512) 1213 .Case("amx-bf16", HasAMXBF16) 1214 .Case("amx-complex", HasAMXCOMPLEX) 1215 .Case("amx-fp16", HasAMXFP16) 1216 .Case("amx-fp8", HasAMXFP8) 1217 .Case("amx-int8", HasAMXINT8) 1218 .Case("amx-movrs", HasAMXMOVRS) 1219 .Case("amx-tf32", HasAMXTF32) 1220 .Case("amx-tile", HasAMXTILE) 1221 .Case("amx-transpose", HasAMXTRANSPOSE) 1222 .Case("avx", SSELevel >= AVX) 1223 .Case("avx10.1-256", HasAVX10_1) 1224 .Case("avx10.1-512", HasAVX10_1_512) 1225 .Case("avx10.2-256", HasAVX10_2) 1226 .Case("avx10.2-512", HasAVX10_2_512) 1227 .Case("avx2", SSELevel >= AVX2) 1228 .Case("avx512f", SSELevel >= AVX512F) 1229 .Case("avx512cd", HasAVX512CD) 1230 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 1231 .Case("avx512vnni", HasAVX512VNNI) 1232 .Case("avx512bf16", HasAVX512BF16) 1233 .Case("avx512fp16", HasAVX512FP16) 1234 .Case("avx512dq", HasAVX512DQ) 1235 .Case("avx512bitalg", HasAVX512BITALG) 1236 .Case("avx512bw", HasAVX512BW) 1237 .Case("avx512vl", HasAVX512VL) 1238 .Case("avx512vbmi", HasAVX512VBMI) 1239 .Case("avx512vbmi2", HasAVX512VBMI2) 1240 .Case("avx512ifma", HasAVX512IFMA) 1241 .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) 1242 .Case("avxifma", HasAVXIFMA) 1243 .Case("avxneconvert", HasAVXNECONVERT) 1244 .Case("avxvnni", HasAVXVNNI) 1245 .Case("avxvnniint16", HasAVXVNNIINT16) 1246 .Case("avxvnniint8", HasAVXVNNIINT8) 1247 .Case("bmi", HasBMI) 1248 .Case("bmi2", HasBMI2) 1249 .Case("cldemote", HasCLDEMOTE) 1250 .Case("clflushopt", HasCLFLUSHOPT) 1251 .Case("clwb", HasCLWB) 1252 .Case("clzero", HasCLZERO) 1253 .Case("cmpccxadd", HasCMPCCXADD) 1254 .Case("crc32", HasCRC32) 1255 .Case("cx8", HasCX8) 1256 .Case("cx16", HasCX16) 1257 .Case("enqcmd", HasENQCMD) 1258 .Case("evex512", HasEVEX512) 1259 .Case("f16c", HasF16C) 1260 .Case("fma", HasFMA) 1261 .Case("fma4", XOPLevel >= FMA4) 1262 .Case("fsgsbase", HasFSGSBASE) 1263 .Case("fxsr", HasFXSR) 1264 .Case("gfni", HasGFNI) 1265 .Case("hreset", HasHRESET) 1266 .Case("invpcid", HasINVPCID) 1267 .Case("kl", HasKL) 1268 .Case("widekl", HasWIDEKL) 1269 .Case("lwp", HasLWP) 1270 .Case("lzcnt", HasLZCNT) 1271 .Case("mmx", HasMMX) 1272 .Case("movbe", HasMOVBE) 1273 .Case("movrs", HasMOVRS) 1274 .Case("movdiri", HasMOVDIRI) 1275 .Case("movdir64b", HasMOVDIR64B) 1276 .Case("mwaitx", HasMWAITX) 1277 .Case("pclmul", HasPCLMUL) 1278 .Case("pconfig", HasPCONFIG) 1279 .Case("pku", HasPKU) 1280 .Case("popcnt", HasPOPCNT) 1281 .Case("prefetchi", HasPREFETCHI) 1282 .Case("prfchw", HasPRFCHW) 1283 .Case("ptwrite", HasPTWRITE) 1284 .Case("raoint", HasRAOINT) 1285 .Case("rdpid", HasRDPID) 1286 .Case("rdpru", HasRDPRU) 1287 .Case("rdrnd", HasRDRND) 1288 .Case("rdseed", HasRDSEED) 1289 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) 1290 .Case("rtm", HasRTM) 1291 .Case("sahf", HasLAHFSAHF) 1292 .Case("serialize", HasSERIALIZE) 1293 .Case("sgx", HasSGX) 1294 .Case("sha", HasSHA) 1295 .Case("sha512", HasSHA512) 1296 .Case("shstk", HasSHSTK) 1297 .Case("sm3", HasSM3) 1298 .Case("sm4", HasSM4) 1299 .Case("sse", SSELevel >= SSE1) 1300 .Case("sse2", SSELevel >= SSE2) 1301 .Case("sse3", SSELevel >= SSE3) 1302 .Case("ssse3", SSELevel >= SSSE3) 1303 .Case("sse4.1", SSELevel >= SSE41) 1304 .Case("sse4.2", SSELevel >= SSE42) 1305 .Case("sse4a", XOPLevel >= SSE4A) 1306 .Case("tbm", HasTBM) 1307 .Case("tsxldtrk", HasTSXLDTRK) 1308 .Case("uintr", HasUINTR) 1309 .Case("usermsr", HasUSERMSR) 1310 .Case("vaes", HasVAES) 1311 .Case("vpclmulqdq", HasVPCLMULQDQ) 1312 .Case("wbnoinvd", HasWBNOINVD) 1313 .Case("waitpkg", HasWAITPKG) 1314 .Case("x86", true) 1315 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 1316 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 1317 .Case("x87", HasX87) 1318 .Case("xop", XOPLevel >= XOP) 1319 .Case("xsave", HasXSAVE) 1320 .Case("xsavec", HasXSAVEC) 1321 .Case("xsaves", HasXSAVES) 1322 .Case("xsaveopt", HasXSAVEOPT) 1323 .Case("fullbf16", HasFullBFloat16) 1324 .Case("egpr", HasEGPR) 1325 .Case("push2pop2", HasPush2Pop2) 1326 .Case("ppx", HasPPX) 1327 .Case("ndd", HasNDD) 1328 .Case("ccmp", HasCCMP) 1329 .Case("nf", HasNF) 1330 .Case("cf", HasCF) 1331 .Case("zu", HasZU) 1332 .Case("branch-hint", HasBranchHint) 1333 .Default(false); 1334 } 1335 1336 // We can't use a generic validation scheme for the features accepted here 1337 // versus subtarget features accepted in the target attribute because the 1338 // bitfield structure that's initialized in the runtime only supports the 1339 // below currently rather than the full range of subtarget features. (See 1340 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 1341 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 1342 return llvm::StringSwitch<bool>(FeatureStr) 1343 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true) 1344 #define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) .Case(STR, true) 1345 #include "llvm/TargetParser/X86TargetParser.def" 1346 .Default(false); 1347 } 1348 1349 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { 1350 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name) 1351 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 1352 .Case(STR, llvm::X86::FEATURE_##ENUM) 1353 1354 #include "llvm/TargetParser/X86TargetParser.def" 1355 ; 1356 // Note, this function should only be used after ensuring the value is 1357 // correct, so it asserts if the value is out of range. 1358 } 1359 1360 uint64_t X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { 1361 auto getPriority = [](StringRef Feature) -> uint64_t { 1362 // Valid CPUs have a 'key feature' that compares just better than its key 1363 // feature. 1364 using namespace llvm::X86; 1365 CPUKind Kind = parseArchX86(Feature); 1366 if (Kind != CK_None) { 1367 ProcessorFeatures KeyFeature = getKeyFeature(Kind); 1368 return (getFeaturePriority(KeyFeature) << 1) + 1; 1369 } 1370 // Now we know we have a feature, so get its priority and shift it a few so 1371 // that we have sufficient room for the CPUs (above). 1372 return getFeaturePriority(getFeature(Feature)) << 1; 1373 }; 1374 1375 uint64_t Priority = 0; 1376 for (StringRef Feature : Features) 1377 if (!Feature.empty()) 1378 Priority = std::max(Priority, getPriority(Feature)); 1379 return Priority; 1380 } 1381 1382 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { 1383 return llvm::X86::validateCPUSpecificCPUDispatch(Name); 1384 } 1385 1386 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { 1387 return llvm::X86::getCPUDispatchMangling(Name); 1388 } 1389 1390 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( 1391 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { 1392 SmallVector<StringRef, 32> TargetCPUFeatures; 1393 llvm::X86::getFeaturesForCPU(Name, TargetCPUFeatures, true); 1394 for (auto &F : TargetCPUFeatures) 1395 Features.push_back(F); 1396 } 1397 1398 // We can't use a generic validation scheme for the cpus accepted here 1399 // versus subtarget cpus accepted in the target attribute because the 1400 // variables intitialized by the runtime only support the below currently 1401 // rather than the full range of cpus. 1402 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { 1403 return llvm::StringSwitch<bool>(FeatureStr) 1404 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) 1405 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1406 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true) 1407 #define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true) 1408 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true) 1409 #include "llvm/TargetParser/X86TargetParser.def" 1410 .Default(false); 1411 } 1412 1413 static unsigned matchAsmCCConstraint(const char *Name) { 1414 auto RV = llvm::StringSwitch<unsigned>(Name) 1415 .Case("@cca", 4) 1416 .Case("@ccae", 5) 1417 .Case("@ccb", 4) 1418 .Case("@ccbe", 5) 1419 .Case("@ccc", 4) 1420 .Case("@cce", 4) 1421 .Case("@ccz", 4) 1422 .Case("@ccg", 4) 1423 .Case("@ccge", 5) 1424 .Case("@ccl", 4) 1425 .Case("@ccle", 5) 1426 .Case("@ccna", 5) 1427 .Case("@ccnae", 6) 1428 .Case("@ccnb", 5) 1429 .Case("@ccnbe", 6) 1430 .Case("@ccnc", 5) 1431 .Case("@ccne", 5) 1432 .Case("@ccnz", 5) 1433 .Case("@ccng", 5) 1434 .Case("@ccnge", 6) 1435 .Case("@ccnl", 5) 1436 .Case("@ccnle", 6) 1437 .Case("@ccno", 5) 1438 .Case("@ccnp", 5) 1439 .Case("@ccns", 5) 1440 .Case("@cco", 4) 1441 .Case("@ccp", 4) 1442 .Case("@ccs", 4) 1443 .Default(0); 1444 return RV; 1445 } 1446 1447 bool X86TargetInfo::validateAsmConstraint( 1448 const char *&Name, TargetInfo::ConstraintInfo &Info) const { 1449 switch (*Name) { 1450 default: 1451 return false; 1452 // Constant constraints. 1453 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 1454 // instructions. 1455 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 1456 // x86_64 instructions. 1457 case 's': 1458 Info.setRequiresImmediate(); 1459 return true; 1460 case 'I': 1461 Info.setRequiresImmediate(0, 31); 1462 return true; 1463 case 'J': 1464 Info.setRequiresImmediate(0, 63); 1465 return true; 1466 case 'K': 1467 Info.setRequiresImmediate(-128, 127); 1468 return true; 1469 case 'L': 1470 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); 1471 return true; 1472 case 'M': 1473 Info.setRequiresImmediate(0, 3); 1474 return true; 1475 case 'N': 1476 Info.setRequiresImmediate(0, 255); 1477 return true; 1478 case 'O': 1479 Info.setRequiresImmediate(0, 127); 1480 return true; 1481 case 'W': 1482 switch (*++Name) { 1483 default: 1484 return false; 1485 case 's': 1486 Info.setAllowsRegister(); 1487 return true; 1488 } 1489 // Register constraints. 1490 case 'Y': // 'Y' is the first character for several 2-character constraints. 1491 // Shift the pointer to the second character of the constraint. 1492 Name++; 1493 switch (*Name) { 1494 default: 1495 return false; 1496 case 'z': // First SSE register. 1497 case '2': 1498 case 't': // Any SSE register, when SSE2 is enabled. 1499 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 1500 case 'm': // Any MMX register, when inter-unit moves enabled. 1501 case 'k': // AVX512 arch mask registers: k1-k7. 1502 Info.setAllowsRegister(); 1503 return true; 1504 } 1505 case 'f': // Any x87 floating point stack register. 1506 // Constraint 'f' cannot be used for output operands. 1507 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+') 1508 return false; 1509 Info.setAllowsRegister(); 1510 return true; 1511 case 'a': // eax. 1512 case 'b': // ebx. 1513 case 'c': // ecx. 1514 case 'd': // edx. 1515 case 'S': // esi. 1516 case 'D': // edi. 1517 case 'A': // edx:eax. 1518 case 't': // Top of floating point stack. 1519 case 'u': // Second from top of floating point stack. 1520 case 'q': // Any register accessible as [r]l: a, b, c, and d. 1521 case 'y': // Any MMX register. 1522 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 1523 case 'x': // Any SSE register. 1524 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 1525 // for intermideate k reg operations). 1526 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 1527 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 1528 case 'l': // "Index" registers: any general register that can be used as an 1529 // index in a base+index memory access. 1530 Info.setAllowsRegister(); 1531 return true; 1532 // Floating point constant constraints. 1533 case 'C': // SSE floating point constant. 1534 case 'G': // x87 floating point constant. 1535 return true; 1536 case 'j': 1537 Name++; 1538 switch (*Name) { 1539 default: 1540 return false; 1541 case 'r': 1542 Info.setAllowsRegister(); 1543 return true; 1544 case 'R': 1545 Info.setAllowsRegister(); 1546 return true; 1547 } 1548 case '@': 1549 // CC condition changes. 1550 if (auto Len = matchAsmCCConstraint(Name)) { 1551 Name += Len - 1; 1552 Info.setAllowsRegister(); 1553 return true; 1554 } 1555 return false; 1556 } 1557 } 1558 1559 // Below is based on the following information: 1560 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1561 // | Processor Name | Cache Line Size (Bytes) | Source | 1562 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1563 // | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf | 1564 // | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) | 1565 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html | 1566 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html | 1567 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html | 1568 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html | 1569 // | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" | 1570 // | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html | 1571 // | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html | 1572 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html | 1573 // | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html | 1574 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" | 1575 // | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" | 1576 // | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" | 1577 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html | 1578 // | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" | 1579 // | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " | 1580 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ 1581 std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { 1582 using namespace llvm::X86; 1583 switch (CPU) { 1584 // i386 1585 case CK_i386: 1586 // i486 1587 case CK_i486: 1588 case CK_WinChipC6: 1589 case CK_WinChip2: 1590 case CK_C3: 1591 // Lakemont 1592 case CK_Lakemont: 1593 return 16; 1594 1595 // i586 1596 case CK_i586: 1597 case CK_Pentium: 1598 case CK_PentiumMMX: 1599 // i686 1600 case CK_PentiumPro: 1601 case CK_i686: 1602 case CK_Pentium2: 1603 case CK_Pentium3: 1604 case CK_PentiumM: 1605 case CK_C3_2: 1606 // K6 1607 case CK_K6: 1608 case CK_K6_2: 1609 case CK_K6_3: 1610 // Geode 1611 case CK_Geode: 1612 return 32; 1613 1614 // Netburst 1615 case CK_Pentium4: 1616 case CK_Prescott: 1617 case CK_Nocona: 1618 // Atom 1619 case CK_Bonnell: 1620 case CK_Silvermont: 1621 case CK_Goldmont: 1622 case CK_GoldmontPlus: 1623 case CK_Tremont: 1624 case CK_Gracemont: 1625 1626 case CK_Westmere: 1627 case CK_SandyBridge: 1628 case CK_IvyBridge: 1629 case CK_Haswell: 1630 case CK_Broadwell: 1631 case CK_SkylakeClient: 1632 case CK_SkylakeServer: 1633 case CK_Cascadelake: 1634 case CK_Nehalem: 1635 case CK_Cooperlake: 1636 case CK_Cannonlake: 1637 case CK_Tigerlake: 1638 case CK_SapphireRapids: 1639 case CK_IcelakeClient: 1640 case CK_Rocketlake: 1641 case CK_IcelakeServer: 1642 case CK_Alderlake: 1643 case CK_Raptorlake: 1644 case CK_Meteorlake: 1645 case CK_Arrowlake: 1646 case CK_ArrowlakeS: 1647 case CK_Lunarlake: 1648 case CK_Pantherlake: 1649 case CK_Sierraforest: 1650 case CK_Grandridge: 1651 case CK_Graniterapids: 1652 case CK_GraniterapidsD: 1653 case CK_Emeraldrapids: 1654 case CK_Clearwaterforest: 1655 case CK_Diamondrapids: 1656 case CK_KNL: 1657 case CK_KNM: 1658 // K7 1659 case CK_Athlon: 1660 case CK_AthlonXP: 1661 // K8 1662 case CK_K8: 1663 case CK_K8SSE3: 1664 case CK_AMDFAM10: 1665 // Bobcat 1666 case CK_BTVER1: 1667 case CK_BTVER2: 1668 // Bulldozer 1669 case CK_BDVER1: 1670 case CK_BDVER2: 1671 case CK_BDVER3: 1672 case CK_BDVER4: 1673 // Zen 1674 case CK_ZNVER1: 1675 case CK_ZNVER2: 1676 case CK_ZNVER3: 1677 case CK_ZNVER4: 1678 case CK_ZNVER5: 1679 // Deprecated 1680 case CK_x86_64: 1681 case CK_x86_64_v2: 1682 case CK_x86_64_v3: 1683 case CK_x86_64_v4: 1684 case CK_Yonah: 1685 case CK_Penryn: 1686 case CK_Core2: 1687 return 64; 1688 1689 // The following currently have unknown cache line sizes (but they are probably all 64): 1690 // Core 1691 case CK_None: 1692 return std::nullopt; 1693 } 1694 llvm_unreachable("Unknown CPU kind"); 1695 } 1696 1697 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap, 1698 StringRef Constraint, 1699 unsigned Size) const { 1700 // Strip off constraint modifiers. 1701 Constraint = Constraint.ltrim("=+&"); 1702 1703 return validateOperandSize(FeatureMap, Constraint, Size); 1704 } 1705 1706 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap, 1707 StringRef Constraint, 1708 unsigned Size) const { 1709 return validateOperandSize(FeatureMap, Constraint, Size); 1710 } 1711 1712 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap, 1713 StringRef Constraint, 1714 unsigned Size) const { 1715 switch (Constraint[0]) { 1716 default: 1717 break; 1718 case 'k': 1719 // Registers k0-k7 (AVX512) size limit is 64 bit. 1720 case 'y': 1721 return Size <= 64; 1722 case 'f': 1723 case 't': 1724 case 'u': 1725 return Size <= 128; 1726 case 'Y': 1727 // 'Y' is the first character for several 2-character constraints. 1728 switch (Constraint[1]) { 1729 default: 1730 return false; 1731 case 'm': 1732 // 'Ym' is synonymous with 'y'. 1733 case 'k': 1734 return Size <= 64; 1735 case 'z': 1736 // XMM0/YMM/ZMM0 1737 if (hasFeatureEnabled(FeatureMap, "avx512f") && 1738 hasFeatureEnabled(FeatureMap, "evex512")) 1739 // ZMM0 can be used if target supports AVX512F and EVEX512 is set. 1740 return Size <= 512U; 1741 else if (hasFeatureEnabled(FeatureMap, "avx")) 1742 // YMM0 can be used if target supports AVX. 1743 return Size <= 256U; 1744 else if (hasFeatureEnabled(FeatureMap, "sse")) 1745 return Size <= 128U; 1746 return false; 1747 case 'i': 1748 case 't': 1749 case '2': 1750 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. 1751 if (SSELevel < SSE2) 1752 return false; 1753 break; 1754 } 1755 break; 1756 case 'v': 1757 case 'x': 1758 if (hasFeatureEnabled(FeatureMap, "avx512f") && 1759 hasFeatureEnabled(FeatureMap, "evex512")) 1760 // 512-bit zmm registers can be used if target supports AVX512F and 1761 // EVEX512 is set. 1762 return Size <= 512U; 1763 else if (hasFeatureEnabled(FeatureMap, "avx")) 1764 // 256-bit ymm registers can be used if target supports AVX. 1765 return Size <= 256U; 1766 return Size <= 128U; 1767 1768 } 1769 1770 return true; 1771 } 1772 1773 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { 1774 switch (*Constraint) { 1775 case '@': 1776 if (auto Len = matchAsmCCConstraint(Constraint)) { 1777 std::string Converted = "{" + std::string(Constraint, Len) + "}"; 1778 Constraint += Len - 1; 1779 return Converted; 1780 } 1781 return std::string(1, *Constraint); 1782 case 'a': 1783 return std::string("{ax}"); 1784 case 'b': 1785 return std::string("{bx}"); 1786 case 'c': 1787 return std::string("{cx}"); 1788 case 'd': 1789 return std::string("{dx}"); 1790 case 'S': 1791 return std::string("{si}"); 1792 case 'D': 1793 return std::string("{di}"); 1794 case 'p': // Keep 'p' constraint (address). 1795 return std::string("p"); 1796 case 't': // top of floating point stack. 1797 return std::string("{st}"); 1798 case 'u': // second from top of floating point stack. 1799 return std::string("{st(1)}"); // second from top of floating point stack. 1800 case 'W': 1801 assert(Constraint[1] == 's'); 1802 return '^' + std::string(Constraint++, 2); 1803 case 'Y': 1804 switch (Constraint[1]) { 1805 default: 1806 // Break from inner switch and fall through (copy single char), 1807 // continue parsing after copying the current constraint into 1808 // the return string. 1809 break; 1810 case 'k': 1811 case 'm': 1812 case 'i': 1813 case 't': 1814 case 'z': 1815 case '2': 1816 // "^" hints llvm that this is a 2 letter constraint. 1817 // "Constraint++" is used to promote the string iterator 1818 // to the next constraint. 1819 return std::string("^") + std::string(Constraint++, 2); 1820 } 1821 [[fallthrough]]; 1822 case 'j': 1823 switch (Constraint[1]) { 1824 default: 1825 // Break from inner switch and fall through (copy single char), 1826 // continue parsing after copying the current constraint into 1827 // the return string. 1828 break; 1829 case 'r': 1830 case 'R': 1831 // "^" hints llvm that this is a 2 letter constraint. 1832 // "Constraint++" is used to promote the string iterator 1833 // to the next constraint. 1834 return std::string("^") + std::string(Constraint++, 2); 1835 } 1836 [[fallthrough]]; 1837 default: 1838 return std::string(1, *Constraint); 1839 } 1840 } 1841 1842 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 1843 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86; 1844 llvm::X86::fillValidCPUArchList(Values, Only64Bit); 1845 } 1846 1847 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const { 1848 llvm::X86::fillValidTuneCPUList(Values); 1849 } 1850 1851 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const { 1852 return llvm::ArrayRef(GCCRegNames); 1853 } 1854 1855 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const { 1856 return llvm::ArrayRef(AddlRegNames); 1857 } 1858 1859 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const { 1860 return llvm::ArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 1861 Builtin::FirstTSBuiltin + 1); 1862 } 1863 1864 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const { 1865 return llvm::ArrayRef(BuiltinInfoX86, 1866 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 1867 } 1868