1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/TargetParser/Triple.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefinePwr11 = 1 << 15, 48 ArchDefineFuture = 1 << 16, 49 ArchDefineA2 = 1 << 17, 50 ArchDefineE500 = 1 << 18 51 } ArchDefineTypes; 52 53 ArchDefineTypes ArchDefs = ArchDefineNone; 54 static const char *const GCCRegNames[]; 55 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 56 std::string CPU; 57 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 58 59 // Target cpu features. 60 bool HasAltivec = false; 61 bool HasMMA = false; 62 bool HasROPProtect = false; 63 bool HasPrivileged = false; 64 bool HasAIXSmallLocalExecTLS = false; 65 bool HasAIXSmallLocalDynamicTLS = false; 66 bool HasVSX = false; 67 bool UseCRBits = false; 68 bool HasP8Vector = false; 69 bool HasP8Crypto = false; 70 bool HasDirectMove = false; 71 bool HasHTM = false; 72 bool HasBPERMD = false; 73 bool HasExtDiv = false; 74 bool HasP9Vector = false; 75 bool HasSPE = false; 76 bool HasFrsqrte = false; 77 bool HasFrsqrtes = false; 78 bool PairedVectorMemops = false; 79 bool HasP10Vector = false; 80 bool HasPCRelativeMemops = false; 81 bool HasPrefixInstrs = false; 82 bool IsISA2_06 = false; 83 bool IsISA2_07 = false; 84 bool IsISA3_0 = false; 85 bool IsISA3_1 = false; 86 bool HasQuadwordAtomics = false; 87 bool HasAIXShLibTLSModelOpt = false; 88 bool UseLongCalls = false; 89 90 protected: 91 std::string ABI; 92 93 public: 94 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 95 : TargetInfo(Triple) { 96 SuitableAlign = 128; 97 LongDoubleWidth = LongDoubleAlign = 128; 98 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 99 HasStrictFP = true; 100 HasIbm128 = true; 101 HasUnalignedAccess = true; 102 } 103 104 // Set the language option for altivec based on our value. 105 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override; 106 107 // Note: GCC recognizes the following additional cpus: 108 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 109 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 110 bool isValidCPUName(StringRef Name) const override; 111 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 112 113 bool setCPU(const std::string &Name) override { 114 bool CPUKnown = isValidCPUName(Name); 115 if (CPUKnown) { 116 CPU = Name; 117 118 // CPU identification. 119 ArchDefs = 120 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 121 .Case("440", ArchDefineName) 122 .Case("450", ArchDefineName | ArchDefine440) 123 .Case("601", ArchDefineName) 124 .Case("602", ArchDefineName | ArchDefinePpcgr) 125 .Case("603", ArchDefineName | ArchDefinePpcgr) 126 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 127 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 128 .Case("604", ArchDefineName | ArchDefinePpcgr) 129 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 130 .Case("620", ArchDefineName | ArchDefinePpcgr) 131 .Case("630", ArchDefineName | ArchDefinePpcgr) 132 .Case("7400", ArchDefineName | ArchDefinePpcgr) 133 .Case("7450", ArchDefineName | ArchDefinePpcgr) 134 .Case("750", ArchDefineName | ArchDefinePpcgr) 135 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 136 ArchDefinePpcsq) 137 .Case("a2", ArchDefineA2) 138 .Cases("power3", "pwr3", ArchDefinePpcgr) 139 .Cases("power4", "pwr4", 140 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 141 .Cases("power5", "pwr5", 142 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 143 ArchDefinePpcsq) 144 .Cases("power5x", "pwr5x", 145 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 146 ArchDefinePpcgr | ArchDefinePpcsq) 147 .Cases("power6", "pwr6", 148 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 149 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 150 .Cases("power6x", "pwr6x", 151 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 152 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 153 ArchDefinePpcsq) 154 .Cases("power7", "pwr7", 155 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 156 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 157 ArchDefinePpcsq) 158 // powerpc64le automatically defaults to at least power8. 159 .Cases("power8", "pwr8", "ppc64le", 160 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 161 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 162 ArchDefinePpcgr | ArchDefinePpcsq) 163 .Cases("power9", "pwr9", 164 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 165 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 166 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 167 .Cases("power10", "pwr10", 168 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 169 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 170 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 171 ArchDefinePpcsq) 172 .Cases("power11", "pwr11", 173 ArchDefinePwr11 | ArchDefinePwr10 | ArchDefinePwr9 | 174 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 175 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 176 ArchDefinePpcgr | ArchDefinePpcsq) 177 .Case("future", 178 ArchDefineFuture | ArchDefinePwr11 | ArchDefinePwr10 | 179 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 180 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 181 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 182 .Cases("8548", "e500", ArchDefineE500) 183 .Default(ArchDefineNone); 184 } 185 return CPUKnown; 186 } 187 188 StringRef getABI() const override { return ABI; } 189 190 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 191 192 bool isCLZForZeroUndef() const override { return false; } 193 194 void getTargetDefines(const LangOptions &Opts, 195 MacroBuilder &Builder) const override; 196 197 bool 198 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 199 StringRef CPU, 200 const std::vector<std::string> &FeaturesVec) const override; 201 202 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; 203 void addP11SpecificFeatures(llvm::StringMap<bool> &Features) const; 204 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 205 206 bool handleTargetFeatures(std::vector<std::string> &Features, 207 DiagnosticsEngine &Diags) override; 208 209 bool hasFeature(StringRef Feature) const override; 210 211 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 212 bool Enabled) const override; 213 214 bool supportsTargetAttributeTune() const override { return true; } 215 216 ArrayRef<const char *> getGCCRegNames() const override; 217 218 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 219 220 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 221 222 bool validateAsmConstraint(const char *&Name, 223 TargetInfo::ConstraintInfo &Info) const override { 224 switch (*Name) { 225 default: 226 return false; 227 case 'O': // Zero 228 break; 229 case 'f': // Floating point register 230 // Don't use floating point registers on soft float ABI. 231 if (FloatABI == SoftFloat) 232 return false; 233 [[fallthrough]]; 234 case 'b': // Base register 235 Info.setAllowsRegister(); 236 break; 237 // FIXME: The following are added to allow parsing. 238 // I just took a guess at what the actions should be. 239 // Also, is more specific checking needed? I.e. specific registers? 240 case 'd': // Floating point register (containing 64-bit value) 241 case 'v': // Altivec vector register 242 // Don't use floating point and altivec vector registers 243 // on soft float ABI 244 if (FloatABI == SoftFloat) 245 return false; 246 Info.setAllowsRegister(); 247 break; 248 case 'w': 249 switch (Name[1]) { 250 case 'd': // VSX vector register to hold vector double data 251 case 'f': // VSX vector register to hold vector float data 252 case 's': // VSX vector register to hold scalar double data 253 case 'w': // VSX vector register to hold scalar double data 254 case 'a': // Any VSX register 255 case 'c': // An individual CR bit 256 case 'i': // FP or VSX register to hold 64-bit integers data 257 break; 258 default: 259 return false; 260 } 261 Info.setAllowsRegister(); 262 Name++; // Skip over 'w'. 263 break; 264 case 'h': // `MQ', `CTR', or `LINK' register 265 case 'q': // `MQ' register 266 case 'c': // `CTR' register 267 case 'l': // `LINK' register 268 case 'x': // `CR' register (condition register) number 0 269 case 'y': // `CR' register (condition register) 270 case 'z': // `XER[CA]' carry bit (part of the XER register) 271 Info.setAllowsRegister(); 272 break; 273 case 'I': // Signed 16-bit constant 274 case 'J': // Unsigned 16-bit constant shifted left 16 bits 275 // (use `L' instead for SImode constants) 276 case 'K': // Unsigned 16-bit constant 277 case 'L': // Signed 16-bit constant shifted left 16 bits 278 case 'M': // Constant larger than 31 279 case 'N': // Exact power of 2 280 case 'P': // Constant whose negation is a signed 16-bit constant 281 case 'G': // Floating point constant that can be loaded into a 282 // register with one instruction per word 283 case 'H': // Integer/Floating point constant that can be loaded 284 // into a register using three instructions 285 break; 286 case 'm': // Memory operand. Note that on PowerPC targets, m can 287 // include addresses that update the base register. It 288 // is therefore only safe to use `m' in an asm statement 289 // if that asm statement accesses the operand exactly once. 290 // The asm statement must also use `%U<opno>' as a 291 // placeholder for the "update" flag in the corresponding 292 // load or store instruction. For example: 293 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 294 // is correct but: 295 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 296 // is not. Use es rather than m if you don't want the base 297 // register to be updated. 298 case 'e': 299 if (Name[1] != 's') 300 return false; 301 // es: A "stable" memory operand; that is, one which does not 302 // include any automodification of the base register. Unlike 303 // `m', this constraint can be used in asm statements that 304 // might access the operand several times, or that might not 305 // access it at all. 306 Info.setAllowsMemory(); 307 Name++; // Skip over 'e'. 308 break; 309 case 'Q': // Memory operand that is an offset from a register (it is 310 // usually better to use `m' or `es' in asm statements) 311 Info.setAllowsRegister(); 312 [[fallthrough]]; 313 case 'Z': // Memory operand that is an indexed or indirect from a 314 // register (it is usually better to use `m' or `es' in 315 // asm statements) 316 Info.setAllowsMemory(); 317 break; 318 case 'a': // Address operand that is an indexed or indirect from a 319 // register (`p' is preferable for asm statements) 320 // TODO: Add full support for this constraint 321 return false; 322 case 'R': // AIX TOC entry 323 case 'S': // Constant suitable as a 64-bit mask operand 324 case 'T': // Constant suitable as a 32-bit mask operand 325 case 'U': // System V Release 4 small data area reference 326 case 't': // AND masks that can be performed by two rldic{l, r} 327 // instructions 328 case 'W': // Vector constant that does not require memory 329 case 'j': // Vector constant that is all zeros. 330 break; 331 // End FIXME. 332 } 333 return true; 334 } 335 336 std::string convertConstraint(const char *&Constraint) const override { 337 std::string R; 338 switch (*Constraint) { 339 case 'e': 340 case 'w': 341 // Two-character constraint; add "^" hint for later parsing. 342 R = std::string("^") + std::string(Constraint, 2); 343 Constraint++; 344 break; 345 default: 346 return TargetInfo::convertConstraint(Constraint); 347 } 348 return R; 349 } 350 351 std::string_view getClobbers() const override { return ""; } 352 int getEHDataRegisterNumber(unsigned RegNo) const override { 353 if (RegNo == 0) 354 return 3; 355 if (RegNo == 1) 356 return 4; 357 return -1; 358 } 359 360 bool hasSjLjLowering() const override { return true; } 361 362 const char *getLongDoubleMangling() const override { 363 if (LongDoubleWidth == 64) 364 return "e"; 365 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 366 ? "g" 367 : "u9__ieee128"; 368 } 369 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 370 const char *getIbm128Mangling() const override { return "g"; } 371 372 bool hasBitIntType() const override { return true; } 373 374 bool isSPRegName(StringRef RegName) const override { 375 return RegName == "r1" || RegName == "x1"; 376 } 377 378 // We support __builtin_cpu_supports/__builtin_cpu_is on targets that 379 // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv. 380 static constexpr int MINIMUM_AIX_OS_MAJOR = 7; 381 static constexpr int MINIMUM_AIX_OS_MINOR = 2; 382 bool supportsCpuSupports() const override { 383 llvm::Triple Triple = getTriple(); 384 // AIX 7.2 is the minimum requirement to support __builtin_cpu_supports(). 385 return Triple.isOSGlibc() || 386 (Triple.isOSAIX() && 387 !Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR)); 388 } 389 390 bool supportsCpuIs() const override { 391 llvm::Triple Triple = getTriple(); 392 // AIX 7.2 is the minimum requirement to support __builtin_cpu_is(). 393 return Triple.isOSGlibc() || 394 (Triple.isOSAIX() && 395 !Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR)); 396 } 397 bool validateCpuSupports(StringRef Feature) const override; 398 bool validateCpuIs(StringRef Name) const override; 399 }; 400 401 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 402 public: 403 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 404 : PPCTargetInfo(Triple, Opts) { 405 if (Triple.isOSAIX()) 406 resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32"); 407 else if (Triple.getArch() == llvm::Triple::ppcle) 408 resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32"); 409 else 410 resetDataLayout("E-m:e-p:32:32-Fn32-i64:64-n32"); 411 412 switch (getTriple().getOS()) { 413 case llvm::Triple::Linux: 414 case llvm::Triple::FreeBSD: 415 case llvm::Triple::NetBSD: 416 SizeType = UnsignedInt; 417 PtrDiffType = SignedInt; 418 IntPtrType = SignedInt; 419 break; 420 case llvm::Triple::AIX: 421 SizeType = UnsignedLong; 422 PtrDiffType = SignedLong; 423 IntPtrType = SignedLong; 424 LongDoubleWidth = 64; 425 LongDoubleAlign = DoubleAlign = 32; 426 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 427 break; 428 default: 429 break; 430 } 431 432 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 433 Triple.isMusl()) { 434 LongDoubleWidth = LongDoubleAlign = 64; 435 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 436 } 437 438 // PPC32 supports atomics up to 4 bytes. 439 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 440 } 441 442 BuiltinVaListKind getBuiltinVaListKind() const override { 443 // This is the ELF definition 444 return TargetInfo::PowerABIBuiltinVaList; 445 } 446 447 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { 448 return std::make_pair(32, 32); 449 } 450 }; 451 452 // Note: ABI differences may eventually require us to have a separate 453 // TargetInfo for little endian. 454 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 455 public: 456 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 457 : PPCTargetInfo(Triple, Opts) { 458 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 459 IntMaxType = SignedLong; 460 Int64Type = SignedLong; 461 std::string DataLayout; 462 463 if (Triple.isOSAIX()) { 464 // TODO: Set appropriate ABI for AIX platform. 465 DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64"; 466 LongDoubleWidth = 64; 467 LongDoubleAlign = DoubleAlign = 32; 468 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 469 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { 470 DataLayout = "e-m:e-Fn32-i64:64-i128:128-n32:64"; 471 ABI = "elfv2"; 472 } else { 473 DataLayout = "E-m:e"; 474 if (Triple.isPPC64ELFv2ABI()) { 475 ABI = "elfv2"; 476 DataLayout += "-Fn32"; 477 } else { 478 ABI = "elfv1"; 479 DataLayout += "-Fi64"; 480 } 481 DataLayout += "-i64:64-i128:128-n32:64"; 482 } 483 484 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { 485 LongDoubleWidth = LongDoubleAlign = 64; 486 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 487 } 488 489 if (Triple.isOSAIX() || Triple.isOSLinux()) 490 DataLayout += "-S128-v256:256:256-v512:512:512"; 491 resetDataLayout(DataLayout); 492 493 // Newer PPC64 instruction sets support atomics up to 16 bytes. 494 MaxAtomicPromoteWidth = 128; 495 // Baseline PPC64 supports inlining atomics up to 8 bytes. 496 MaxAtomicInlineWidth = 64; 497 } 498 499 void setMaxAtomicWidth() override { 500 // For power8 and up, backend is able to inline 16-byte atomic lock free 501 // code. 502 // TODO: We should allow AIX to inline quadword atomics in the future. 503 if (!getTriple().isOSAIX() && hasFeature("quadword-atomics")) 504 MaxAtomicInlineWidth = 128; 505 } 506 507 BuiltinVaListKind getBuiltinVaListKind() const override { 508 return TargetInfo::CharPtrBuiltinVaList; 509 } 510 511 // PPC64 Linux-specific ABI options. 512 bool setABI(const std::string &Name) override { 513 if (Name == "elfv1" || Name == "elfv2") { 514 ABI = Name; 515 return true; 516 } 517 return false; 518 } 519 520 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 521 switch (CC) { 522 case CC_Swift: 523 return CCCR_OK; 524 case CC_SwiftAsync: 525 return CCCR_Error; 526 default: 527 return CCCR_Warning; 528 } 529 } 530 531 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { 532 return std::make_pair(128, 128); 533 } 534 }; 535 536 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 537 public AIXTargetInfo<PPC32TargetInfo> { 538 public: 539 using AIXTargetInfo::AIXTargetInfo; 540 BuiltinVaListKind getBuiltinVaListKind() const override { 541 return TargetInfo::CharPtrBuiltinVaList; 542 } 543 }; 544 545 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 546 public AIXTargetInfo<PPC64TargetInfo> { 547 public: 548 using AIXTargetInfo::AIXTargetInfo; 549 }; 550 551 } // namespace targets 552 } // namespace clang 553 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 554