1 //===--- PPC.cpp - Implement PPC target feature support -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "PPC.h" 14 #include "clang/Basic/Diagnostic.h" 15 #include "clang/Basic/MacroBuilder.h" 16 #include "clang/Basic/TargetBuiltins.h" 17 #include "llvm/TargetParser/PPCTargetParser.h" 18 19 using namespace clang; 20 using namespace clang::targets; 21 22 static constexpr Builtin::Info BuiltinInfo[] = { 23 #define BUILTIN(ID, TYPE, ATTRS) \ 24 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 25 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 26 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, 27 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 28 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::HEADER, ALL_LANGUAGES}, 29 #include "clang/Basic/BuiltinsPPC.def" 30 }; 31 32 /// handleTargetFeatures - Perform initialization based on the user 33 /// configured set of features. 34 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 35 DiagnosticsEngine &Diags) { 36 FloatABI = HardFloat; 37 for (const auto &Feature : Features) { 38 if (Feature == "+altivec") { 39 HasAltivec = true; 40 } else if (Feature == "+vsx") { 41 HasVSX = true; 42 } else if (Feature == "+crbits") { 43 UseCRBits = true; 44 } else if (Feature == "+bpermd") { 45 HasBPERMD = true; 46 } else if (Feature == "+extdiv") { 47 HasExtDiv = true; 48 } else if (Feature == "+power8-vector") { 49 HasP8Vector = true; 50 } else if (Feature == "+crypto") { 51 HasP8Crypto = true; 52 } else if (Feature == "+direct-move") { 53 HasDirectMove = true; 54 } else if (Feature == "+htm") { 55 HasHTM = true; 56 } else if (Feature == "+float128") { 57 HasFloat128 = !getTriple().isOSAIX(); 58 } else if (Feature == "+power9-vector") { 59 HasP9Vector = true; 60 } else if (Feature == "+power10-vector") { 61 HasP10Vector = true; 62 } else if (Feature == "+pcrelative-memops") { 63 HasPCRelativeMemops = true; 64 } else if (Feature == "+prefix-instrs") { 65 HasPrefixInstrs = true; 66 } else if (Feature == "+spe" || Feature == "+efpu2") { 67 HasStrictFP = false; 68 HasSPE = true; 69 LongDoubleWidth = LongDoubleAlign = 64; 70 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 71 } else if (Feature == "+frsqrte") { 72 HasFrsqrte = true; 73 } else if (Feature == "+frsqrtes") { 74 HasFrsqrtes = true; 75 } else if (Feature == "-hard-float") { 76 FloatABI = SoftFloat; 77 } else if (Feature == "+paired-vector-memops") { 78 PairedVectorMemops = true; 79 } else if (Feature == "+mma") { 80 HasMMA = true; 81 } else if (Feature == "+rop-protect") { 82 HasROPProtect = true; 83 } else if (Feature == "+privileged") { 84 HasPrivileged = true; 85 } else if (Feature == "+aix-small-local-exec-tls") { 86 HasAIXSmallLocalExecTLS = true; 87 } else if (Feature == "+aix-small-local-dynamic-tls") { 88 HasAIXSmallLocalDynamicTLS = true; 89 } else if (Feature == "+isa-v206-instructions") { 90 IsISA2_06 = true; 91 } else if (Feature == "+isa-v207-instructions") { 92 IsISA2_07 = true; 93 } else if (Feature == "+isa-v30-instructions") { 94 IsISA3_0 = true; 95 } else if (Feature == "+isa-v31-instructions") { 96 IsISA3_1 = true; 97 } else if (Feature == "+quadword-atomics") { 98 HasQuadwordAtomics = true; 99 } else if (Feature == "+aix-shared-lib-tls-model-opt") { 100 HasAIXShLibTLSModelOpt = true; 101 } else if (Feature == "+longcall") { 102 UseLongCalls = true; 103 } 104 // TODO: Finish this list and add an assert that we've handled them 105 // all. 106 } 107 108 return true; 109 } 110 111 static void defineXLCompatMacros(MacroBuilder &Builder) { 112 Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd"); 113 Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd"); 114 Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s"); 115 Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb"); 116 Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4"); 117 Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8"); 118 Builder.defineMacro("__eieio", "__builtin_ppc_eieio"); 119 Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio"); 120 Builder.defineMacro("__isync", "__builtin_ppc_isync"); 121 Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync"); 122 Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync"); 123 Builder.defineMacro("__sync", "__builtin_ppc_sync"); 124 Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync"); 125 Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl"); 126 Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp"); 127 Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst"); 128 Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt"); 129 Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst"); 130 Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz"); 131 Builder.defineMacro("__icbt", "__builtin_ppc_icbt"); 132 Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap"); 133 Builder.defineMacro("__compare_and_swaplp", 134 "__builtin_ppc_compare_and_swaplp"); 135 Builder.defineMacro("__fetch_and_add", "__builtin_ppc_fetch_and_add"); 136 Builder.defineMacro("__fetch_and_addlp", "__builtin_ppc_fetch_and_addlp"); 137 Builder.defineMacro("__fetch_and_and", "__builtin_ppc_fetch_and_and"); 138 Builder.defineMacro("__fetch_and_andlp", "__builtin_ppc_fetch_and_andlp"); 139 Builder.defineMacro("__fetch_and_or", "__builtin_ppc_fetch_and_or"); 140 Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp"); 141 Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap"); 142 Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp"); 143 Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx"); 144 Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx"); 145 Builder.defineMacro("__lharx", "__builtin_ppc_lharx"); 146 Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx"); 147 Builder.defineMacro("__stfiw", "__builtin_ppc_stfiw"); 148 Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx"); 149 Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx"); 150 Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx"); 151 Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx"); 152 Builder.defineMacro("__tdw", "__builtin_ppc_tdw"); 153 Builder.defineMacro("__tw", "__builtin_ppc_tw"); 154 Builder.defineMacro("__trap", "__builtin_ppc_trap"); 155 Builder.defineMacro("__trapd", "__builtin_ppc_trapd"); 156 Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid"); 157 Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud"); 158 Builder.defineMacro("__fctid", "__builtin_ppc_fctid"); 159 Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz"); 160 Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw"); 161 Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz"); 162 Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz"); 163 Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz"); 164 Builder.defineMacro("__cmpeqb", "__builtin_ppc_cmpeqb"); 165 Builder.defineMacro("__cmprb", "__builtin_ppc_cmprb"); 166 Builder.defineMacro("__setb", "__builtin_ppc_setb"); 167 Builder.defineMacro("__cmpb", "__builtin_ppc_cmpb"); 168 Builder.defineMacro("__mulhd", "__builtin_ppc_mulhd"); 169 Builder.defineMacro("__mulhdu", "__builtin_ppc_mulhdu"); 170 Builder.defineMacro("__mulhw", "__builtin_ppc_mulhw"); 171 Builder.defineMacro("__mulhwu", "__builtin_ppc_mulhwu"); 172 Builder.defineMacro("__maddhd", "__builtin_ppc_maddhd"); 173 Builder.defineMacro("__maddhdu", "__builtin_ppc_maddhdu"); 174 Builder.defineMacro("__maddld", "__builtin_ppc_maddld"); 175 Builder.defineMacro("__rlwnm", "__builtin_ppc_rlwnm"); 176 Builder.defineMacro("__rlwimi", "__builtin_ppc_rlwimi"); 177 Builder.defineMacro("__rldimi", "__builtin_ppc_rldimi"); 178 Builder.defineMacro("__load2r", "__builtin_ppc_load2r"); 179 Builder.defineMacro("__load4r", "__builtin_ppc_load4r"); 180 Builder.defineMacro("__load8r", "__builtin_ppc_load8r"); 181 Builder.defineMacro("__store2r", "__builtin_ppc_store2r"); 182 Builder.defineMacro("__store4r", "__builtin_ppc_store4r"); 183 Builder.defineMacro("__store8r", "__builtin_ppc_store8r"); 184 Builder.defineMacro("__extract_exp", "__builtin_ppc_extract_exp"); 185 Builder.defineMacro("__extract_sig", "__builtin_ppc_extract_sig"); 186 Builder.defineMacro("__mtfsb0", "__builtin_ppc_mtfsb0"); 187 Builder.defineMacro("__mtfsb1", "__builtin_ppc_mtfsb1"); 188 Builder.defineMacro("__mtfsf", "__builtin_ppc_mtfsf"); 189 Builder.defineMacro("__mtfsfi", "__builtin_ppc_mtfsfi"); 190 Builder.defineMacro("__insert_exp", "__builtin_ppc_insert_exp"); 191 Builder.defineMacro("__fmsub", "__builtin_ppc_fmsub"); 192 Builder.defineMacro("__fmsubs", "__builtin_ppc_fmsubs"); 193 Builder.defineMacro("__fnmadd", "__builtin_ppc_fnmadd"); 194 Builder.defineMacro("__fnmadds", "__builtin_ppc_fnmadds"); 195 Builder.defineMacro("__fnmsub", "__builtin_ppc_fnmsub"); 196 Builder.defineMacro("__fnmsubs", "__builtin_ppc_fnmsubs"); 197 Builder.defineMacro("__fre", "__builtin_ppc_fre"); 198 Builder.defineMacro("__fres", "__builtin_ppc_fres"); 199 Builder.defineMacro("__swdiv_nochk", "__builtin_ppc_swdiv_nochk"); 200 Builder.defineMacro("__swdivs_nochk", "__builtin_ppc_swdivs_nochk"); 201 Builder.defineMacro("__alloca", "__builtin_alloca"); 202 Builder.defineMacro("__vcipher", "__builtin_altivec_crypto_vcipher"); 203 Builder.defineMacro("__vcipherlast", "__builtin_altivec_crypto_vcipherlast"); 204 Builder.defineMacro("__vncipher", "__builtin_altivec_crypto_vncipher"); 205 Builder.defineMacro("__vncipherlast", 206 "__builtin_altivec_crypto_vncipherlast"); 207 Builder.defineMacro("__vpermxor", "__builtin_altivec_crypto_vpermxor"); 208 Builder.defineMacro("__vpmsumb", "__builtin_altivec_crypto_vpmsumb"); 209 Builder.defineMacro("__vpmsumd", "__builtin_altivec_crypto_vpmsumd"); 210 Builder.defineMacro("__vpmsumh", "__builtin_altivec_crypto_vpmsumh"); 211 Builder.defineMacro("__vpmsumw", "__builtin_altivec_crypto_vpmsumw"); 212 Builder.defineMacro("__divde", "__builtin_divde"); 213 Builder.defineMacro("__divwe", "__builtin_divwe"); 214 Builder.defineMacro("__divdeu", "__builtin_divdeu"); 215 Builder.defineMacro("__divweu", "__builtin_divweu"); 216 Builder.defineMacro("__alignx", "__builtin_ppc_alignx"); 217 Builder.defineMacro("__bcopy", "bcopy"); 218 Builder.defineMacro("__bpermd", "__builtin_bpermd"); 219 Builder.defineMacro("__cntlz4", "__builtin_clz"); 220 Builder.defineMacro("__cntlz8", "__builtin_clzll"); 221 Builder.defineMacro("__cmplx", "__builtin_complex"); 222 Builder.defineMacro("__cmplxf", "__builtin_complex"); 223 Builder.defineMacro("__cnttz4", "__builtin_ctz"); 224 Builder.defineMacro("__cnttz8", "__builtin_ctzll"); 225 Builder.defineMacro("__darn", "__builtin_darn"); 226 Builder.defineMacro("__darn_32", "__builtin_darn_32"); 227 Builder.defineMacro("__darn_raw", "__builtin_darn_raw"); 228 Builder.defineMacro("__dcbf", "__builtin_dcbf"); 229 Builder.defineMacro("__fence", "__builtin_ppc_fence"); 230 Builder.defineMacro("__fmadd", "__builtin_fma"); 231 Builder.defineMacro("__fmadds", "__builtin_fmaf"); 232 Builder.defineMacro("__abs", "__builtin_abs"); 233 Builder.defineMacro("__labs", "__builtin_labs"); 234 Builder.defineMacro("__llabs", "__builtin_llabs"); 235 Builder.defineMacro("__popcnt4", "__builtin_popcount"); 236 Builder.defineMacro("__popcnt8", "__builtin_popcountll"); 237 Builder.defineMacro("__readflm", "__builtin_readflm"); 238 Builder.defineMacro("__rotatel4", "__builtin_rotateleft32"); 239 Builder.defineMacro("__rotatel8", "__builtin_rotateleft64"); 240 Builder.defineMacro("__rdlam", "__builtin_ppc_rdlam"); 241 Builder.defineMacro("__setflm", "__builtin_setflm"); 242 Builder.defineMacro("__setrnd", "__builtin_setrnd"); 243 Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt"); 244 Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt"); 245 Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu"); 246 Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr"); 247 Builder.defineMacro("__mtmsr", "__builtin_ppc_mtmsr"); 248 Builder.defineMacro("__mfspr", "__builtin_ppc_mfspr"); 249 Builder.defineMacro("__mtspr", "__builtin_ppc_mtspr"); 250 Builder.defineMacro("__fric", "__builtin_ppc_fric"); 251 Builder.defineMacro("__frim", "__builtin_ppc_frim"); 252 Builder.defineMacro("__frims", "__builtin_ppc_frims"); 253 Builder.defineMacro("__frin", "__builtin_ppc_frin"); 254 Builder.defineMacro("__frins", "__builtin_ppc_frins"); 255 Builder.defineMacro("__frip", "__builtin_ppc_frip"); 256 Builder.defineMacro("__frips", "__builtin_ppc_frips"); 257 Builder.defineMacro("__friz", "__builtin_ppc_friz"); 258 Builder.defineMacro("__frizs", "__builtin_ppc_frizs"); 259 Builder.defineMacro("__fsel", "__builtin_ppc_fsel"); 260 Builder.defineMacro("__fsels", "__builtin_ppc_fsels"); 261 Builder.defineMacro("__frsqrte", "__builtin_ppc_frsqrte"); 262 Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes"); 263 Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt"); 264 Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts"); 265 Builder.defineMacro("__addex", "__builtin_ppc_addex"); 266 Builder.defineMacro("__cmplxl", "__builtin_complex"); 267 Builder.defineMacro("__compare_exp_uo", "__builtin_ppc_compare_exp_uo"); 268 Builder.defineMacro("__compare_exp_lt", "__builtin_ppc_compare_exp_lt"); 269 Builder.defineMacro("__compare_exp_gt", "__builtin_ppc_compare_exp_gt"); 270 Builder.defineMacro("__compare_exp_eq", "__builtin_ppc_compare_exp_eq"); 271 Builder.defineMacro("__test_data_class", "__builtin_ppc_test_data_class"); 272 Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv"); 273 Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs"); 274 Builder.defineMacro("__fnabs", "__builtin_ppc_fnabs"); 275 Builder.defineMacro("__fnabss", "__builtin_ppc_fnabss"); 276 Builder.defineMacro("__builtin_maxfe", "__builtin_ppc_maxfe"); 277 Builder.defineMacro("__builtin_maxfl", "__builtin_ppc_maxfl"); 278 Builder.defineMacro("__builtin_maxfs", "__builtin_ppc_maxfs"); 279 Builder.defineMacro("__builtin_minfe", "__builtin_ppc_minfe"); 280 Builder.defineMacro("__builtin_minfl", "__builtin_ppc_minfl"); 281 Builder.defineMacro("__builtin_minfs", "__builtin_ppc_minfs"); 282 Builder.defineMacro("__builtin_mffs", "__builtin_ppc_mffs"); 283 Builder.defineMacro("__builtin_mffsl", "__builtin_ppc_mffsl"); 284 Builder.defineMacro("__builtin_mtfsf", "__builtin_ppc_mtfsf"); 285 Builder.defineMacro("__builtin_set_fpscr_rn", "__builtin_ppc_set_fpscr_rn"); 286 } 287 288 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 289 /// #defines that are not tied to a specific subtarget. 290 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 291 MacroBuilder &Builder) const { 292 293 // We define the XLC compatibility macros only on AIX and Linux since XLC 294 // was never available on any other platforms. 295 if (getTriple().isOSAIX() || getTriple().isOSLinux()) 296 defineXLCompatMacros(Builder); 297 298 // Target identification. 299 Builder.defineMacro("__ppc__"); 300 Builder.defineMacro("__PPC__"); 301 Builder.defineMacro("_ARCH_PPC"); 302 Builder.defineMacro("__powerpc__"); 303 Builder.defineMacro("__POWERPC__"); 304 if (PointerWidth == 64) { 305 Builder.defineMacro("_ARCH_PPC64"); 306 Builder.defineMacro("__powerpc64__"); 307 Builder.defineMacro("__PPC64__"); 308 } else if (getTriple().isOSAIX()) { 309 // The XL compilers on AIX define _ARCH_PPC64 for both 32 and 64-bit modes. 310 Builder.defineMacro("_ARCH_PPC64"); 311 } 312 if (getTriple().isOSAIX()) { 313 Builder.defineMacro("__THW_PPC__"); 314 // Define __PPC and __powerpc for AIX XL C/C++ compatibility 315 Builder.defineMacro("__PPC"); 316 Builder.defineMacro("__powerpc"); 317 } 318 319 // Target properties. 320 if (getTriple().getArch() == llvm::Triple::ppc64le || 321 getTriple().getArch() == llvm::Triple::ppcle) { 322 Builder.defineMacro("_LITTLE_ENDIAN"); 323 } else { 324 if (!getTriple().isOSNetBSD() && 325 !getTriple().isOSOpenBSD()) 326 Builder.defineMacro("_BIG_ENDIAN"); 327 } 328 329 // ABI options. 330 if (ABI == "elfv1") 331 Builder.defineMacro("_CALL_ELF", "1"); 332 if (ABI == "elfv2") 333 Builder.defineMacro("_CALL_ELF", "2"); 334 335 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 336 // our support post-dates this and it should work on all 64-bit ppc linux 337 // platforms. It is guaranteed to work on all elfv2 platforms. 338 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 339 Builder.defineMacro("_CALL_LINUX", "1"); 340 341 // Subtarget options. 342 if (!getTriple().isOSAIX()){ 343 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 344 } 345 Builder.defineMacro("__REGISTER_PREFIX__", ""); 346 347 // FIXME: Should be controlled by command line option. 348 if (LongDoubleWidth == 128) { 349 Builder.defineMacro("__LONG_DOUBLE_128__"); 350 Builder.defineMacro("__LONGDOUBLE128"); 351 if (Opts.PPCIEEELongDouble) 352 Builder.defineMacro("__LONG_DOUBLE_IEEE128__"); 353 else 354 Builder.defineMacro("__LONG_DOUBLE_IBM128__"); 355 } 356 357 if (getTriple().isOSAIX() && Opts.LongDoubleSize == 64) { 358 assert(LongDoubleWidth == 64); 359 Builder.defineMacro("__LONGDOUBLE64"); 360 } 361 362 // Define this for elfv2 (64-bit only). 363 if (ABI == "elfv2") 364 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 365 366 if (ArchDefs & ArchDefineName) 367 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 368 if (ArchDefs & ArchDefinePpcgr) 369 Builder.defineMacro("_ARCH_PPCGR"); 370 if (ArchDefs & ArchDefinePpcsq) 371 Builder.defineMacro("_ARCH_PPCSQ"); 372 if (ArchDefs & ArchDefine440) 373 Builder.defineMacro("_ARCH_440"); 374 if (ArchDefs & ArchDefine603) 375 Builder.defineMacro("_ARCH_603"); 376 if (ArchDefs & ArchDefine604) 377 Builder.defineMacro("_ARCH_604"); 378 if (ArchDefs & ArchDefinePwr4) 379 Builder.defineMacro("_ARCH_PWR4"); 380 if (ArchDefs & ArchDefinePwr5) 381 Builder.defineMacro("_ARCH_PWR5"); 382 if (ArchDefs & ArchDefinePwr5x) 383 Builder.defineMacro("_ARCH_PWR5X"); 384 if (ArchDefs & ArchDefinePwr6) 385 Builder.defineMacro("_ARCH_PWR6"); 386 if (ArchDefs & ArchDefinePwr6x) 387 Builder.defineMacro("_ARCH_PWR6X"); 388 if (ArchDefs & ArchDefinePwr7) 389 Builder.defineMacro("_ARCH_PWR7"); 390 if (ArchDefs & ArchDefinePwr8) 391 Builder.defineMacro("_ARCH_PWR8"); 392 if (ArchDefs & ArchDefinePwr9) 393 Builder.defineMacro("_ARCH_PWR9"); 394 if (ArchDefs & ArchDefinePwr10) 395 Builder.defineMacro("_ARCH_PWR10"); 396 if (ArchDefs & ArchDefinePwr11) 397 Builder.defineMacro("_ARCH_PWR11"); 398 if (ArchDefs & ArchDefineA2) 399 Builder.defineMacro("_ARCH_A2"); 400 if (ArchDefs & ArchDefineE500) 401 Builder.defineMacro("__NO_LWSYNC__"); 402 if (ArchDefs & ArchDefineFuture) 403 Builder.defineMacro("_ARCH_PWR_FUTURE"); 404 405 if (HasAltivec) { 406 Builder.defineMacro("__VEC__", "10206"); 407 Builder.defineMacro("__ALTIVEC__"); 408 } 409 if (HasSPE) 410 Builder.defineMacro("__SPE__"); 411 if (HasSPE || FloatABI == SoftFloat) 412 Builder.defineMacro("__NO_FPRS__"); 413 if (FloatABI == SoftFloat) { 414 Builder.defineMacro("_SOFT_FLOAT"); 415 Builder.defineMacro("_SOFT_DOUBLE"); 416 } else { 417 if (HasFrsqrte) 418 Builder.defineMacro("__RSQRTE__"); 419 if (HasFrsqrtes) 420 Builder.defineMacro("__RSQRTEF__"); 421 } 422 if (HasVSX) 423 Builder.defineMacro("__VSX__"); 424 if (HasP8Vector) 425 Builder.defineMacro("__POWER8_VECTOR__"); 426 if (HasP8Crypto) 427 Builder.defineMacro("__CRYPTO__"); 428 if (HasHTM) 429 Builder.defineMacro("__HTM__"); 430 if (HasFloat128) 431 Builder.defineMacro("__FLOAT128__"); 432 if (HasP9Vector) 433 Builder.defineMacro("__POWER9_VECTOR__"); 434 if (HasMMA) 435 Builder.defineMacro("__MMA__"); 436 if (HasROPProtect) 437 Builder.defineMacro("__ROP_PROTECT__"); 438 if (HasP10Vector) 439 Builder.defineMacro("__POWER10_VECTOR__"); 440 if (HasPCRelativeMemops) 441 Builder.defineMacro("__PCREL__"); 442 443 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 444 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 445 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 446 if (PointerWidth == 64) 447 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 448 449 // We have support for the bswap intrinsics so we can define this. 450 Builder.defineMacro("__HAVE_BSWAP__", "1"); 451 452 // FIXME: The following are not yet generated here by Clang, but are 453 // generated by GCC: 454 // 455 // __RECIP_PRECISION__ 456 // __APPLE_ALTIVEC__ 457 // __RECIP__ 458 // __RECIPF__ 459 // __NO_LWSYNC__ 460 // __CMODEL_MEDIUM__ 461 // __CMODEL_LARGE__ 462 // _CALL_SYSV 463 // _CALL_DARWIN 464 } 465 466 // Handle explicit options being passed to the compiler here: 467 // - if we've explicitly turned off vsx and turned on any of: 468 // - power8-vector 469 // - direct-move 470 // - float128 471 // - power9-vector 472 // - paired-vector-memops 473 // - mma 474 // - power10-vector 475 // - if we've explicitly turned on vsx and turned off altivec. 476 // - if we've explicitly turned off hard-float and turned on altivec. 477 // then go ahead and error since the customer has expressed an incompatible 478 // set of options. 479 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 480 const std::vector<std::string> &FeaturesVec) { 481 auto FindVSXSubfeature = [&](StringRef Feature, StringRef SubOption, 482 StringRef Option) { 483 if (llvm::is_contained(FeaturesVec, Feature)) { 484 Diags.Report(diag::err_opt_not_valid_with_opt) << SubOption << Option; 485 return true; 486 } 487 return false; 488 }; 489 490 // Cannot allow soft-float with VSX, Altivec, or any 491 // VSX subfeatures. 492 bool Found = false; 493 if (llvm::is_contained(FeaturesVec, "-hard-float")) { 494 Found |= FindVSXSubfeature("+vsx", "-mvsx", "-msoft-float"); 495 Found |= FindVSXSubfeature("+altivec", "-maltivec", "-msoft-float"); 496 Found |= 497 FindVSXSubfeature("+power8-vector", "-mpower8-vector", "-msoft-float"); 498 Found |= FindVSXSubfeature("+direct-move", "-mdirect-move", "-msoft-float"); 499 Found |= FindVSXSubfeature("+float128", "-mfloat128", "-msoft-float"); 500 Found |= 501 FindVSXSubfeature("+power9-vector", "-mpower9-vector", "-msoft-float"); 502 Found |= FindVSXSubfeature("+paired-vector-memops", 503 "-mpaired-vector-memops", "-msoft-float"); 504 Found |= FindVSXSubfeature("+mma", "-mmma", "-msoft-float"); 505 Found |= FindVSXSubfeature("+crypto", "-mcrypto", "-msoft-float"); 506 Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector", 507 "-msoft-float"); 508 } 509 if (Found) 510 return false; 511 512 // Cannot allow VSX with no Altivec. 513 if (llvm::is_contained(FeaturesVec, "+vsx") && 514 llvm::is_contained(FeaturesVec, "-altivec")) { 515 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mvsx" 516 << "-mno-altivec"; 517 return false; 518 } 519 520 // vsx was not explicitly turned off. 521 if (!llvm::is_contained(FeaturesVec, "-vsx")) 522 return true; 523 524 Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector", "-mno-vsx"); 525 Found |= FindVSXSubfeature("+direct-move", "-mdirect-move", "-mno-vsx"); 526 Found |= FindVSXSubfeature("+float128", "-mfloat128", "-mno-vsx"); 527 Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector", "-mno-vsx"); 528 Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops", 529 "-mno-vsx"); 530 Found |= FindVSXSubfeature("+mma", "-mmma", "-mno-vsx"); 531 Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector", "-mno-vsx"); 532 533 // Return false if any vsx subfeatures was found. 534 return !Found; 535 } 536 537 bool PPCTargetInfo::initFeatureMap( 538 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 539 const std::vector<std::string> &FeaturesVec) const { 540 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 541 .Case("7400", true) 542 .Case("g4", true) 543 .Case("7450", true) 544 .Case("g4+", true) 545 .Case("970", true) 546 .Case("g5", true) 547 .Case("pwr6", true) 548 .Case("pwr7", true) 549 .Case("pwr8", true) 550 .Case("pwr9", true) 551 .Case("ppc64", true) 552 .Case("ppc64le", true) 553 .Default(false); 554 555 Features["power9-vector"] = (CPU == "pwr9"); 556 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 557 .Case("ppc64le", true) 558 .Case("pwr9", true) 559 .Case("pwr8", true) 560 .Default(false); 561 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 562 .Case("ppc64le", true) 563 .Case("pwr9", true) 564 .Case("pwr8", true) 565 .Default(false); 566 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 567 .Case("ppc64le", true) 568 .Case("pwr9", true) 569 .Case("pwr8", true) 570 .Case("pwr7", true) 571 .Default(false); 572 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 573 .Case("ppc64le", true) 574 .Case("pwr9", true) 575 .Case("pwr8", true) 576 .Case("pwr7", true) 577 .Default(false); 578 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 579 .Case("ppc64le", true) 580 .Case("pwr9", true) 581 .Case("pwr8", true) 582 .Default(false); 583 Features["crbits"] = llvm::StringSwitch<bool>(CPU) 584 .Case("ppc64le", true) 585 .Case("pwr9", true) 586 .Case("pwr8", true) 587 .Default(false); 588 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 589 .Case("ppc64le", true) 590 .Case("pwr9", true) 591 .Case("pwr8", true) 592 .Case("pwr7", true) 593 .Default(false); 594 Features["htm"] = llvm::StringSwitch<bool>(CPU) 595 .Case("ppc64le", true) 596 .Case("pwr9", true) 597 .Case("pwr8", true) 598 .Default(false); 599 600 // ROP Protect is off by default. 601 Features["rop-protect"] = false; 602 // Privileged instructions are off by default. 603 Features["privileged"] = false; 604 605 // The code generated by the -maix-small-local-[exec|dynamic]-tls option is 606 // turned off by default. 607 Features["aix-small-local-exec-tls"] = false; 608 Features["aix-small-local-dynamic-tls"] = false; 609 610 // Turn off TLS model opt by default. 611 Features["aix-shared-lib-tls-model-opt"] = false; 612 613 Features["spe"] = llvm::StringSwitch<bool>(CPU) 614 .Case("8548", true) 615 .Case("e500", true) 616 .Default(false); 617 618 Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU) 619 .Case("ppc64le", true) 620 .Case("pwr9", true) 621 .Case("pwr8", true) 622 .Case("pwr7", true) 623 .Case("a2", true) 624 .Default(false); 625 626 Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU) 627 .Case("ppc64le", true) 628 .Case("pwr9", true) 629 .Case("pwr8", true) 630 .Default(false); 631 632 Features["isa-v30-instructions"] = 633 llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false); 634 635 Features["quadword-atomics"] = 636 getTriple().isArch64Bit() && llvm::StringSwitch<bool>(CPU) 637 .Case("pwr9", true) 638 .Case("pwr8", true) 639 .Default(false); 640 641 // Power10 includes all the same features as Power9 plus any features specific 642 // to the Power10 core. 643 if (CPU == "pwr10" || CPU == "power10") { 644 initFeatureMap(Features, Diags, "pwr9", FeaturesVec); 645 addP10SpecificFeatures(Features); 646 } 647 648 // Power11 includes all the same features as Power10 plus any features 649 // specific to the Power11 core. 650 if (CPU == "pwr11" || CPU == "power11") { 651 initFeatureMap(Features, Diags, "pwr10", FeaturesVec); 652 addP11SpecificFeatures(Features); 653 } 654 655 // Future CPU should include all of the features of Power 11 as well as any 656 // additional features (yet to be determined) specific to it. 657 if (CPU == "future") { 658 initFeatureMap(Features, Diags, "pwr11", FeaturesVec); 659 addFutureSpecificFeatures(Features); 660 } 661 662 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 663 return false; 664 665 if (!(ArchDefs & ArchDefinePwr7) && (ArchDefs & ArchDefinePpcgr) && 666 llvm::is_contained(FeaturesVec, "+float128")) { 667 // We have __float128 on PPC but not pre-VSX targets. 668 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU; 669 return false; 670 } 671 672 if (!(ArchDefs & ArchDefinePwr10)) { 673 if (llvm::is_contained(FeaturesVec, "+mma")) { 674 // MMA operations are not available pre-Power10. 675 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU; 676 return false; 677 } 678 if (llvm::is_contained(FeaturesVec, "+pcrel")) { 679 // PC-Relative instructions are not available pre-Power10, 680 // and these instructions also require prefixed instructions support. 681 Diags.Report(diag::err_opt_not_valid_without_opt) 682 << "-mpcrel" 683 << "-mcpu=pwr10 -mprefixed"; 684 return false; 685 } 686 if (llvm::is_contained(FeaturesVec, "+prefixed")) { 687 // Prefixed instructions are not available pre-Power10. 688 Diags.Report(diag::err_opt_not_valid_without_opt) << "-mprefixed" 689 << "-mcpu=pwr10"; 690 return false; 691 } 692 if (llvm::is_contained(FeaturesVec, "+paired-vector-memops")) { 693 // Paired vector memops are not available pre-Power10. 694 Diags.Report(diag::err_opt_not_valid_without_opt) 695 << "-mpaired-vector-memops" 696 << "-mcpu=pwr10"; 697 return false; 698 } 699 } 700 701 if (!(ArchDefs & ArchDefinePwr8) && 702 llvm::is_contained(FeaturesVec, "+rop-protect")) { 703 // We can turn on ROP Protect on Power 8 and above. 704 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mrop-protect" << CPU; 705 return false; 706 } 707 708 if (!(ArchDefs & ArchDefinePwr8) && 709 llvm::is_contained(FeaturesVec, "+privileged")) { 710 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mprivileged" << CPU; 711 return false; 712 } 713 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 714 } 715 716 // Add any Power10 specific features. 717 void PPCTargetInfo::addP10SpecificFeatures( 718 llvm::StringMap<bool> &Features) const { 719 Features["htm"] = false; // HTM was removed for P10. 720 Features["paired-vector-memops"] = true; 721 Features["mma"] = true; 722 Features["power10-vector"] = true; 723 Features["pcrelative-memops"] = true; 724 Features["prefix-instrs"] = true; 725 Features["isa-v31-instructions"] = true; 726 } 727 728 // Add any Power11 specific features. 729 void PPCTargetInfo::addP11SpecificFeatures( 730 llvm::StringMap<bool> &Features) const {} 731 732 // Add features specific to the "Future" CPU. 733 void PPCTargetInfo::addFutureSpecificFeatures( 734 llvm::StringMap<bool> &Features) const {} 735 736 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 737 return llvm::StringSwitch<bool>(Feature) 738 .Case("powerpc", true) 739 .Case("altivec", HasAltivec) 740 .Case("vsx", HasVSX) 741 .Case("crbits", UseCRBits) 742 .Case("power8-vector", HasP8Vector) 743 .Case("crypto", HasP8Crypto) 744 .Case("direct-move", HasDirectMove) 745 .Case("htm", HasHTM) 746 .Case("bpermd", HasBPERMD) 747 .Case("extdiv", HasExtDiv) 748 .Case("float128", HasFloat128) 749 .Case("power9-vector", HasP9Vector) 750 .Case("paired-vector-memops", PairedVectorMemops) 751 .Case("power10-vector", HasP10Vector) 752 .Case("pcrelative-memops", HasPCRelativeMemops) 753 .Case("prefix-instrs", HasPrefixInstrs) 754 .Case("spe", HasSPE) 755 .Case("mma", HasMMA) 756 .Case("rop-protect", HasROPProtect) 757 .Case("privileged", HasPrivileged) 758 .Case("aix-small-local-exec-tls", HasAIXSmallLocalExecTLS) 759 .Case("aix-small-local-dynamic-tls", HasAIXSmallLocalDynamicTLS) 760 .Case("isa-v206-instructions", IsISA2_06) 761 .Case("isa-v207-instructions", IsISA2_07) 762 .Case("isa-v30-instructions", IsISA3_0) 763 .Case("isa-v31-instructions", IsISA3_1) 764 .Case("quadword-atomics", HasQuadwordAtomics) 765 .Case("aix-shared-lib-tls-model-opt", HasAIXShLibTLSModelOpt) 766 .Case("longcall", UseLongCalls) 767 .Default(false); 768 } 769 770 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 771 StringRef Name, bool Enabled) const { 772 if (Enabled) { 773 if (Name == "efpu2") 774 Features["spe"] = true; 775 // If we're enabling any of the vsx based features then enable vsx and 776 // altivec. We'll diagnose any problems later. 777 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 778 .Case("vsx", true) 779 .Case("direct-move", true) 780 .Case("power8-vector", true) 781 .Case("power9-vector", true) 782 .Case("paired-vector-memops", true) 783 .Case("power10-vector", true) 784 .Case("float128", true) 785 .Case("mma", true) 786 .Default(false); 787 if (FeatureHasVSX) 788 Features["vsx"] = Features["altivec"] = true; 789 if (Name == "power9-vector") 790 Features["power8-vector"] = true; 791 else if (Name == "power10-vector") 792 Features["power8-vector"] = Features["power9-vector"] = true; 793 if (Name == "pcrel") 794 Features["pcrelative-memops"] = true; 795 else if (Name == "prefixed") 796 Features["prefix-instrs"] = true; 797 else 798 Features[Name] = true; 799 } else { 800 if (Name == "spe") 801 Features["efpu2"] = false; 802 // If we're disabling altivec, hard-float, or vsx go ahead and disable all 803 // of the vsx features. 804 if ((Name == "altivec") || (Name == "vsx") || (Name == "hard-float")) { 805 if (Name != "vsx") 806 Features["altivec"] = Features["crypto"] = false; 807 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 808 Features["float128"] = Features["power9-vector"] = 809 Features["paired-vector-memops"] = Features["mma"] = 810 Features["power10-vector"] = false; 811 } 812 if (Name == "power8-vector") 813 Features["power9-vector"] = Features["paired-vector-memops"] = 814 Features["mma"] = Features["power10-vector"] = false; 815 else if (Name == "power9-vector") 816 Features["paired-vector-memops"] = Features["mma"] = 817 Features["power10-vector"] = false; 818 if (Name == "pcrel") 819 Features["pcrelative-memops"] = false; 820 else if (Name == "prefixed") 821 Features["prefix-instrs"] = false; 822 else 823 Features[Name] = false; 824 } 825 } 826 827 // Make sure that registers are added in the correct array index which should be 828 // the DWARF number for PPC registers. 829 const char *const PPCTargetInfo::GCCRegNames[] = { 830 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", 831 "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", 832 "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", 833 "r27", "r28", "r29", "r30", "r31", "f0", "f1", "f2", "f3", 834 "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", 835 "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", 836 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", 837 "f31", "mq", "lr", "ctr", "ap", "cr0", "cr1", "cr2", "cr3", 838 "cr4", "cr5", "cr6", "cr7", "xer", "v0", "v1", "v2", "v3", 839 "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", 840 "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 841 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", 842 "v31", "vrsave", "vscr", "spe_acc", "spefscr", "sfp" 843 }; 844 845 ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const { 846 return llvm::ArrayRef(GCCRegNames); 847 } 848 849 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 850 // While some of these aliases do map to different registers 851 // they still share the same register name. 852 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"}, 853 {{"3"}, "r3"}, {{"4"}, "r4"}, {{"5"}, "r5"}, 854 {{"6"}, "r6"}, {{"7"}, "r7"}, {{"8"}, "r8"}, 855 {{"9"}, "r9"}, {{"10"}, "r10"}, {{"11"}, "r11"}, 856 {{"12"}, "r12"}, {{"13"}, "r13"}, {{"14"}, "r14"}, 857 {{"15"}, "r15"}, {{"16"}, "r16"}, {{"17"}, "r17"}, 858 {{"18"}, "r18"}, {{"19"}, "r19"}, {{"20"}, "r20"}, 859 {{"21"}, "r21"}, {{"22"}, "r22"}, {{"23"}, "r23"}, 860 {{"24"}, "r24"}, {{"25"}, "r25"}, {{"26"}, "r26"}, 861 {{"27"}, "r27"}, {{"28"}, "r28"}, {{"29"}, "r29"}, 862 {{"30"}, "r30"}, {{"31"}, "r31"}, {{"fr0"}, "f0"}, 863 {{"fr1"}, "f1"}, {{"fr2"}, "f2"}, {{"fr3"}, "f3"}, 864 {{"fr4"}, "f4"}, {{"fr5"}, "f5"}, {{"fr6"}, "f6"}, 865 {{"fr7"}, "f7"}, {{"fr8"}, "f8"}, {{"fr9"}, "f9"}, 866 {{"fr10"}, "f10"}, {{"fr11"}, "f11"}, {{"fr12"}, "f12"}, 867 {{"fr13"}, "f13"}, {{"fr14"}, "f14"}, {{"fr15"}, "f15"}, 868 {{"fr16"}, "f16"}, {{"fr17"}, "f17"}, {{"fr18"}, "f18"}, 869 {{"fr19"}, "f19"}, {{"fr20"}, "f20"}, {{"fr21"}, "f21"}, 870 {{"fr22"}, "f22"}, {{"fr23"}, "f23"}, {{"fr24"}, "f24"}, 871 {{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"}, 872 {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"}, 873 {{"fr31"}, "f31"}, {{"cc"}, "cr0"}, 874 }; 875 876 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 877 return llvm::ArrayRef(GCCRegAliases); 878 } 879 880 // PPC ELFABIv2 DWARF Definition "Table 2.26. Mappings of Common Registers". 881 // vs0 ~ vs31 is mapping to 32 - 63, 882 // vs32 ~ vs63 is mapping to 77 - 108. 883 // And this mapping applies to all OSes which run on powerpc. 884 const TargetInfo::AddlRegName GCCAddlRegNames[] = { 885 // Table of additional register names to use in user input. 886 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35}, 887 {{"vs4"}, 36}, {{"vs5"}, 37}, {{"vs6"}, 38}, {{"vs7"}, 39}, 888 {{"vs8"}, 40}, {{"vs9"}, 41}, {{"vs10"}, 42}, {{"vs11"}, 43}, 889 {{"vs12"}, 44}, {{"vs13"}, 45}, {{"vs14"}, 46}, {{"vs15"}, 47}, 890 {{"vs16"}, 48}, {{"vs17"}, 49}, {{"vs18"}, 50}, {{"vs19"}, 51}, 891 {{"vs20"}, 52}, {{"vs21"}, 53}, {{"vs22"}, 54}, {{"vs23"}, 55}, 892 {{"vs24"}, 56}, {{"vs25"}, 57}, {{"vs26"}, 58}, {{"vs27"}, 59}, 893 {{"vs28"}, 60}, {{"vs29"}, 61}, {{"vs30"}, 62}, {{"vs31"}, 63}, 894 {{"vs32"}, 77}, {{"vs33"}, 78}, {{"vs34"}, 79}, {{"vs35"}, 80}, 895 {{"vs36"}, 81}, {{"vs37"}, 82}, {{"vs38"}, 83}, {{"vs39"}, 84}, 896 {{"vs40"}, 85}, {{"vs41"}, 86}, {{"vs42"}, 87}, {{"vs43"}, 88}, 897 {{"vs44"}, 89}, {{"vs45"}, 90}, {{"vs46"}, 91}, {{"vs47"}, 92}, 898 {{"vs48"}, 93}, {{"vs49"}, 94}, {{"vs50"}, 95}, {{"vs51"}, 96}, 899 {{"vs52"}, 97}, {{"vs53"}, 98}, {{"vs54"}, 99}, {{"vs55"}, 100}, 900 {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104}, 901 {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108}, 902 }; 903 904 ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const { 905 return llvm::ArrayRef(GCCAddlRegNames); 906 } 907 908 bool PPCTargetInfo::isValidCPUName(StringRef Name) const { 909 return llvm::PPC::isValidCPU(Name); 910 } 911 912 void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { 913 llvm::PPC::fillValidCPUList(Values); 914 } 915 916 void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) { 917 if (HasAltivec) 918 Opts.AltiVec = 1; 919 TargetInfo::adjust(Diags, Opts); 920 if (LongDoubleFormat != &llvm::APFloat::IEEEdouble()) 921 LongDoubleFormat = Opts.PPCIEEELongDouble 922 ? &llvm::APFloat::IEEEquad() 923 : &llvm::APFloat::PPCDoubleDouble(); 924 Opts.IEEE128 = 1; 925 if (getTriple().isOSAIX() && Opts.EnableAIXQuadwordAtomicsABI && 926 HasQuadwordAtomics) 927 MaxAtomicInlineWidth = 128; 928 } 929 930 ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const { 931 return llvm::ArrayRef(BuiltinInfo, 932 clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin); 933 } 934 935 bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const { 936 llvm::Triple Triple = getTriple(); 937 if (Triple.isOSAIX()) { 938 #define PPC_AIX_FEATURE(NAME, DESC, SUPPORT_METHOD, INDEX, MASK, COMP_OP, \ 939 VALUE) \ 940 .Case(NAME, true) 941 return llvm::StringSwitch<bool>(FeatureStr) 942 #include "llvm/TargetParser/PPCTargetParser.def" 943 .Default(false); 944 } 945 946 assert(Triple.isOSLinux() && 947 "__builtin_cpu_supports() is only supported for AIX and Linux."); 948 949 #define PPC_LNX_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true) 950 return llvm::StringSwitch<bool>(FeatureStr) 951 #include "llvm/TargetParser/PPCTargetParser.def" 952 .Default(false); 953 } 954 955 bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const { 956 llvm::Triple Triple = getTriple(); 957 assert((Triple.isOSAIX() || Triple.isOSLinux()) && 958 "__builtin_cpu_is() is only supported for AIX and Linux."); 959 960 #define PPC_CPU(NAME, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, \ 961 AIXID) \ 962 .Case(NAME, {Linux_SUPPORT_METHOD, AIX_SUPPORT_METHOD}) 963 964 std::pair<unsigned, unsigned> SuppportMethod = 965 llvm::StringSwitch<std::pair<unsigned, unsigned>>(CPUName) 966 #include "llvm/TargetParser/PPCTargetParser.def" 967 .Default({BUILTIN_PPC_UNSUPPORTED, BUILTIN_PPC_UNSUPPORTED}); 968 return Triple.isOSLinux() 969 ? (SuppportMethod.first != BUILTIN_PPC_UNSUPPORTED) 970 : (SuppportMethod.second != BUILTIN_PPC_UNSUPPORTED); 971 } 972