1 //===- bolt/Core/Relocation.cpp - Object file relocations -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the Relocation class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "bolt/Core/Relocation.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCStreamer.h" 17 #include "llvm/MC/MCSymbol.h" 18 #include "llvm/Object/ELF.h" 19 20 using namespace llvm; 21 using namespace bolt; 22 23 namespace ELFReserved { 24 enum { 25 R_RISCV_TPREL_I = 49, 26 R_RISCV_TPREL_S = 50, 27 }; 28 } // namespace ELFReserved 29 30 Triple::ArchType Relocation::Arch; 31 32 static bool isSupportedX86(uint64_t Type) { 33 switch (Type) { 34 default: 35 return false; 36 case ELF::R_X86_64_8: 37 case ELF::R_X86_64_16: 38 case ELF::R_X86_64_32: 39 case ELF::R_X86_64_32S: 40 case ELF::R_X86_64_64: 41 case ELF::R_X86_64_PC8: 42 case ELF::R_X86_64_PC32: 43 case ELF::R_X86_64_PC64: 44 case ELF::R_X86_64_PLT32: 45 case ELF::R_X86_64_GOTPC64: 46 case ELF::R_X86_64_GOTPCREL: 47 case ELF::R_X86_64_GOTTPOFF: 48 case ELF::R_X86_64_TPOFF32: 49 case ELF::R_X86_64_GOTPCRELX: 50 case ELF::R_X86_64_REX_GOTPCRELX: 51 return true; 52 } 53 } 54 55 static bool isSupportedAArch64(uint64_t Type) { 56 switch (Type) { 57 default: 58 return false; 59 case ELF::R_AARCH64_CALL26: 60 case ELF::R_AARCH64_JUMP26: 61 case ELF::R_AARCH64_TSTBR14: 62 case ELF::R_AARCH64_CONDBR19: 63 case ELF::R_AARCH64_ADR_PREL_LO21: 64 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 65 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 66 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 67 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 68 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 69 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 70 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 71 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 72 case ELF::R_AARCH64_ADR_GOT_PAGE: 73 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 74 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 75 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 76 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 77 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 78 case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0: 79 case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: 80 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 81 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 82 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 83 case ELF::R_AARCH64_TLSDESC_CALL: 84 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 85 case ELF::R_AARCH64_PREL16: 86 case ELF::R_AARCH64_PREL32: 87 case ELF::R_AARCH64_PREL64: 88 case ELF::R_AARCH64_ABS16: 89 case ELF::R_AARCH64_ABS32: 90 case ELF::R_AARCH64_ABS64: 91 case ELF::R_AARCH64_MOVW_UABS_G0: 92 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 93 case ELF::R_AARCH64_MOVW_UABS_G1: 94 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 95 case ELF::R_AARCH64_MOVW_UABS_G2: 96 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 97 case ELF::R_AARCH64_MOVW_UABS_G3: 98 return true; 99 } 100 } 101 102 static bool isSupportedRISCV(uint64_t Type) { 103 switch (Type) { 104 default: 105 return false; 106 case ELF::R_RISCV_JAL: 107 case ELF::R_RISCV_CALL: 108 case ELF::R_RISCV_CALL_PLT: 109 case ELF::R_RISCV_BRANCH: 110 case ELF::R_RISCV_RELAX: 111 case ELF::R_RISCV_GOT_HI20: 112 case ELF::R_RISCV_PCREL_HI20: 113 case ELF::R_RISCV_PCREL_LO12_I: 114 case ELF::R_RISCV_PCREL_LO12_S: 115 case ELF::R_RISCV_RVC_JUMP: 116 case ELF::R_RISCV_RVC_BRANCH: 117 case ELF::R_RISCV_ADD32: 118 case ELF::R_RISCV_SUB32: 119 case ELF::R_RISCV_HI20: 120 case ELF::R_RISCV_LO12_I: 121 case ELF::R_RISCV_LO12_S: 122 case ELF::R_RISCV_64: 123 case ELF::R_RISCV_TLS_GOT_HI20: 124 case ELF::R_RISCV_TPREL_HI20: 125 case ELF::R_RISCV_TPREL_ADD: 126 case ELF::R_RISCV_TPREL_LO12_I: 127 case ELF::R_RISCV_TPREL_LO12_S: 128 case ELFReserved::R_RISCV_TPREL_I: 129 case ELFReserved::R_RISCV_TPREL_S: 130 return true; 131 } 132 } 133 134 static size_t getSizeForTypeX86(uint64_t Type) { 135 switch (Type) { 136 default: 137 errs() << object::getELFRelocationTypeName(ELF::EM_X86_64, Type) << '\n'; 138 llvm_unreachable("unsupported relocation type"); 139 case ELF::R_X86_64_8: 140 case ELF::R_X86_64_PC8: 141 return 1; 142 case ELF::R_X86_64_16: 143 return 2; 144 case ELF::R_X86_64_PLT32: 145 case ELF::R_X86_64_PC32: 146 case ELF::R_X86_64_32S: 147 case ELF::R_X86_64_32: 148 case ELF::R_X86_64_GOTPCREL: 149 case ELF::R_X86_64_GOTTPOFF: 150 case ELF::R_X86_64_TPOFF32: 151 case ELF::R_X86_64_GOTPCRELX: 152 case ELF::R_X86_64_REX_GOTPCRELX: 153 return 4; 154 case ELF::R_X86_64_PC64: 155 case ELF::R_X86_64_64: 156 case ELF::R_X86_64_GOTPC64: 157 return 8; 158 } 159 } 160 161 static size_t getSizeForTypeAArch64(uint64_t Type) { 162 switch (Type) { 163 default: 164 errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n'; 165 llvm_unreachable("unsupported relocation type"); 166 case ELF::R_AARCH64_ABS16: 167 case ELF::R_AARCH64_PREL16: 168 return 2; 169 case ELF::R_AARCH64_CALL26: 170 case ELF::R_AARCH64_JUMP26: 171 case ELF::R_AARCH64_TSTBR14: 172 case ELF::R_AARCH64_CONDBR19: 173 case ELF::R_AARCH64_ADR_PREL_LO21: 174 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 175 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 176 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 177 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 178 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 179 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 180 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 181 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 182 case ELF::R_AARCH64_ADR_GOT_PAGE: 183 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 184 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 185 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 186 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 187 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 188 case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0: 189 case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: 190 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 191 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 192 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 193 case ELF::R_AARCH64_TLSDESC_CALL: 194 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 195 case ELF::R_AARCH64_PREL32: 196 case ELF::R_AARCH64_MOVW_UABS_G0: 197 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 198 case ELF::R_AARCH64_MOVW_UABS_G1: 199 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 200 case ELF::R_AARCH64_MOVW_UABS_G2: 201 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 202 case ELF::R_AARCH64_MOVW_UABS_G3: 203 case ELF::R_AARCH64_ABS32: 204 return 4; 205 case ELF::R_AARCH64_ABS64: 206 case ELF::R_AARCH64_PREL64: 207 return 8; 208 } 209 } 210 211 static size_t getSizeForTypeRISCV(uint64_t Type) { 212 switch (Type) { 213 default: 214 errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n'; 215 llvm_unreachable("unsupported relocation type"); 216 case ELF::R_RISCV_RVC_JUMP: 217 case ELF::R_RISCV_RVC_BRANCH: 218 return 2; 219 case ELF::R_RISCV_JAL: 220 case ELF::R_RISCV_BRANCH: 221 case ELF::R_RISCV_PCREL_HI20: 222 case ELF::R_RISCV_PCREL_LO12_I: 223 case ELF::R_RISCV_PCREL_LO12_S: 224 case ELF::R_RISCV_32_PCREL: 225 case ELF::R_RISCV_CALL: 226 case ELF::R_RISCV_CALL_PLT: 227 case ELF::R_RISCV_ADD32: 228 case ELF::R_RISCV_SUB32: 229 case ELF::R_RISCV_HI20: 230 case ELF::R_RISCV_LO12_I: 231 case ELF::R_RISCV_LO12_S: 232 return 4; 233 case ELF::R_RISCV_64: 234 case ELF::R_RISCV_GOT_HI20: 235 case ELF::R_RISCV_TLS_GOT_HI20: 236 // See extractValueRISCV for why this is necessary. 237 return 8; 238 } 239 } 240 241 static bool skipRelocationTypeX86(uint64_t Type) { 242 return Type == ELF::R_X86_64_NONE; 243 } 244 245 static bool skipRelocationTypeAArch64(uint64_t Type) { 246 return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19; 247 } 248 249 static bool skipRelocationTypeRISCV(uint64_t Type) { 250 switch (Type) { 251 default: 252 return false; 253 case ELF::R_RISCV_NONE: 254 case ELF::R_RISCV_RELAX: 255 return true; 256 } 257 } 258 259 static bool skipRelocationProcessX86(uint64_t &Type, uint64_t Contents) { 260 return false; 261 } 262 263 static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) { 264 auto IsMov = [](uint64_t Contents) -> bool { 265 // The bits 28-23 are 0b100101 266 return (Contents & 0x1f800000) == 0x12800000; 267 }; 268 269 auto IsB = [](uint64_t Contents) -> bool { 270 // The bits 31-26 are 0b000101 271 return (Contents & 0xfc000000) == 0x14000000; 272 }; 273 274 auto IsAdr = [](uint64_t Contents) -> bool { 275 // The bits 31-24 are 0b0xx10000 276 return (Contents & 0x9f000000) == 0x10000000; 277 }; 278 279 auto IsAddImm = [](uint64_t Contents) -> bool { 280 // The bits 30-23 are 0b00100010 281 return (Contents & 0x7F800000) == 0x11000000; 282 }; 283 284 auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; }; 285 286 // The linker might eliminate the instruction and replace it with NOP, ignore 287 if (IsNop(Contents)) 288 return true; 289 290 // The linker might relax ADRP+LDR instruction sequence for loading symbol 291 // address from GOT table to ADRP+ADD sequence that would point to the 292 // binary-local symbol. Change relocation type in order to process it right. 293 if (Type == ELF::R_AARCH64_LD64_GOT_LO12_NC && IsAddImm(Contents)) { 294 Type = ELF::R_AARCH64_ADD_ABS_LO12_NC; 295 return false; 296 } 297 298 // The linker might perform TLS relocations relaxations, such as 299 // changed TLS access model (e.g. changed global dynamic model 300 // to initial exec), thus changing the instructions. The static 301 // relocations might be invalid at this point and we might no 302 // need to process these relocations anymore. 303 // More information could be found by searching 304 // elfNN_aarch64_tls_relax in bfd 305 switch (Type) { 306 default: 307 break; 308 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 309 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 310 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 311 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: { 312 if (IsMov(Contents)) 313 return true; 314 } 315 } 316 317 // The linker might replace load/store instruction with jump and 318 // veneer due to errata 843419 319 // https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d 320 // Thus load/store relocations for these instructions must be ignored 321 // NOTE: We only process GOT and TLS relocations this way since the 322 // addend used in load/store instructions won't change after bolt 323 // (it is important since the instruction in veneer won't have relocation) 324 switch (Type) { 325 default: 326 break; 327 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 328 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 329 case ELF::R_AARCH64_TLSDESC_LD64_LO12: { 330 if (IsB(Contents)) 331 return true; 332 } 333 } 334 335 // The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP 336 switch (Type) { 337 default: 338 break; 339 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 340 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 341 case ELF::R_AARCH64_ADR_GOT_PAGE: 342 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 343 if (IsAdr(Contents)) 344 return true; 345 } 346 347 return false; 348 } 349 350 static bool skipRelocationProcessRISCV(uint64_t &Type, uint64_t Contents) { 351 return false; 352 } 353 354 static uint64_t encodeValueX86(uint64_t Type, uint64_t Value, uint64_t PC) { 355 switch (Type) { 356 default: 357 llvm_unreachable("unsupported relocation"); 358 case ELF::R_X86_64_64: 359 case ELF::R_X86_64_32: 360 break; 361 case ELF::R_X86_64_PC32: 362 Value -= PC; 363 break; 364 } 365 return Value; 366 } 367 368 static uint64_t encodeValueAArch64(uint64_t Type, uint64_t Value, uint64_t PC) { 369 switch (Type) { 370 default: 371 llvm_unreachable("unsupported relocation"); 372 case ELF::R_AARCH64_ABS16: 373 case ELF::R_AARCH64_ABS32: 374 case ELF::R_AARCH64_ABS64: 375 break; 376 case ELF::R_AARCH64_PREL16: 377 case ELF::R_AARCH64_PREL32: 378 case ELF::R_AARCH64_PREL64: 379 Value -= PC; 380 break; 381 case ELF::R_AARCH64_CALL26: 382 Value -= PC; 383 assert(isInt<28>(Value) && "only PC +/- 128MB is allowed for direct call"); 384 // Immediate goes in bits 25:0 of BL. 385 // OP 1001_01 goes in bits 31:26 of BL. 386 Value = ((Value >> 2) & 0x3ffffff) | 0x94000000ULL; 387 break; 388 case ELF::R_AARCH64_JUMP26: 389 Value -= PC; 390 assert(isInt<28>(Value) && 391 "only PC +/- 128MB is allowed for direct branch"); 392 // Immediate goes in bits 25:0 of B. 393 // OP 0001_01 goes in bits 31:26 of B. 394 Value = ((Value >> 2) & 0x3ffffff) | 0x14000000ULL; 395 break; 396 } 397 return Value; 398 } 399 400 static uint64_t encodeValueRISCV(uint64_t Type, uint64_t Value, uint64_t PC) { 401 switch (Type) { 402 default: 403 llvm_unreachable("unsupported relocation"); 404 case ELF::R_RISCV_64: 405 break; 406 } 407 return Value; 408 } 409 410 static uint64_t extractValueX86(uint64_t Type, uint64_t Contents, uint64_t PC) { 411 if (Type == ELF::R_X86_64_32S) 412 return SignExtend64<32>(Contents); 413 if (Relocation::isPCRelative(Type)) 414 return SignExtend64(Contents, 8 * Relocation::getSizeForType(Type)); 415 return Contents; 416 } 417 418 static uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents, 419 uint64_t PC) { 420 switch (Type) { 421 default: 422 errs() << object::getELFRelocationTypeName(ELF::EM_AARCH64, Type) << '\n'; 423 llvm_unreachable("unsupported relocation type"); 424 case ELF::R_AARCH64_ABS16: 425 case ELF::R_AARCH64_ABS32: 426 case ELF::R_AARCH64_ABS64: 427 return Contents; 428 case ELF::R_AARCH64_PREL16: 429 return static_cast<int64_t>(PC) + SignExtend64<16>(Contents & 0xffff); 430 case ELF::R_AARCH64_PREL32: 431 return static_cast<int64_t>(PC) + SignExtend64<32>(Contents & 0xffffffff); 432 case ELF::R_AARCH64_PREL64: 433 return static_cast<int64_t>(PC) + Contents; 434 case ELF::R_AARCH64_TLSDESC_CALL: 435 case ELF::R_AARCH64_JUMP26: 436 case ELF::R_AARCH64_CALL26: 437 // Immediate goes in bits 25:0 of B and BL. 438 Contents &= ~0xfffffffffc000000ULL; 439 return static_cast<int64_t>(PC) + SignExtend64<28>(Contents << 2); 440 case ELF::R_AARCH64_TSTBR14: 441 // Immediate:15:2 goes in bits 18:5 of TBZ, TBNZ 442 Contents &= ~0xfffffffffff8001fULL; 443 return static_cast<int64_t>(PC) + SignExtend64<16>(Contents >> 3); 444 case ELF::R_AARCH64_CONDBR19: 445 // Immediate:20:2 goes in bits 23:5 of Bcc, CBZ, CBNZ 446 Contents &= ~0xffffffffff00001fULL; 447 return static_cast<int64_t>(PC) + SignExtend64<21>(Contents >> 3); 448 case ELF::R_AARCH64_ADR_GOT_PAGE: 449 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 450 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 451 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 452 case ELF::R_AARCH64_ADR_PREL_LO21: 453 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 454 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: { 455 // Bits 32:12 of Symbol address goes in bits 30:29 + 23:5 of ADRP 456 // and ADR instructions 457 bool IsAdr = !!(((Contents >> 31) & 0x1) == 0); 458 Contents &= ~0xffffffff9f00001fUll; 459 uint64_t LowBits = (Contents >> 29) & 0x3; 460 uint64_t HighBits = (Contents >> 5) & 0x7ffff; 461 Contents = LowBits | (HighBits << 2); 462 if (IsAdr) 463 return static_cast<int64_t>(PC) + SignExtend64<21>(Contents); 464 465 // ADRP instruction 466 Contents = static_cast<int64_t>(PC) + SignExtend64<33>(Contents << 12); 467 Contents &= ~0xfffUll; 468 return Contents; 469 } 470 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 471 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 472 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 473 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: { 474 // Immediate goes in bits 21:10 of LD/ST instruction, taken 475 // from bits 11:3 of Symbol address 476 Contents &= ~0xffffffffffc003ffU; 477 return Contents >> (10 - 3); 478 } 479 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 480 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 481 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 482 case ELF::R_AARCH64_ADD_ABS_LO12_NC: { 483 // Immediate goes in bits 21:10 of ADD instruction 484 Contents &= ~0xffffffffffc003ffU; 485 return Contents >> (10 - 0); 486 } 487 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: { 488 // Immediate goes in bits 21:10 of ADD instruction, taken 489 // from bits 11:4 of Symbol address 490 Contents &= ~0xffffffffffc003ffU; 491 return Contents >> (10 - 4); 492 } 493 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: { 494 // Immediate goes in bits 21:10 of ADD instruction, taken 495 // from bits 11:2 of Symbol address 496 Contents &= ~0xffffffffffc003ffU; 497 return Contents >> (10 - 2); 498 } 499 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: { 500 // Immediate goes in bits 21:10 of ADD instruction, taken 501 // from bits 11:1 of Symbol address 502 Contents &= ~0xffffffffffc003ffU; 503 return Contents >> (10 - 1); 504 } 505 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: { 506 // Immediate goes in bits 21:10 of ADD instruction, taken 507 // from bits 11:0 of Symbol address 508 Contents &= ~0xffffffffffc003ffU; 509 return Contents >> (10 - 0); 510 } 511 case ELF::R_AARCH64_MOVW_UABS_G3: 512 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 513 case ELF::R_AARCH64_MOVW_UABS_G2: 514 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 515 case ELF::R_AARCH64_MOVW_UABS_G1: 516 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 517 case ELF::R_AARCH64_MOVW_UABS_G0: 518 // The shift goes in bits 22:21 of MOV* instructions 519 uint8_t Shift = (Contents >> 21) & 0x3; 520 // Immediate goes in bits 20:5 521 Contents = (Contents >> 5) & 0xffff; 522 return Contents << (16 * Shift); 523 } 524 } 525 526 static uint64_t extractUImmRISCV(uint32_t Contents) { 527 return SignExtend64<32>(Contents & 0xfffff000); 528 } 529 530 static uint64_t extractIImmRISCV(uint32_t Contents) { 531 return SignExtend64<12>(Contents >> 20); 532 } 533 534 static uint64_t extractSImmRISCV(uint32_t Contents) { 535 return SignExtend64<12>(((Contents >> 7) & 0x1f) | ((Contents >> 25) << 5)); 536 } 537 538 static uint64_t extractJImmRISCV(uint32_t Contents) { 539 return SignExtend64<21>( 540 (((Contents >> 21) & 0x3ff) << 1) | (((Contents >> 20) & 0x1) << 11) | 541 (((Contents >> 12) & 0xff) << 12) | (((Contents >> 31) & 0x1) << 20)); 542 } 543 544 static uint64_t extractBImmRISCV(uint32_t Contents) { 545 return SignExtend64<13>( 546 (((Contents >> 8) & 0xf) << 1) | (((Contents >> 25) & 0x3f) << 5) | 547 (((Contents >> 7) & 0x1) << 11) | (((Contents >> 31) & 0x1) << 12)); 548 } 549 550 static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents, 551 uint64_t PC) { 552 switch (Type) { 553 default: 554 errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n'; 555 llvm_unreachable("unsupported relocation type"); 556 case ELF::R_RISCV_JAL: 557 return extractJImmRISCV(Contents); 558 case ELF::R_RISCV_CALL: 559 case ELF::R_RISCV_CALL_PLT: 560 return extractUImmRISCV(Contents); 561 case ELF::R_RISCV_BRANCH: 562 return extractBImmRISCV(Contents); 563 case ELF::R_RISCV_GOT_HI20: 564 case ELF::R_RISCV_TLS_GOT_HI20: 565 // We need to know the exact address of the GOT entry so we extract the 566 // value from both the AUIPC and L[D|W]. We cannot rely on the symbol in the 567 // relocation for this since it simply refers to the object that is stored 568 // in the GOT entry, not to the entry itself. 569 return extractUImmRISCV(Contents & 0xffffffff) + 570 extractIImmRISCV(Contents >> 32); 571 case ELF::R_RISCV_PCREL_HI20: 572 case ELF::R_RISCV_HI20: 573 return extractUImmRISCV(Contents); 574 case ELF::R_RISCV_PCREL_LO12_I: 575 case ELF::R_RISCV_LO12_I: 576 return extractIImmRISCV(Contents); 577 case ELF::R_RISCV_PCREL_LO12_S: 578 case ELF::R_RISCV_LO12_S: 579 return extractSImmRISCV(Contents); 580 case ELF::R_RISCV_RVC_JUMP: 581 return SignExtend64<11>(Contents >> 2); 582 case ELF::R_RISCV_RVC_BRANCH: 583 return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0)); 584 case ELF::R_RISCV_ADD32: 585 case ELF::R_RISCV_SUB32: 586 case ELF::R_RISCV_64: 587 return Contents; 588 } 589 } 590 591 static bool isGOTX86(uint64_t Type) { 592 switch (Type) { 593 default: 594 return false; 595 case ELF::R_X86_64_GOT32: 596 case ELF::R_X86_64_GOTPCREL: 597 case ELF::R_X86_64_GOTTPOFF: 598 case ELF::R_X86_64_GOTOFF64: 599 case ELF::R_X86_64_GOTPC32: 600 case ELF::R_X86_64_GOT64: 601 case ELF::R_X86_64_GOTPCREL64: 602 case ELF::R_X86_64_GOTPC64: 603 case ELF::R_X86_64_GOTPLT64: 604 case ELF::R_X86_64_GOTPC32_TLSDESC: 605 case ELF::R_X86_64_GOTPCRELX: 606 case ELF::R_X86_64_REX_GOTPCRELX: 607 return true; 608 } 609 } 610 611 static bool isGOTAArch64(uint64_t Type) { 612 switch (Type) { 613 default: 614 return false; 615 case ELF::R_AARCH64_ADR_GOT_PAGE: 616 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 617 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 618 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 619 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 620 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 621 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 622 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 623 case ELF::R_AARCH64_TLSDESC_CALL: 624 return true; 625 } 626 } 627 628 static bool isGOTRISCV(uint64_t Type) { 629 switch (Type) { 630 default: 631 return false; 632 case ELF::R_RISCV_GOT_HI20: 633 case ELF::R_RISCV_TLS_GOT_HI20: 634 return true; 635 } 636 } 637 638 static bool isTLSX86(uint64_t Type) { 639 switch (Type) { 640 default: 641 return false; 642 case ELF::R_X86_64_TPOFF32: 643 case ELF::R_X86_64_TPOFF64: 644 case ELF::R_X86_64_GOTTPOFF: 645 return true; 646 } 647 } 648 649 static bool isTLSAArch64(uint64_t Type) { 650 switch (Type) { 651 default: 652 return false; 653 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 654 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 655 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 656 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 657 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 658 case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0: 659 case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: 660 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 661 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 662 case ELF::R_AARCH64_TLSDESC_CALL: 663 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 664 return true; 665 } 666 } 667 668 static bool isTLSRISCV(uint64_t Type) { 669 switch (Type) { 670 default: 671 return false; 672 case ELF::R_RISCV_TLS_GOT_HI20: 673 case ELF::R_RISCV_TPREL_HI20: 674 case ELF::R_RISCV_TPREL_ADD: 675 case ELF::R_RISCV_TPREL_LO12_I: 676 case ELF::R_RISCV_TPREL_LO12_S: 677 case ELFReserved::R_RISCV_TPREL_I: 678 case ELFReserved::R_RISCV_TPREL_S: 679 return true; 680 } 681 } 682 683 static bool isPCRelativeX86(uint64_t Type) { 684 switch (Type) { 685 default: 686 llvm_unreachable("Unknown relocation type"); 687 case ELF::R_X86_64_64: 688 case ELF::R_X86_64_32: 689 case ELF::R_X86_64_32S: 690 case ELF::R_X86_64_16: 691 case ELF::R_X86_64_8: 692 case ELF::R_X86_64_TPOFF32: 693 return false; 694 case ELF::R_X86_64_PC8: 695 case ELF::R_X86_64_PC32: 696 case ELF::R_X86_64_PC64: 697 case ELF::R_X86_64_GOTPCREL: 698 case ELF::R_X86_64_PLT32: 699 case ELF::R_X86_64_GOTOFF64: 700 case ELF::R_X86_64_GOTPC32: 701 case ELF::R_X86_64_GOTPC64: 702 case ELF::R_X86_64_GOTTPOFF: 703 case ELF::R_X86_64_GOTPCRELX: 704 case ELF::R_X86_64_REX_GOTPCRELX: 705 return true; 706 } 707 } 708 709 static bool isPCRelativeAArch64(uint64_t Type) { 710 switch (Type) { 711 default: 712 llvm_unreachable("Unknown relocation type"); 713 case ELF::R_AARCH64_ABS16: 714 case ELF::R_AARCH64_ABS32: 715 case ELF::R_AARCH64_ABS64: 716 case ELF::R_AARCH64_LDST64_ABS_LO12_NC: 717 case ELF::R_AARCH64_ADD_ABS_LO12_NC: 718 case ELF::R_AARCH64_LDST128_ABS_LO12_NC: 719 case ELF::R_AARCH64_LDST32_ABS_LO12_NC: 720 case ELF::R_AARCH64_LDST16_ABS_LO12_NC: 721 case ELF::R_AARCH64_LDST8_ABS_LO12_NC: 722 case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 723 case ELF::R_AARCH64_TLSLE_ADD_TPREL_HI12: 724 case ELF::R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 725 case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0: 726 case ELF::R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: 727 case ELF::R_AARCH64_LD64_GOT_LO12_NC: 728 case ELF::R_AARCH64_TLSDESC_LD64_LO12: 729 case ELF::R_AARCH64_TLSDESC_ADD_LO12: 730 case ELF::R_AARCH64_MOVW_UABS_G0: 731 case ELF::R_AARCH64_MOVW_UABS_G0_NC: 732 case ELF::R_AARCH64_MOVW_UABS_G1: 733 case ELF::R_AARCH64_MOVW_UABS_G1_NC: 734 case ELF::R_AARCH64_MOVW_UABS_G2: 735 case ELF::R_AARCH64_MOVW_UABS_G2_NC: 736 case ELF::R_AARCH64_MOVW_UABS_G3: 737 return false; 738 case ELF::R_AARCH64_TLSDESC_CALL: 739 case ELF::R_AARCH64_CALL26: 740 case ELF::R_AARCH64_JUMP26: 741 case ELF::R_AARCH64_TSTBR14: 742 case ELF::R_AARCH64_CONDBR19: 743 case ELF::R_AARCH64_ADR_PREL_LO21: 744 case ELF::R_AARCH64_ADR_PREL_PG_HI21: 745 case ELF::R_AARCH64_ADR_PREL_PG_HI21_NC: 746 case ELF::R_AARCH64_ADR_GOT_PAGE: 747 case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 748 case ELF::R_AARCH64_TLSDESC_ADR_PREL21: 749 case ELF::R_AARCH64_TLSDESC_ADR_PAGE21: 750 case ELF::R_AARCH64_PREL16: 751 case ELF::R_AARCH64_PREL32: 752 case ELF::R_AARCH64_PREL64: 753 return true; 754 } 755 } 756 757 static bool isPCRelativeRISCV(uint64_t Type) { 758 switch (Type) { 759 default: 760 llvm_unreachable("Unknown relocation type"); 761 case ELF::R_RISCV_ADD32: 762 case ELF::R_RISCV_SUB32: 763 case ELF::R_RISCV_HI20: 764 case ELF::R_RISCV_LO12_I: 765 case ELF::R_RISCV_LO12_S: 766 case ELF::R_RISCV_64: 767 return false; 768 case ELF::R_RISCV_JAL: 769 case ELF::R_RISCV_CALL: 770 case ELF::R_RISCV_CALL_PLT: 771 case ELF::R_RISCV_BRANCH: 772 case ELF::R_RISCV_GOT_HI20: 773 case ELF::R_RISCV_PCREL_HI20: 774 case ELF::R_RISCV_PCREL_LO12_I: 775 case ELF::R_RISCV_PCREL_LO12_S: 776 case ELF::R_RISCV_RVC_JUMP: 777 case ELF::R_RISCV_RVC_BRANCH: 778 case ELF::R_RISCV_32_PCREL: 779 case ELF::R_RISCV_TLS_GOT_HI20: 780 return true; 781 } 782 } 783 784 bool Relocation::isSupported(uint64_t Type) { 785 switch (Arch) { 786 default: 787 return false; 788 case Triple::aarch64: 789 return isSupportedAArch64(Type); 790 case Triple::riscv64: 791 return isSupportedRISCV(Type); 792 case Triple::x86_64: 793 return isSupportedX86(Type); 794 } 795 } 796 797 size_t Relocation::getSizeForType(uint64_t Type) { 798 switch (Arch) { 799 default: 800 llvm_unreachable("Unsupported architecture"); 801 case Triple::aarch64: 802 return getSizeForTypeAArch64(Type); 803 case Triple::riscv64: 804 return getSizeForTypeRISCV(Type); 805 case Triple::x86_64: 806 return getSizeForTypeX86(Type); 807 } 808 } 809 810 bool Relocation::skipRelocationType(uint64_t Type) { 811 switch (Arch) { 812 default: 813 llvm_unreachable("Unsupported architecture"); 814 case Triple::aarch64: 815 return skipRelocationTypeAArch64(Type); 816 case Triple::riscv64: 817 return skipRelocationTypeRISCV(Type); 818 case Triple::x86_64: 819 return skipRelocationTypeX86(Type); 820 } 821 } 822 823 bool Relocation::skipRelocationProcess(uint64_t &Type, uint64_t Contents) { 824 switch (Arch) { 825 default: 826 llvm_unreachable("Unsupported architecture"); 827 case Triple::aarch64: 828 return skipRelocationProcessAArch64(Type, Contents); 829 case Triple::riscv64: 830 return skipRelocationProcessRISCV(Type, Contents); 831 case Triple::x86_64: 832 return skipRelocationProcessX86(Type, Contents); 833 } 834 } 835 836 uint64_t Relocation::encodeValue(uint64_t Type, uint64_t Value, uint64_t PC) { 837 switch (Arch) { 838 default: 839 llvm_unreachable("Unsupported architecture"); 840 case Triple::aarch64: 841 return encodeValueAArch64(Type, Value, PC); 842 case Triple::riscv64: 843 return encodeValueRISCV(Type, Value, PC); 844 case Triple::x86_64: 845 return encodeValueX86(Type, Value, PC); 846 } 847 } 848 849 uint64_t Relocation::extractValue(uint64_t Type, uint64_t Contents, 850 uint64_t PC) { 851 switch (Arch) { 852 default: 853 llvm_unreachable("Unsupported architecture"); 854 case Triple::aarch64: 855 return extractValueAArch64(Type, Contents, PC); 856 case Triple::riscv64: 857 return extractValueRISCV(Type, Contents, PC); 858 case Triple::x86_64: 859 return extractValueX86(Type, Contents, PC); 860 } 861 } 862 863 bool Relocation::isGOT(uint64_t Type) { 864 switch (Arch) { 865 default: 866 llvm_unreachable("Unsupported architecture"); 867 case Triple::aarch64: 868 return isGOTAArch64(Type); 869 case Triple::riscv64: 870 return isGOTRISCV(Type); 871 case Triple::x86_64: 872 return isGOTX86(Type); 873 } 874 } 875 876 bool Relocation::isX86GOTPCRELX(uint64_t Type) { 877 if (Arch != Triple::x86_64) 878 return false; 879 return Type == ELF::R_X86_64_GOTPCRELX || Type == ELF::R_X86_64_REX_GOTPCRELX; 880 } 881 882 bool Relocation::isX86GOTPC64(uint64_t Type) { 883 if (Arch != Triple::x86_64) 884 return false; 885 return Type == ELF::R_X86_64_GOTPC64; 886 } 887 888 bool Relocation::isNone(uint64_t Type) { return Type == getNone(); } 889 890 bool Relocation::isRelative(uint64_t Type) { 891 switch (Arch) { 892 default: 893 llvm_unreachable("Unsupported architecture"); 894 case Triple::aarch64: 895 return Type == ELF::R_AARCH64_RELATIVE; 896 case Triple::riscv64: 897 return Type == ELF::R_RISCV_RELATIVE; 898 case Triple::x86_64: 899 return Type == ELF::R_X86_64_RELATIVE; 900 } 901 } 902 903 bool Relocation::isIRelative(uint64_t Type) { 904 switch (Arch) { 905 default: 906 llvm_unreachable("Unsupported architecture"); 907 case Triple::aarch64: 908 return Type == ELF::R_AARCH64_IRELATIVE; 909 case Triple::riscv64: 910 llvm_unreachable("not implemented"); 911 case Triple::x86_64: 912 return Type == ELF::R_X86_64_IRELATIVE; 913 } 914 } 915 916 bool Relocation::isTLS(uint64_t Type) { 917 switch (Arch) { 918 default: 919 llvm_unreachable("Unsupported architecture"); 920 case Triple::aarch64: 921 return isTLSAArch64(Type); 922 case Triple::riscv64: 923 return isTLSRISCV(Type); 924 case Triple::x86_64: 925 return isTLSX86(Type); 926 } 927 } 928 929 bool Relocation::isInstructionReference(uint64_t Type) { 930 if (Arch != Triple::riscv64) 931 return false; 932 933 switch (Type) { 934 default: 935 return false; 936 case ELF::R_RISCV_PCREL_LO12_I: 937 case ELF::R_RISCV_PCREL_LO12_S: 938 return true; 939 } 940 } 941 942 uint64_t Relocation::getNone() { 943 switch (Arch) { 944 default: 945 llvm_unreachable("Unsupported architecture"); 946 case Triple::aarch64: 947 return ELF::R_AARCH64_NONE; 948 case Triple::riscv64: 949 return ELF::R_RISCV_NONE; 950 case Triple::x86_64: 951 return ELF::R_X86_64_NONE; 952 } 953 } 954 955 uint64_t Relocation::getPC32() { 956 switch (Arch) { 957 default: 958 llvm_unreachable("Unsupported architecture"); 959 case Triple::aarch64: 960 return ELF::R_AARCH64_PREL32; 961 case Triple::riscv64: 962 return ELF::R_RISCV_32_PCREL; 963 case Triple::x86_64: 964 return ELF::R_X86_64_PC32; 965 } 966 } 967 968 uint64_t Relocation::getPC64() { 969 switch (Arch) { 970 default: 971 llvm_unreachable("Unsupported architecture"); 972 case Triple::aarch64: 973 return ELF::R_AARCH64_PREL64; 974 case Triple::riscv64: 975 llvm_unreachable("not implemented"); 976 case Triple::x86_64: 977 return ELF::R_X86_64_PC64; 978 } 979 } 980 981 bool Relocation::isPCRelative(uint64_t Type) { 982 switch (Arch) { 983 default: 984 llvm_unreachable("Unsupported architecture"); 985 case Triple::aarch64: 986 return isPCRelativeAArch64(Type); 987 case Triple::riscv64: 988 return isPCRelativeRISCV(Type); 989 case Triple::x86_64: 990 return isPCRelativeX86(Type); 991 } 992 } 993 994 uint64_t Relocation::getAbs64() { 995 switch (Arch) { 996 default: 997 llvm_unreachable("Unsupported architecture"); 998 case Triple::aarch64: 999 return ELF::R_AARCH64_ABS64; 1000 case Triple::riscv64: 1001 return ELF::R_RISCV_64; 1002 case Triple::x86_64: 1003 return ELF::R_X86_64_64; 1004 } 1005 } 1006 1007 uint64_t Relocation::getRelative() { 1008 switch (Arch) { 1009 default: 1010 llvm_unreachable("Unsupported architecture"); 1011 case Triple::aarch64: 1012 return ELF::R_AARCH64_RELATIVE; 1013 case Triple::riscv64: 1014 llvm_unreachable("not implemented"); 1015 case Triple::x86_64: 1016 return ELF::R_X86_64_RELATIVE; 1017 } 1018 } 1019 1020 size_t Relocation::emit(MCStreamer *Streamer) const { 1021 const size_t Size = getSizeForType(Type); 1022 const auto *Value = createExpr(Streamer); 1023 Streamer->emitValue(Value, Size); 1024 return Size; 1025 } 1026 1027 const MCExpr *Relocation::createExpr(MCStreamer *Streamer) const { 1028 MCContext &Ctx = Streamer->getContext(); 1029 const MCExpr *Value = nullptr; 1030 1031 if (Symbol && Addend) { 1032 Value = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, Ctx), 1033 MCConstantExpr::create(Addend, Ctx), Ctx); 1034 } else if (Symbol) { 1035 Value = MCSymbolRefExpr::create(Symbol, Ctx); 1036 } else { 1037 Value = MCConstantExpr::create(Addend, Ctx); 1038 } 1039 1040 if (isPCRelative(Type)) { 1041 MCSymbol *TempLabel = Ctx.createNamedTempSymbol(); 1042 Streamer->emitLabel(TempLabel); 1043 Value = MCBinaryExpr::createSub( 1044 Value, MCSymbolRefExpr::create(TempLabel, Ctx), Ctx); 1045 } 1046 1047 return Value; 1048 } 1049 1050 const MCExpr *Relocation::createExpr(MCStreamer *Streamer, 1051 const MCExpr *RetainedValue) const { 1052 const auto *Value = createExpr(Streamer); 1053 1054 if (RetainedValue) { 1055 Value = MCBinaryExpr::create(getComposeOpcodeFor(Type), RetainedValue, 1056 Value, Streamer->getContext()); 1057 } 1058 1059 return Value; 1060 } 1061 1062 MCBinaryExpr::Opcode Relocation::getComposeOpcodeFor(uint64_t Type) { 1063 assert(Arch == Triple::riscv64 && "only implemented for RISC-V"); 1064 1065 switch (Type) { 1066 default: 1067 llvm_unreachable("not implemented"); 1068 case ELF::R_RISCV_ADD32: 1069 return MCBinaryExpr::Add; 1070 case ELF::R_RISCV_SUB32: 1071 return MCBinaryExpr::Sub; 1072 } 1073 } 1074 1075 void Relocation::print(raw_ostream &OS) const { 1076 switch (Arch) { 1077 default: 1078 OS << "RType:" << Twine::utohexstr(Type); 1079 break; 1080 1081 case Triple::aarch64: 1082 static const char *const AArch64RelocNames[] = { 1083 #define ELF_RELOC(name, value) #name, 1084 #include "llvm/BinaryFormat/ELFRelocs/AArch64.def" 1085 #undef ELF_RELOC 1086 }; 1087 assert(Type < ArrayRef(AArch64RelocNames).size()); 1088 OS << AArch64RelocNames[Type]; 1089 break; 1090 1091 case Triple::riscv64: 1092 // RISC-V relocations are not sequentially numbered so we cannot use an 1093 // array 1094 switch (Type) { 1095 default: 1096 llvm_unreachable("illegal RISC-V relocation"); 1097 #define ELF_RELOC(name, value) \ 1098 case value: \ 1099 OS << #name; \ 1100 break; 1101 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" 1102 #undef ELF_RELOC 1103 } 1104 break; 1105 1106 case Triple::x86_64: 1107 static const char *const X86RelocNames[] = { 1108 #define ELF_RELOC(name, value) #name, 1109 #include "llvm/BinaryFormat/ELFRelocs/x86_64.def" 1110 #undef ELF_RELOC 1111 }; 1112 assert(Type < ArrayRef(X86RelocNames).size()); 1113 OS << X86RelocNames[Type]; 1114 break; 1115 } 1116 OS << ", 0x" << Twine::utohexstr(Offset); 1117 if (Symbol) { 1118 OS << ", " << Symbol->getName(); 1119 } 1120 if (int64_t(Addend) < 0) 1121 OS << ", -0x" << Twine::utohexstr(-int64_t(Addend)); 1122 else 1123 OS << ", 0x" << Twine::utohexstr(Addend); 1124 OS << ", 0x" << Twine::utohexstr(Value); 1125 } 1126