1/********************************************************************** 2 Copyright(c) 2019 Arm Corporation All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions 6 are met: 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 * Redistributions in binary form must reproduce the above copyright 10 notice, this list of conditions and the following disclaimer in 11 the documentation and/or other materials provided with the 12 distribution. 13 * Neither the name of Arm Corporation nor the names of its 14 contributors may be used to endorse or promote products derived 15 from this software without specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28**********************************************************************/ 29 30#include "../include/aarch64_label.h" 31 32 .arch armv8-a+crc 33 .text 34 .align 2 35#include "lz0a_const_aarch64.h" 36#include "data_struct_aarch64.h" 37#include "huffman_aarch64.h" 38#include "bitbuf2_aarch64.h" 39#include "stdmac_aarch64.h" 40 41/* 42declare Macros 43*/ 44 45.macro declare_generic_reg name:req,reg:req,default:req 46 \name .req \default\reg 47 w_\name .req w\reg 48 x_\name .req x\reg 49.endm 50 51 .global cdecl(encode_deflate_icf_aarch64) 52#ifndef __APPLE__ 53 .type encode_deflate_icf_aarch64, %function 54#endif 55 56/* 57 struct deflate_icf *encode_deflate_icf_base(struct deflate_icf *next_in, 58 struct deflate_icf *end_in, struct BitBuf2 *bb, 59 struct hufftables_icf *hufftables) 60 61*/ 62 63 // parameters 64 declare_generic_reg next_in, 0,x 65 declare_generic_reg end_in, 1,x 66 declare_generic_reg bb, 2,x 67 declare_generic_reg hufftables, 3,x 68 69 // local variable 70 declare_generic_reg bb_out_end, 4,x 71 declare_generic_reg bb_bit_count, 5,w 72 declare_generic_reg dist_extra, 6,x 73 declare_generic_reg dist_lit_table, 7,x 74 declare_generic_reg code_and_extra, 8,x 75 declare_generic_reg bb_out_buf, 9,x 76 declare_generic_reg bb_bits, 10,x 77 declare_generic_reg d_length, 11,x 78 declare_generic_reg l_length, 12,x 79 declare_generic_reg d_extra_bit_count, 13,x 80 81 declare_generic_reg code_sum, 4,x 82 declare_generic_reg count_sum, 7,x 83 84 declare_generic_reg tmp0, 14,x 85 declare_generic_reg tmp1, 15,x 86 87// bit buffer offset 88.equ offset_m_bits, 0 89.equ offset_m_bit_count, 8 90.equ offset_m_out_buf, 16 91.equ offset_m_out_end, 24 92 93cdecl(encode_deflate_icf_aarch64): 94 cmp next_in, end_in 95 bcs .done 96 97 ldp bb_out_buf, bb_out_end, [bb, offset_m_out_buf] 98 cmp bb_out_end, bb_out_buf 99 bcc .done 100 101 ldr bb_bit_count, [bb, offset_m_bit_count] 102 ldr bb_bits, [bb, offset_m_bits] 103 b .loop_start 104 105 .align 3 106.loop: 107 ldr bb_out_end, [bb, offset_m_out_end] 108 cmp bb_out_end, bb_out_buf 109 bcc .done 110 111.loop_start: 112 ldrh w_code_and_extra, [next_in] 113 add next_in, next_in, 4 114 ldr w_dist_lit_table, [next_in, -4] 115 and code_and_extra, code_and_extra, 1023 116 117 ldrh w_dist_extra, [next_in, -2] 118 add code_and_extra, code_and_extra, 31 119 ubfx x_dist_lit_table, x_dist_lit_table, 10, 9 120 add x_tmp0, hufftables, code_and_extra, lsl 2 121 ubfx x_dist_extra, x_dist_extra, 3, 13 122 lsl x_dist_lit_table, x_dist_lit_table, 2 123 124 ldr w_code_and_extra, [hufftables, code_and_extra, lsl 2] 125 add x_d_extra_bit_count, hufftables, x_dist_lit_table 126 ldrb w_l_length, [x_tmp0, 3] 127 and code_and_extra, code_and_extra, 0xffffff 128 ldrh w_code_sum, [hufftables, x_dist_lit_table] 129 ldrb w_d_length, [x_d_extra_bit_count, 3] 130 add w_l_length, w_l_length, bb_bit_count 131 ldrb w_d_extra_bit_count, [x_d_extra_bit_count, 2] 132 133 lsl x_tmp0, code_and_extra, x_bb_bit_count 134 add bb_bit_count, w_d_length, w_l_length 135 lsl x_code_sum, x_code_sum, x_l_length 136 orr x_code_sum, x_code_sum, x_tmp0 137 add w_count_sum, w_d_extra_bit_count, bb_bit_count 138 lsl x_bb_bit_count, x_dist_extra, x_bb_bit_count 139 140 orr x_bb_bit_count, x_bb_bit_count, bb_bits 141 orr x_tmp0, x_code_sum, x_bb_bit_count // me->m_bits => x_tmp0 142 str x_tmp0, [bb, offset_m_bits] // me->m_bits => x_tmp0 143 str w_count_sum, [bb, offset_m_bit_count] 144 145 str x_tmp0, [bb_out_buf] // me->m_bits => x_tmp0 146 ldr bb_bit_count, [bb, offset_m_bit_count] 147 ldr bb_bits, [bb, offset_m_bits] 148 and w_tmp0, bb_bit_count, -8 // bits => w_tmp0 149 ldr bb_out_buf, [bb, offset_m_out_buf] 150 lsr w_tmp1, bb_bit_count, 3 // bits/8 => w_tmp1 151 lsr bb_bits, bb_bits, x_tmp0 // bits => x_tmp0 152 sub bb_bit_count, bb_bit_count, w_tmp0 // bits => w_tmp0 153 add bb_out_buf, bb_out_buf, x_tmp1 // bits/8 => x_tmp1 154 str bb_bits, [bb,offset_m_bits] 155 str bb_bit_count, [bb, offset_m_bit_count] 156 str bb_out_buf, [bb, offset_m_out_buf] 157 158 cmp end_in, next_in 159 bhi .loop 160 161.done: 162 ret 163#ifndef __APPLE__ 164 .size encode_deflate_icf_aarch64, .-encode_deflate_icf_aarch64 165#endif 166