1 typedef struct Conf Conf; 2 typedef struct FPU FPU; 3 typedef struct FPenv FPenv; 4 typedef ulong Instr; 5 typedef struct ISAConf ISAConf; 6 typedef struct Label Label; 7 typedef struct Lock Lock; 8 typedef struct MMU MMU; 9 typedef struct Mach Mach; 10 typedef struct Notsave Notsave; 11 typedef struct PCArch PCArch; 12 typedef struct Pcidev Pcidev; 13 typedef struct PCMmap PCMmap; 14 typedef struct PCMslot PCMslot; 15 typedef struct Page Page; 16 typedef struct PMMU PMMU; 17 typedef struct Segdesc Segdesc; 18 typedef struct Ureg Ureg; 19 typedef struct Vctl Vctl; 20 21 #pragma incomplete Ureg 22 #pragma incomplete Vctl 23 24 25 struct Lock 26 { 27 ulong key; 28 ulong sr; 29 ulong pc; 30 ulong pri; 31 }; 32 33 struct Label 34 { 35 ulong sp; 36 ulong pc; 37 }; 38 39 /* 40 * FPenv.status 41 */ 42 enum 43 { 44 FPINIT, 45 FPACTIVE, 46 FPINACTIVE, 47 }; 48 49 /* 50 * This structure must agree with FPsave and FPrestore asm routines 51 */ 52 struct FPenv 53 { 54 ushort control; 55 ushort r1; 56 ushort status; 57 ushort r2; 58 ushort tag; 59 ushort r3; 60 ulong pc; 61 ushort selector; 62 ushort r4; 63 ulong operand; 64 ushort oselector; 65 ushort r5; 66 }; 67 68 /* 69 * This structure must agree with fpsave and fprestore asm routines 70 */ 71 struct FPU 72 { 73 FPenv env; 74 uchar regs[80]; /* floating point registers */ 75 }; 76 77 struct Conf 78 { 79 ulong nmach; /* processors */ 80 ulong nproc; /* processes */ 81 ulong monitor; /* has monitor? */ 82 ulong npage0; /* total physical pages of memory */ 83 ulong npage1; /* total physical pages of memory */ 84 ulong npage; /* total physical pages of memory */ 85 ulong base0; /* base of bank 0 */ 86 ulong base1; /* base of bank 1 */ 87 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 88 ulong ialloc; /* max interrupt time allocation in bytes */ 89 ulong pipeqsize; /* size in bytes of pipe queues */ 90 int nuart; /* number of uart devices */ 91 }; 92 93 #include "../port/portdat.h" 94 95 typedef struct { 96 ulong link; /* link (old TSS selector) */ 97 ulong esp0; /* privilege level 0 stack pointer */ 98 ulong ss0; /* privilege level 0 stack selector */ 99 ulong esp1; /* privilege level 1 stack pointer */ 100 ulong ss1; /* privilege level 1 stack selector */ 101 ulong esp2; /* privilege level 2 stack pointer */ 102 ulong ss2; /* privilege level 2 stack selector */ 103 ulong cr3; /* page directory base register */ 104 ulong eip; /* instruction pointer */ 105 ulong eflags; /* flags register */ 106 ulong eax; /* general registers */ 107 ulong ecx; 108 ulong edx; 109 ulong ebx; 110 ulong esp; 111 ulong ebp; 112 ulong esi; 113 ulong edi; 114 ulong es; /* segment selectors */ 115 ulong cs; 116 ulong ss; 117 ulong ds; 118 ulong fs; 119 ulong gs; 120 ulong ldt; /* selector for task's LDT */ 121 ulong iomap; /* I/O map base address + T-bit */ 122 } Tss; 123 124 struct Segdesc 125 { 126 ulong d0; 127 ulong d1; 128 }; 129 130 struct Mach 131 { 132 int machno; /* physical id of processor (KNOWN TO ASSEMBLY) */ 133 ulong splpc; /* pc of last caller to splhi */ 134 135 ulong* pdb; /* page directory base for this processor (va) */ 136 Tss* tss; /* tss for this processor */ 137 Segdesc *gdt; /* gdt for this processor */ 138 139 Proc* externup; /* extern register Proc *up */ 140 141 ulong ticks; /* of the clock since boot time */ 142 Proc* proc; /* current process on this processor */ 143 Label sched; /* scheduler wakeup */ 144 Lock alarmlock; /* access to alarm list */ 145 void* alarm; /* alarms bound to this clock */ 146 int inclockintr; 147 148 int nrdy; 149 int ilockdepth; 150 151 int loopconst; 152 153 Lock apictimerlock; 154 int cpumhz; 155 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 156 uvlong cpuhz; 157 int cpuidax; 158 int cpuiddx; 159 char cpuidid[16]; 160 char* cpuidtype; 161 int havetsc; 162 int havepge; 163 uvlong tscticks; 164 uvlong tscoff; 165 int intr; 166 ulong spuriousintr; 167 int lastintr; 168 169 vlong mtrrcap; 170 vlong mtrrdef; 171 vlong mtrrfix[11]; 172 vlong mtrrvar[32]; /* 256 max. */ 173 174 int stack[1]; 175 }; 176 177 struct 178 { 179 Lock; 180 int machs; /* bitmap of active CPUs */ 181 int exiting; /* shutdown */ 182 int ispanic; /* shutdown in response to a panic */ 183 int thunderbirdsarego; /* lets the added processors continue to schedinit */ 184 }active; 185 186 187 /* 188 * routines for things outside the PC model, like power management 189 */ 190 struct PCArch 191 { 192 char* id; 193 int (*ident)(void); /* this should be in the model */ 194 void (*reset)(void); /* this should be in the model */ 195 int (*serialpower)(int); /* 1 == on, 0 == off */ 196 int (*modempower)(int); /* 1 == on, 0 == off */ 197 198 void (*intrinit)(void); 199 int (*intrenable)(Vctl*); 200 int (*intrvecno)(int); 201 int (*intrdisable)(int); 202 203 void (*clockenable)(void); 204 uvlong (*fastclock)(uvlong*); 205 void (*timerset)(uvlong); 206 }; 207 208 /* 209 * a parsed plan9.ini line 210 */ 211 #define NISAOPT 8 212 213 struct ISAConf { 214 char *type; 215 ulong port; 216 int irq; 217 ulong dma; 218 ulong mem; 219 ulong size; 220 ulong freq; 221 222 int nopt; 223 char *opt[NISAOPT]; 224 }; 225 226 extern PCArch *arch; /* PC architecture */ 227 228 /* 229 * Each processor sees its own Mach structure at address MACHADDR. 230 * However, the Mach structures must also be available via the per-processor 231 * MMU information array machp, mainly for disambiguation and access to 232 * the clock which is only maintained by the bootstrap processor (0). 233 */ 234 Mach* machp[MAXMACH]; 235 236 #define MACHP(n) (machp[n]) 237 238 extern Mach *m; 239 //extern Proc *up; 240 #define up (((Mach*)MACHADDR)->externup) 241 242 extern int swcursor; 243 244 /* 245 * hardware info about a device 246 */ 247 typedef struct { 248 ulong port; 249 int size; 250 } Devport; 251 252 struct DevConf 253 { 254 ulong intnum; /* interrupt number */ 255 char *type; /* card type, malloced */ 256 int nports; /* Number of ports */ 257 Devport *ports; /* The ports themselves */ 258 }; 259