1 /* 2 * Memory and machine-specific definitions. Used in C and assembler. 3 */ 4 5 /* 6 * Sizes 7 */ 8 #define BI2BY 8 /* bits per byte */ 9 #define BI2WD 32 /* bits per word */ 10 #define BY2WD 4 /* bytes per word */ 11 #define BY2PG 4096 /* bytes per page */ 12 #define WD2PG (BY2PG/BY2WD) /* words per page */ 13 #define PGSHIFT 12 /* log(BY2PG) */ 14 #define PGROUND(s) (((s)+(BY2PG-1))&~(BY2PG-1)) 15 16 #define MAXMACH 1 /* max # cpus system can run */ 17 #define CACHELINELOG 4 18 #define CACHELINESZ (1<<CACHELINELOG) 19 20 /* 21 * Time 22 */ 23 #define HZ (50) /* clock frequency */ 24 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 25 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 26 #define TK2MS(t) ((((ulong)(t))*1000)/HZ) /* ticks to milliseconds */ 27 #define MS2TK(t) ((((ulong)(t))*HZ)/1000) /* milliseconds to ticks */ 28 #define MHz 1000000 29 30 /* 31 * Fundamental values 32 */ 33 34 #define KZERO 0 /* bootstrap runs in real mode */ 35 #define MACHSIZE 4096 36 37 /* 38 * physical MMU 39 */ 40 #define KSEG0 0x20000000 41 #define KSEGM 0xE0000000 /* mask to check which seg */ 42 43 /* 44 * MSR bits 45 */ 46 47 #define POW 0x40000 /* enable power mgmt */ 48 #define TGPR 0x20000 /* GPR0-3 remapped; 603/603e specific */ 49 #define ILE 0x10000 /* interrupts little endian */ 50 #define EE 0x08000 /* enable external/decrementer interrupts */ 51 #define PR 0x04000 /* =1, user mode */ 52 #define FPE 0x02000 /* enable floating point */ 53 #define ME 0x01000 /* enable machine check exceptions */ 54 #define FE0 0x00800 55 #define SE 0x00400 /* single-step trace */ 56 #define BE 0x00200 /* branch trace */ 57 #define FE1 0x00100 58 #define IP 0x00040 /* =0, vector to nnnnn; =1, vector to FFFnnnnn */ 59 #define IR 0x00020 /* enable instruction address translation */ 60 #define DR 0x00010 /* enable data address translation */ 61 #define RI 0x00002 /* exception is recoverable */ 62 #define LE 0x00001 /* little endian mode */ 63 64 #define KMSR (ME|FE0|FE1|FPE) 65 #define UMSR (KMSR|PR|EE|IR|DR) 66 67 /* 68 * MPC82x addresses; mpc8bug is happy with these 69 */ 70 #define BCSRMEM 0x02100000 71 #define INTMEM 0x02200000 72 #define FLASHMEM 0x02800000 73 #define SDRAMMEM 0x03000000 74 75 #define DPRAM (INTMEM+0x2000) 76 #define DPLEN1 0x400 77 #define DPLEN2 0x200 78 #define DPLEN3 0x100 79 #define DPBASE (DPRAM+DPLEN1) 80 81 #define SCC1P (INTMEM+0x3C00) 82 #define I2CP (INTMEM+0x3C80) 83 #define MISCP (INTMEM+0x3CB0) 84 #define IDMA1P (INTMEM+0x3CC0) 85 #define SCC2P (INTMEM+0x3D00) 86 #define SCC3P (INTMEM+0x3E00) 87 #define SCC4P (INTMEM+0x3F00) 88 #define SPIP (INTMEM+0x3D80) 89 #define TIMERP (INTMEM+0x3DB0) 90 #define SMC1P (INTMEM+0x3E80) 91 #define DSP1P (INTMEM+0x3EC0) 92 #define SMC2P (INTMEM+0x3F80) 93 #define DSP2P (INTMEM+0x3FC0) 94 95 #define KEEP_ALIVE_KEY 0x55ccaa33 /* clock and rtc register key */ 96