1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_rss.h" 28 #include "opt_ratelimit.h" 29 #include "opt_ipsec.h" 30 31 #include <linux/kmod.h> 32 #include <linux/module.h> 33 #include <linux/errno.h> 34 #include <linux/pci.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/slab.h> 37 #include <linux/io-mapping.h> 38 #include <linux/interrupt.h> 39 #include <linux/hardirq.h> 40 #include <dev/mlx5/driver.h> 41 #include <dev/mlx5/cq.h> 42 #include <dev/mlx5/qp.h> 43 #include <dev/mlx5/srq.h> 44 #include <dev/mlx5/mpfs.h> 45 #include <dev/mlx5/vport.h> 46 #include <linux/delay.h> 47 #include <dev/mlx5/mlx5_ifc.h> 48 #include <dev/mlx5/mlx5_fpga/core.h> 49 #include <dev/mlx5/mlx5_lib/mlx5.h> 50 #include <dev/mlx5/mlx5_core/mlx5_core.h> 51 #include <dev/mlx5/mlx5_core/eswitch.h> 52 #include <dev/mlx5/mlx5_core/fs_core.h> 53 #include <dev/mlx5/mlx5_core/diag_cnt.h> 54 #ifdef PCI_IOV 55 #include <sys/nv.h> 56 #include <sys/socket.h> 57 #include <dev/pci/pci_iov.h> 58 #include <sys/iov_schema.h> 59 #include <sys/iov.h> 60 #include <net/if.h> 61 #include <net/if_vlan_var.h> 62 #endif 63 64 static const char mlx5_version[] = "Mellanox Core driver " 65 DRIVER_VERSION " (" DRIVER_RELDATE ")"; 66 MODULE_DESCRIPTION("Mellanox ConnectX-4 and onwards core driver"); 67 MODULE_LICENSE("Dual BSD/GPL"); 68 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 69 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1); 70 MODULE_DEPEND(mlx5, firmware, 1, 1, 1); 71 #ifdef IPSEC_OFFLOAD 72 MODULE_DEPEND(mlx5, ipsec, 1, 1, 1); 73 #endif 74 MODULE_VERSION(mlx5, 1); 75 76 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 77 "mlx5 hardware controls"); 78 79 int mlx5_core_debug_mask; 80 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN, 81 &mlx5_core_debug_mask, 0, 82 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 83 84 #define MLX5_DEFAULT_PROF 2 85 static int mlx5_prof_sel = MLX5_DEFAULT_PROF; 86 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN, 87 &mlx5_prof_sel, 0, 88 "profile selector. Valid range 0 - 2"); 89 90 static int mlx5_fast_unload_enabled = 1; 91 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN, 92 &mlx5_fast_unload_enabled, 0, 93 "Set to enable fast unload. Clear to disable."); 94 95 static int mlx5_core_comp_eq_size = 1024; 96 SYSCTL_INT(_hw_mlx5, OID_AUTO, comp_eq_size, CTLFLAG_RDTUN | CTLFLAG_MPSAFE, 97 &mlx5_core_comp_eq_size, 0, 98 "Set default completion EQ size between 1024 and 16384 inclusivly. Value should be power of two."); 99 100 static LIST_HEAD(intf_list); 101 static LIST_HEAD(dev_list); 102 static DEFINE_MUTEX(intf_mutex); 103 104 struct mlx5_device_context { 105 struct list_head list; 106 struct mlx5_interface *intf; 107 void *context; 108 }; 109 110 enum { 111 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 112 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 113 }; 114 115 static struct mlx5_profile profiles[] = { 116 [0] = { 117 .mask = 0, 118 }, 119 [1] = { 120 .mask = MLX5_PROF_MASK_QP_SIZE, 121 .log_max_qp = 12, 122 }, 123 [2] = { 124 .mask = MLX5_PROF_MASK_QP_SIZE | 125 MLX5_PROF_MASK_MR_CACHE, 126 .log_max_qp = 17, 127 .mr_cache[0] = { 128 .size = 500, 129 .limit = 250 130 }, 131 .mr_cache[1] = { 132 .size = 500, 133 .limit = 250 134 }, 135 .mr_cache[2] = { 136 .size = 500, 137 .limit = 250 138 }, 139 .mr_cache[3] = { 140 .size = 500, 141 .limit = 250 142 }, 143 .mr_cache[4] = { 144 .size = 500, 145 .limit = 250 146 }, 147 .mr_cache[5] = { 148 .size = 500, 149 .limit = 250 150 }, 151 .mr_cache[6] = { 152 .size = 500, 153 .limit = 250 154 }, 155 .mr_cache[7] = { 156 .size = 500, 157 .limit = 250 158 }, 159 .mr_cache[8] = { 160 .size = 500, 161 .limit = 250 162 }, 163 .mr_cache[9] = { 164 .size = 500, 165 .limit = 250 166 }, 167 .mr_cache[10] = { 168 .size = 500, 169 .limit = 250 170 }, 171 .mr_cache[11] = { 172 .size = 500, 173 .limit = 250 174 }, 175 .mr_cache[12] = { 176 .size = 64, 177 .limit = 32 178 }, 179 .mr_cache[13] = { 180 .size = 32, 181 .limit = 16 182 }, 183 .mr_cache[14] = { 184 .size = 16, 185 .limit = 8 186 }, 187 }, 188 [3] = { 189 .mask = MLX5_PROF_MASK_QP_SIZE, 190 .log_max_qp = 17, 191 }, 192 }; 193 194 static int 195 mlx5_core_get_comp_eq_size(void) 196 { 197 int value = mlx5_core_comp_eq_size; 198 199 if (value < 1024) 200 value = 1024; 201 else if (value > 16384) 202 value = 16384; 203 204 /* make value power of two, rounded down */ 205 while (value & (value - 1)) 206 value &= (value - 1); 207 return (value); 208 } 209 210 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 211 { 212 const size_t driver_ver_sz = 213 MLX5_FLD_SZ_BYTES(set_driver_version_in, driver_version); 214 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 215 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {}; 216 char *string; 217 218 if (!MLX5_CAP_GEN(dev, driver_version)) 219 return; 220 221 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 222 223 snprintf(string, driver_ver_sz, "FreeBSD,mlx5_core,%u.%u.%u," DRIVER_VERSION, 224 __FreeBSD_version / 100000, (__FreeBSD_version / 1000) % 100, 225 __FreeBSD_version % 1000); 226 227 /* Send the command */ 228 MLX5_SET(set_driver_version_in, in, opcode, 229 MLX5_CMD_OP_SET_DRIVER_VERSION); 230 231 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 232 } 233 234 #ifdef PCI_IOV 235 static const char iov_mac_addr_name[] = "mac-addr"; 236 static const char iov_vlan_name[] = "vlan"; 237 static const char iov_node_guid_name[] = "node-guid"; 238 static const char iov_port_guid_name[] = "port-guid"; 239 #endif 240 241 static int set_dma_caps(struct pci_dev *pdev) 242 { 243 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 244 int err; 245 246 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 247 if (err) { 248 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n"); 249 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 250 if (err) { 251 mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n"); 252 return err; 253 } 254 } 255 256 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 257 if (err) { 258 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n"); 259 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 260 if (err) { 261 mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n"); 262 return err; 263 } 264 } 265 266 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 267 return err; 268 } 269 270 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev, 271 u16 *p_power, u8 *p_status) 272 { 273 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; 274 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; 275 int err; 276 277 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 278 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0); 279 280 *p_status = MLX5_GET(mpein_reg, out, pwr_status); 281 *p_power = MLX5_GET(mpein_reg, out, pci_power); 282 return err; 283 } 284 285 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 286 { 287 struct pci_dev *pdev = dev->pdev; 288 int err = 0; 289 290 mutex_lock(&dev->pci_status_mutex); 291 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 292 err = pci_enable_device(pdev); 293 if (!err) 294 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 295 } 296 mutex_unlock(&dev->pci_status_mutex); 297 298 return err; 299 } 300 301 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 302 { 303 struct pci_dev *pdev = dev->pdev; 304 305 mutex_lock(&dev->pci_status_mutex); 306 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 307 pci_disable_device(pdev); 308 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 309 } 310 mutex_unlock(&dev->pci_status_mutex); 311 } 312 313 static int request_bar(struct pci_dev *pdev) 314 { 315 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 316 int err = 0; 317 318 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 319 mlx5_core_err(dev, "Missing registers BAR, aborting\n"); 320 return -ENODEV; 321 } 322 323 err = pci_request_regions(pdev, DRIVER_NAME); 324 if (err) 325 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n"); 326 327 return err; 328 } 329 330 static void release_bar(struct pci_dev *pdev) 331 { 332 pci_release_regions(pdev); 333 } 334 335 static int mlx5_enable_msix(struct mlx5_core_dev *dev) 336 { 337 struct mlx5_priv *priv = &dev->priv; 338 struct mlx5_eq_table *table = &priv->eq_table; 339 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 340 int limit = dev->msix_eqvec; 341 int nvec = MLX5_EQ_VEC_COMP_BASE; 342 int i; 343 344 if (limit > 0) 345 nvec += limit; 346 else 347 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 348 349 if (nvec > num_eqs) 350 nvec = num_eqs; 351 if (nvec > 256) 352 nvec = 256; /* limit of firmware API */ 353 if (nvec <= MLX5_EQ_VEC_COMP_BASE) 354 return -ENOMEM; 355 356 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 357 358 for (i = 0; i < nvec; i++) 359 priv->msix_arr[i].entry = i; 360 361 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 362 MLX5_EQ_VEC_COMP_BASE + 1, nvec); 363 if (nvec < 0) 364 return nvec; 365 366 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 367 return 0; 368 } 369 370 static void mlx5_disable_msix(struct mlx5_core_dev *dev) 371 { 372 struct mlx5_priv *priv = &dev->priv; 373 374 pci_disable_msix(dev->pdev); 375 kfree(priv->msix_arr); 376 } 377 378 struct mlx5_reg_host_endianess { 379 u8 he; 380 u8 rsvd[15]; 381 }; 382 383 384 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 385 386 enum { 387 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 388 MLX5_DEV_CAP_FLAG_DCT | 389 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 390 }; 391 392 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 393 { 394 switch (size) { 395 case 128: 396 return 0; 397 case 256: 398 return 1; 399 case 512: 400 return 2; 401 case 1024: 402 return 3; 403 case 2048: 404 return 4; 405 case 4096: 406 return 5; 407 default: 408 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 409 return 0; 410 } 411 } 412 413 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 414 enum mlx5_cap_type cap_type, 415 enum mlx5_cap_mode cap_mode) 416 { 417 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 418 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 419 void *out, *hca_caps; 420 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 421 int err; 422 423 memset(in, 0, sizeof(in)); 424 out = kzalloc(out_sz, GFP_KERNEL); 425 426 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 427 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 428 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 429 if (err) { 430 mlx5_core_warn(dev, 431 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 432 cap_type, cap_mode, err); 433 goto query_ex; 434 } 435 436 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 437 438 switch (cap_mode) { 439 case HCA_CAP_OPMOD_GET_MAX: 440 memcpy(dev->hca_caps_max[cap_type], hca_caps, 441 MLX5_UN_SZ_BYTES(hca_cap_union)); 442 break; 443 case HCA_CAP_OPMOD_GET_CUR: 444 memcpy(dev->hca_caps_cur[cap_type], hca_caps, 445 MLX5_UN_SZ_BYTES(hca_cap_union)); 446 break; 447 default: 448 mlx5_core_warn(dev, 449 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 450 cap_type, cap_mode); 451 err = -EINVAL; 452 break; 453 } 454 query_ex: 455 kfree(out); 456 return err; 457 } 458 459 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 460 { 461 int ret; 462 463 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 464 if (ret) 465 return ret; 466 467 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 468 } 469 470 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 471 { 472 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 473 474 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 475 476 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 477 } 478 479 static int handle_hca_cap(struct mlx5_core_dev *dev) 480 { 481 void *set_ctx = NULL; 482 struct mlx5_profile *prof = dev->profile; 483 int err = -ENOMEM; 484 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 485 void *set_hca_cap; 486 487 set_ctx = kzalloc(set_sz, GFP_KERNEL); 488 489 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 490 if (err) 491 goto query_ex; 492 493 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 494 capability); 495 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 496 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 497 498 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 499 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 500 128); 501 /* we limit the size of the pkey table to 128 entries for now */ 502 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 503 to_fw_pkey_sz(dev, 128)); 504 505 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 506 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 507 prof->log_max_qp); 508 509 /* disable cmdif checksum */ 510 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 511 512 /* Enable 4K UAR only when HCA supports it and page size is bigger 513 * than 4K. 514 */ 515 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 516 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 517 518 /* enable drain sigerr */ 519 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 520 521 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 522 523 err = set_caps(dev, set_ctx, set_sz); 524 525 query_ex: 526 kfree(set_ctx); 527 return err; 528 } 529 530 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 531 { 532 void *set_ctx; 533 void *set_hca_cap; 534 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 535 int req_endianness; 536 int err; 537 538 if (MLX5_CAP_GEN(dev, atomic)) { 539 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 540 if (err) 541 return err; 542 } else { 543 return 0; 544 } 545 546 req_endianness = 547 MLX5_CAP_ATOMIC(dev, 548 supported_atomic_req_8B_endianess_mode_1); 549 550 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 551 return 0; 552 553 set_ctx = kzalloc(set_sz, GFP_KERNEL); 554 if (!set_ctx) 555 return -ENOMEM; 556 557 MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 558 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 559 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 560 561 /* Set requestor to host endianness */ 562 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 563 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 564 565 err = set_caps(dev, set_ctx, set_sz); 566 567 kfree(set_ctx); 568 return err; 569 } 570 571 static int handle_hca_cap_2(struct mlx5_core_dev *dev) 572 { 573 int err; 574 575 if (MLX5_CAP_GEN_MAX(dev, hca_cap_2)) { 576 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); 577 if (err) 578 return err; 579 } 580 581 return 0; 582 } 583 584 static int set_hca_ctrl(struct mlx5_core_dev *dev) 585 { 586 struct mlx5_reg_host_endianess he_in; 587 struct mlx5_reg_host_endianess he_out; 588 int err; 589 590 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 591 !MLX5_CAP_GEN(dev, roce)) 592 return 0; 593 594 memset(&he_in, 0, sizeof(he_in)); 595 he_in.he = MLX5_SET_HOST_ENDIANNESS; 596 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 597 &he_out, sizeof(he_out), 598 MLX5_REG_HOST_ENDIANNESS, 0, 1); 599 return err; 600 } 601 602 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 603 { 604 int ret = 0; 605 606 /* Disable local_lb by default */ 607 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 608 ret = mlx5_nic_vport_update_local_lb(dev, false); 609 610 return ret; 611 } 612 613 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 614 { 615 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 616 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 617 618 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 619 MLX5_SET(enable_hca_in, in, function_id, func_id); 620 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 621 } 622 623 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 624 { 625 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 626 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 627 628 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 629 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 630 } 631 632 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 633 { 634 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 635 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 636 u32 sup_issi; 637 int err; 638 639 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 640 641 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 642 if (err) { 643 u32 syndrome; 644 u8 status; 645 646 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 647 if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 648 mlx5_core_dbg(dev, "Only ISSI 0 is supported\n"); 649 return 0; 650 } 651 652 mlx5_core_err(dev, "failed to query ISSI\n"); 653 return err; 654 } 655 656 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 657 658 if (sup_issi & (1 << 1)) { 659 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 660 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 661 662 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 663 MLX5_SET(set_issi_in, set_in, current_issi, 1); 664 665 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 666 if (err) { 667 mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err); 668 return err; 669 } 670 671 dev->issi = 1; 672 673 return 0; 674 } else if (sup_issi & (1 << 0)) { 675 return 0; 676 } 677 678 return -ENOTSUPP; 679 } 680 681 682 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 683 { 684 struct mlx5_eq_table *table = &dev->priv.eq_table; 685 struct mlx5_eq *eq; 686 int err = -ENOENT; 687 688 spin_lock(&table->lock); 689 list_for_each_entry(eq, &table->comp_eqs_list, list) { 690 if (eq->index == vector) { 691 *eqn = eq->eqn; 692 *irqn = eq->irqn; 693 err = 0; 694 break; 695 } 696 } 697 spin_unlock(&table->lock); 698 699 return err; 700 } 701 EXPORT_SYMBOL(mlx5_vector2eqn); 702 703 static void free_comp_eqs(struct mlx5_core_dev *dev) 704 { 705 struct mlx5_eq_table *table = &dev->priv.eq_table; 706 struct mlx5_eq *eq, *n; 707 708 spin_lock(&table->lock); 709 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 710 list_del(&eq->list); 711 spin_unlock(&table->lock); 712 if (mlx5_destroy_unmap_eq(dev, eq)) 713 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 714 eq->eqn); 715 kfree(eq); 716 spin_lock(&table->lock); 717 } 718 spin_unlock(&table->lock); 719 } 720 721 static int alloc_comp_eqs(struct mlx5_core_dev *dev) 722 { 723 struct mlx5_eq_table *table = &dev->priv.eq_table; 724 struct mlx5_eq *eq; 725 int ncomp_vec; 726 int nent; 727 int err; 728 int i; 729 730 INIT_LIST_HEAD(&table->comp_eqs_list); 731 ncomp_vec = table->num_comp_vectors; 732 nent = mlx5_core_get_comp_eq_size(); 733 for (i = 0; i < ncomp_vec; i++) { 734 eq = kzalloc_node(sizeof(*eq), GFP_KERNEL, dev->priv.numa_node); 735 736 err = mlx5_create_map_eq(dev, eq, 737 i + MLX5_EQ_VEC_COMP_BASE, nent, 0); 738 if (err) { 739 kfree(eq); 740 goto clean; 741 } 742 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 743 eq->index = i; 744 spin_lock(&table->lock); 745 list_add_tail(&eq->list, &table->comp_eqs_list); 746 spin_unlock(&table->lock); 747 } 748 749 return 0; 750 751 clean: 752 free_comp_eqs(dev); 753 return err; 754 } 755 756 static inline int fw_initializing(struct mlx5_core_dev *dev) 757 { 758 return ioread32be(&dev->iseg->initializing) >> 31; 759 } 760 761 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 762 u32 warn_time_mili) 763 { 764 int warn = jiffies + msecs_to_jiffies(warn_time_mili); 765 int end = jiffies + msecs_to_jiffies(max_wait_mili); 766 int err = 0; 767 768 MPASS(max_wait_mili > warn_time_mili); 769 770 while (fw_initializing(dev) == 1) { 771 if (time_after(jiffies, end)) { 772 err = -EBUSY; 773 break; 774 } 775 if (warn_time_mili && time_after(jiffies, warn)) { 776 mlx5_core_warn(dev, 777 "Waiting for FW initialization, timeout abort in %u s\n", 778 (unsigned)(jiffies_to_msecs(end - warn) / 1000)); 779 warn = jiffies + msecs_to_jiffies(warn_time_mili); 780 } 781 msleep(FW_INIT_WAIT_MS); 782 } 783 784 if (err != 0) 785 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n", 786 ioread32be(&dev->iseg->initializing)); 787 788 return err; 789 } 790 791 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 792 { 793 struct mlx5_device_context *dev_ctx; 794 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 795 796 dev_ctx = kzalloc_node(sizeof(*dev_ctx), GFP_KERNEL, priv->numa_node); 797 if (!dev_ctx) 798 return; 799 800 dev_ctx->intf = intf; 801 CURVNET_SET_QUIET(vnet0); 802 dev_ctx->context = intf->add(dev); 803 CURVNET_RESTORE(); 804 805 if (dev_ctx->context) { 806 spin_lock_irq(&priv->ctx_lock); 807 list_add_tail(&dev_ctx->list, &priv->ctx_list); 808 spin_unlock_irq(&priv->ctx_lock); 809 } else { 810 kfree(dev_ctx); 811 } 812 } 813 814 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 815 { 816 struct mlx5_device_context *dev_ctx; 817 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 818 819 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 820 if (dev_ctx->intf == intf) { 821 spin_lock_irq(&priv->ctx_lock); 822 list_del(&dev_ctx->list); 823 spin_unlock_irq(&priv->ctx_lock); 824 825 intf->remove(dev, dev_ctx->context); 826 kfree(dev_ctx); 827 return; 828 } 829 } 830 831 int 832 mlx5_register_device(struct mlx5_core_dev *dev) 833 { 834 struct mlx5_priv *priv = &dev->priv; 835 struct mlx5_interface *intf; 836 837 mutex_lock(&intf_mutex); 838 list_add_tail(&priv->dev_list, &dev_list); 839 list_for_each_entry(intf, &intf_list, list) 840 mlx5_add_device(intf, priv); 841 mutex_unlock(&intf_mutex); 842 843 return 0; 844 } 845 846 void 847 mlx5_unregister_device(struct mlx5_core_dev *dev) 848 { 849 struct mlx5_priv *priv = &dev->priv; 850 struct mlx5_interface *intf; 851 852 mutex_lock(&intf_mutex); 853 list_for_each_entry(intf, &intf_list, list) 854 mlx5_remove_device(intf, priv); 855 list_del(&priv->dev_list); 856 mutex_unlock(&intf_mutex); 857 } 858 859 int mlx5_register_interface(struct mlx5_interface *intf) 860 { 861 struct mlx5_priv *priv; 862 863 if (!intf->add || !intf->remove) 864 return -EINVAL; 865 866 mutex_lock(&intf_mutex); 867 list_add_tail(&intf->list, &intf_list); 868 list_for_each_entry(priv, &dev_list, dev_list) 869 mlx5_add_device(intf, priv); 870 mutex_unlock(&intf_mutex); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(mlx5_register_interface); 875 876 void mlx5_unregister_interface(struct mlx5_interface *intf) 877 { 878 struct mlx5_priv *priv; 879 880 mutex_lock(&intf_mutex); 881 list_for_each_entry(priv, &dev_list, dev_list) 882 mlx5_remove_device(intf, priv); 883 list_del(&intf->list); 884 mutex_unlock(&intf_mutex); 885 } 886 EXPORT_SYMBOL(mlx5_unregister_interface); 887 888 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 889 { 890 struct mlx5_priv *priv = &mdev->priv; 891 struct mlx5_device_context *dev_ctx; 892 unsigned long flags; 893 void *result = NULL; 894 895 spin_lock_irqsave(&priv->ctx_lock, flags); 896 897 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 898 if ((dev_ctx->intf->protocol == protocol) && 899 dev_ctx->intf->get_dev) { 900 result = dev_ctx->intf->get_dev(dev_ctx->context); 901 break; 902 } 903 904 spin_unlock_irqrestore(&priv->ctx_lock, flags); 905 906 return result; 907 } 908 EXPORT_SYMBOL(mlx5_get_protocol_dev); 909 910 static int mlx5_auto_fw_update; 911 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 912 &mlx5_auto_fw_update, 0, 913 "Allow automatic firmware update on driver start"); 914 static int 915 mlx5_firmware_update(struct mlx5_core_dev *dev) 916 { 917 const struct firmware *fw; 918 int err; 919 920 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update); 921 if (!mlx5_auto_fw_update) 922 return (0); 923 fw = firmware_get("mlx5fw_mfa"); 924 if (fw) { 925 err = mlx5_firmware_flash(dev, fw); 926 firmware_put(fw, FIRMWARE_UNLOAD); 927 } 928 else 929 return (-ENOENT); 930 931 return err; 932 } 933 934 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 935 { 936 struct pci_dev *pdev = dev->pdev; 937 int err; 938 939 pdev = dev->pdev; 940 pci_set_drvdata(dev->pdev, dev); 941 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 942 priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 943 944 mutex_init(&priv->pgdir_mutex); 945 INIT_LIST_HEAD(&priv->pgdir_list); 946 spin_lock_init(&priv->mkey_lock); 947 948 err = mlx5_pci_enable_device(dev); 949 if (err) { 950 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 951 goto err_dbg; 952 } 953 954 err = request_bar(pdev); 955 if (err) { 956 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 957 goto err_disable; 958 } 959 960 pci_set_master(pdev); 961 962 err = set_dma_caps(pdev); 963 if (err) { 964 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 965 goto err_clr_master; 966 } 967 968 dev->iseg_base = pci_resource_start(dev->pdev, 0); 969 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 970 if (!dev->iseg) { 971 err = -ENOMEM; 972 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 973 goto err_clr_master; 974 } 975 976 return 0; 977 978 err_clr_master: 979 release_bar(dev->pdev); 980 err_disable: 981 mlx5_pci_disable_device(dev); 982 err_dbg: 983 return err; 984 } 985 986 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 987 { 988 #ifdef PCI_IOV 989 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) 990 pci_iov_detach(dev->pdev->dev.bsddev); 991 #endif 992 iounmap(dev->iseg); 993 release_bar(dev->pdev); 994 mlx5_pci_disable_device(dev); 995 } 996 997 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 998 { 999 int err; 1000 1001 err = mlx5_vsc_find_cap(dev); 1002 if (err) 1003 mlx5_core_warn(dev, "Unable to find vendor specific capabilities\n"); 1004 1005 err = mlx5_query_hca_caps(dev); 1006 if (err) { 1007 mlx5_core_err(dev, "query hca failed\n"); 1008 goto out; 1009 } 1010 1011 err = mlx5_query_board_id(dev); 1012 if (err) { 1013 mlx5_core_err(dev, "query board id failed\n"); 1014 goto out; 1015 } 1016 1017 err = mlx5_eq_init(dev); 1018 if (err) { 1019 mlx5_core_err(dev, "failed to initialize eq\n"); 1020 goto out; 1021 } 1022 1023 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 1024 1025 err = mlx5_init_cq_table(dev); 1026 if (err) { 1027 mlx5_core_err(dev, "failed to initialize cq table\n"); 1028 goto err_eq_cleanup; 1029 } 1030 1031 mlx5_init_qp_table(dev); 1032 mlx5_init_srq_table(dev); 1033 mlx5_init_mr_table(dev); 1034 1035 mlx5_init_reserved_gids(dev); 1036 mlx5_fpga_init(dev); 1037 1038 #ifdef RATELIMIT 1039 err = mlx5_init_rl_table(dev); 1040 if (err) { 1041 mlx5_core_err(dev, "Failed to init rate limiting\n"); 1042 goto err_tables_cleanup; 1043 } 1044 #endif 1045 return 0; 1046 1047 #ifdef RATELIMIT 1048 err_tables_cleanup: 1049 mlx5_cleanup_mr_table(dev); 1050 mlx5_cleanup_srq_table(dev); 1051 mlx5_cleanup_qp_table(dev); 1052 mlx5_cleanup_cq_table(dev); 1053 #endif 1054 1055 err_eq_cleanup: 1056 mlx5_eq_cleanup(dev); 1057 1058 out: 1059 return err; 1060 } 1061 1062 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1063 { 1064 #ifdef RATELIMIT 1065 mlx5_cleanup_rl_table(dev); 1066 #endif 1067 mlx5_fpga_cleanup(dev); 1068 mlx5_cleanup_reserved_gids(dev); 1069 mlx5_cleanup_mr_table(dev); 1070 mlx5_cleanup_srq_table(dev); 1071 mlx5_cleanup_qp_table(dev); 1072 mlx5_cleanup_cq_table(dev); 1073 mlx5_eq_cleanup(dev); 1074 } 1075 1076 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1077 bool boot) 1078 { 1079 int err; 1080 1081 mutex_lock(&dev->intf_state_mutex); 1082 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1083 mlx5_core_warn(dev, "interface is up, NOP\n"); 1084 goto out; 1085 } 1086 1087 mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n", 1088 fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 1089 1090 /* 1091 * On load removing any previous indication of internal error, 1092 * device is up 1093 */ 1094 dev->state = MLX5_DEVICE_STATE_UP; 1095 1096 /* wait for firmware to accept initialization segments configurations 1097 */ 1098 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, 1099 FW_INIT_WARN_MESSAGE_INTERVAL); 1100 if (err) { 1101 dev_err(&dev->pdev->dev, 1102 "Firmware over %d MS in pre-initializing state, aborting\n", 1103 FW_PRE_INIT_TIMEOUT_MILI); 1104 goto out_err; 1105 } 1106 1107 err = mlx5_cmd_init(dev); 1108 if (err) { 1109 mlx5_core_err(dev, 1110 "Failed initializing command interface, aborting\n"); 1111 goto out_err; 1112 } 1113 1114 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 1115 if (err) { 1116 mlx5_core_err(dev, 1117 "Firmware over %d MS in initializing state, aborting\n", 1118 FW_INIT_TIMEOUT_MILI); 1119 goto err_cmd_cleanup; 1120 } 1121 1122 err = mlx5_core_enable_hca(dev, 0); 1123 if (err) { 1124 mlx5_core_err(dev, "enable hca failed\n"); 1125 goto err_cmd_cleanup; 1126 } 1127 1128 err = mlx5_core_set_issi(dev); 1129 if (err) { 1130 mlx5_core_err(dev, "failed to set issi\n"); 1131 goto err_disable_hca; 1132 } 1133 1134 err = mlx5_pagealloc_start(dev); 1135 if (err) { 1136 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n"); 1137 goto err_disable_hca; 1138 } 1139 1140 err = mlx5_satisfy_startup_pages(dev, 1); 1141 if (err) { 1142 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1143 goto err_pagealloc_stop; 1144 } 1145 1146 err = set_hca_ctrl(dev); 1147 if (err) { 1148 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1149 goto reclaim_boot_pages; 1150 } 1151 1152 err = handle_hca_cap(dev); 1153 if (err) { 1154 mlx5_core_err(dev, "handle_hca_cap failed\n"); 1155 goto reclaim_boot_pages; 1156 } 1157 1158 err = handle_hca_cap_atomic(dev); 1159 if (err) { 1160 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 1161 goto reclaim_boot_pages; 1162 } 1163 1164 err = handle_hca_cap_2(dev); 1165 if (err) { 1166 mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); 1167 goto reclaim_boot_pages; 1168 } 1169 1170 err = mlx5_satisfy_startup_pages(dev, 0); 1171 if (err) { 1172 mlx5_core_err(dev, "failed to allocate init pages\n"); 1173 goto reclaim_boot_pages; 1174 } 1175 1176 err = mlx5_cmd_init_hca(dev); 1177 if (err) { 1178 mlx5_core_err(dev, "init hca failed\n"); 1179 goto reclaim_boot_pages; 1180 } 1181 1182 mlx5_set_driver_version(dev); 1183 1184 mlx5_start_health_poll(dev); 1185 1186 if (boot && (err = mlx5_init_once(dev, priv))) { 1187 mlx5_core_err(dev, "sw objs init failed\n"); 1188 goto err_stop_poll; 1189 } 1190 1191 dev->priv.uar = mlx5_get_uars_page(dev); 1192 if (IS_ERR(dev->priv.uar)) { 1193 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1194 err = PTR_ERR(dev->priv.uar); 1195 goto err_cleanup_once; 1196 } 1197 1198 err = mlx5_enable_msix(dev); 1199 if (err) { 1200 mlx5_core_err(dev, "enable msix failed\n"); 1201 goto err_cleanup_uar; 1202 } 1203 1204 err = mlx5_start_eqs(dev); 1205 if (err) { 1206 mlx5_core_err(dev, "Failed to start pages and async EQs\n"); 1207 goto err_disable_msix; 1208 } 1209 1210 err = alloc_comp_eqs(dev); 1211 if (err) { 1212 mlx5_core_err(dev, "Failed to alloc completion EQs\n"); 1213 goto err_stop_eqs; 1214 } 1215 1216 err = mlx5_fs_core_init(dev); 1217 if (err) { 1218 mlx5_core_err(dev, "flow steering init %d\n", err); 1219 goto err_free_comp_eqs; 1220 } 1221 1222 err = mlx5_core_set_hca_defaults(dev); 1223 if (err) { 1224 mlx5_core_err(dev, "Failed to set HCA defaults %d\n", err); 1225 goto err_free_comp_eqs; 1226 } 1227 1228 err = mlx5_mpfs_init(dev); 1229 if (err) { 1230 mlx5_core_err(dev, "mpfs init failed %d\n", err); 1231 goto err_fs; 1232 } 1233 1234 err = mlx5_fpga_device_start(dev); 1235 if (err) { 1236 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1237 goto err_mpfs; 1238 } 1239 1240 err = mlx5_diag_cnt_init(dev); 1241 if (err) { 1242 mlx5_core_err(dev, "diag cnt init failed %d\n", err); 1243 goto err_fpga; 1244 } 1245 1246 err = mlx5_register_device(dev); 1247 if (err) { 1248 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err); 1249 goto err_diag_cnt; 1250 } 1251 1252 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1253 1254 out: 1255 mutex_unlock(&dev->intf_state_mutex); 1256 return 0; 1257 1258 err_diag_cnt: 1259 mlx5_diag_cnt_cleanup(dev); 1260 1261 err_fpga: 1262 mlx5_fpga_device_stop(dev); 1263 1264 err_mpfs: 1265 mlx5_mpfs_destroy(dev); 1266 1267 err_fs: 1268 mlx5_cleanup_fs(dev); 1269 1270 err_free_comp_eqs: 1271 free_comp_eqs(dev); 1272 1273 err_stop_eqs: 1274 mlx5_stop_eqs(dev); 1275 1276 err_disable_msix: 1277 mlx5_disable_msix(dev); 1278 1279 err_cleanup_uar: 1280 mlx5_put_uars_page(dev, dev->priv.uar); 1281 1282 err_cleanup_once: 1283 if (boot) 1284 mlx5_cleanup_once(dev); 1285 1286 err_stop_poll: 1287 mlx5_stop_health_poll(dev, boot); 1288 if (mlx5_cmd_teardown_hca(dev)) { 1289 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1290 goto out_err; 1291 } 1292 1293 reclaim_boot_pages: 1294 mlx5_reclaim_startup_pages(dev); 1295 1296 err_pagealloc_stop: 1297 mlx5_pagealloc_stop(dev); 1298 1299 err_disable_hca: 1300 mlx5_core_disable_hca(dev); 1301 1302 err_cmd_cleanup: 1303 mlx5_cmd_cleanup(dev); 1304 1305 out_err: 1306 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1307 mutex_unlock(&dev->intf_state_mutex); 1308 1309 return err; 1310 } 1311 1312 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1313 bool cleanup) 1314 { 1315 int err = 0; 1316 1317 if (cleanup) 1318 mlx5_drain_health_recovery(dev); 1319 1320 mutex_lock(&dev->intf_state_mutex); 1321 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1322 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__); 1323 if (cleanup) 1324 mlx5_cleanup_once(dev); 1325 goto out; 1326 } 1327 1328 mlx5_unregister_device(dev); 1329 1330 mlx5_eswitch_cleanup(dev->priv.eswitch); 1331 mlx5_diag_cnt_cleanup(dev); 1332 mlx5_fpga_device_stop(dev); 1333 mlx5_mpfs_destroy(dev); 1334 mlx5_fs_core_cleanup(dev); 1335 mlx5_wait_for_reclaim_vfs_pages(dev); 1336 free_comp_eqs(dev); 1337 mlx5_stop_eqs(dev); 1338 mlx5_disable_msix(dev); 1339 mlx5_put_uars_page(dev, dev->priv.uar); 1340 if (cleanup) 1341 mlx5_cleanup_once(dev); 1342 mlx5_stop_health_poll(dev, cleanup); 1343 err = mlx5_cmd_teardown_hca(dev); 1344 if (err) { 1345 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1346 goto out; 1347 } 1348 mlx5_pagealloc_stop(dev); 1349 mlx5_reclaim_startup_pages(dev); 1350 mlx5_core_disable_hca(dev); 1351 mlx5_cmd_cleanup(dev); 1352 1353 out: 1354 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1355 mutex_unlock(&dev->intf_state_mutex); 1356 return err; 1357 } 1358 1359 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1360 unsigned long param) 1361 { 1362 struct mlx5_priv *priv = &dev->priv; 1363 struct mlx5_device_context *dev_ctx; 1364 unsigned long flags; 1365 1366 spin_lock_irqsave(&priv->ctx_lock, flags); 1367 1368 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1369 if (dev_ctx->intf->event) 1370 dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1371 1372 spin_unlock_irqrestore(&priv->ctx_lock, flags); 1373 } 1374 1375 struct mlx5_core_event_handler { 1376 void (*event)(struct mlx5_core_dev *dev, 1377 enum mlx5_dev_event event, 1378 void *data); 1379 }; 1380 1381 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e, 1382 1383 #define MLX5_PORT_MODULE_ERROR_STATS(m) \ 1384 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \ 1385 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \ 1386 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \ 1387 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \ 1388 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \ 1389 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \ 1390 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \ 1391 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") \ 1392 m(+1, u64, pmd_type_not_enabled, "pmd_type_not_enabled", "PMD type is not enabled") \ 1393 m(+1, u64, laster_tec_failure, "laster_tec_failure", "Laster TEC failure") \ 1394 m(+1, u64, high_current, "high_current", "High current") \ 1395 m(+1, u64, high_voltage, "high_voltage", "High voltage") \ 1396 m(+1, u64, pcie_sys_power_slot_exceeded, "pcie_sys_power_slot_exceeded", "PCIe system power slot Exceeded") \ 1397 m(+1, u64, high_power, "high_power", "High power") \ 1398 m(+1, u64, module_state_machine_fault, "module_state_machine_fault", "Module State Machine fault") 1399 1400 static const char *mlx5_pme_err_desc[] = { 1401 MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC) 1402 }; 1403 1404 static int init_one(struct pci_dev *pdev, 1405 const struct pci_device_id *id) 1406 { 1407 struct mlx5_core_dev *dev; 1408 struct mlx5_priv *priv; 1409 device_t bsddev = pdev->dev.bsddev; 1410 #ifdef PCI_IOV 1411 nvlist_t *pf_schema, *vf_schema; 1412 int num_vfs, sriov_pos; 1413 #endif 1414 int i,err; 1415 int numa_node; 1416 struct sysctl_oid *pme_sysctl_node; 1417 struct sysctl_oid *pme_err_sysctl_node; 1418 struct sysctl_oid *cap_sysctl_node; 1419 struct sysctl_oid *current_cap_sysctl_node; 1420 struct sysctl_oid *max_cap_sysctl_node; 1421 1422 printk_once("mlx5: %s", mlx5_version); 1423 1424 numa_node = dev_to_node(&pdev->dev); 1425 1426 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, numa_node); 1427 1428 priv = &dev->priv; 1429 priv->numa_node = numa_node; 1430 1431 if (id) 1432 priv->pci_dev_data = id->driver_data; 1433 1434 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) { 1435 device_printf(bsddev, 1436 "WARN: selected profile out of range, selecting default (%d)\n", 1437 MLX5_DEFAULT_PROF); 1438 mlx5_prof_sel = MLX5_DEFAULT_PROF; 1439 } 1440 dev->profile = &profiles[mlx5_prof_sel]; 1441 dev->pdev = pdev; 1442 dev->event = mlx5_core_event; 1443 1444 /* Set desc */ 1445 device_set_desc(bsddev, mlx5_version); 1446 1447 sysctl_ctx_init(&dev->sysctl_ctx); 1448 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1449 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1450 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1451 "Maximum number of MSIX event queue vectors, if set"); 1452 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1453 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1454 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0, 1455 "0:Invalid 1:Sufficient 2:Insufficient"); 1456 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1457 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1458 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0, 1459 "Current power value in Watts"); 1460 1461 pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1462 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1463 OID_AUTO, "pme_stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1464 "Port module event statistics"); 1465 if (pme_sysctl_node == NULL) { 1466 err = -ENOMEM; 1467 goto clean_sysctl_ctx; 1468 } 1469 pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1470 SYSCTL_CHILDREN(pme_sysctl_node), 1471 OID_AUTO, "errors", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1472 "Port module event error statistics"); 1473 if (pme_err_sysctl_node == NULL) { 1474 err = -ENOMEM; 1475 goto clean_sysctl_ctx; 1476 } 1477 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1478 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1479 "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1480 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED], 1481 0, "Number of time module plugged"); 1482 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1483 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1484 "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1485 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED], 1486 0, "Number of time module unplugged"); 1487 for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) { 1488 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1489 SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO, 1490 mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE, 1491 &dev->priv.pme_stats.error_counters[i], 1492 0, mlx5_pme_err_desc[2 * i + 1]); 1493 } 1494 1495 cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1496 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1497 OID_AUTO, "caps", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1498 "hardware capabilities raw bitstrings"); 1499 if (cap_sysctl_node == NULL) { 1500 err = -ENOMEM; 1501 goto clean_sysctl_ctx; 1502 } 1503 current_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1504 SYSCTL_CHILDREN(cap_sysctl_node), 1505 OID_AUTO, "current", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1506 ""); 1507 if (current_cap_sysctl_node == NULL) { 1508 err = -ENOMEM; 1509 goto clean_sysctl_ctx; 1510 } 1511 max_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1512 SYSCTL_CHILDREN(cap_sysctl_node), 1513 OID_AUTO, "max", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1514 ""); 1515 if (max_cap_sysctl_node == NULL) { 1516 err = -ENOMEM; 1517 goto clean_sysctl_ctx; 1518 } 1519 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1520 SYSCTL_CHILDREN(current_cap_sysctl_node), 1521 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE, 1522 &dev->hca_caps_cur[MLX5_CAP_GENERAL], 1523 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1524 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1525 SYSCTL_CHILDREN(max_cap_sysctl_node), 1526 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE, 1527 &dev->hca_caps_max[MLX5_CAP_GENERAL], 1528 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1529 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1530 SYSCTL_CHILDREN(current_cap_sysctl_node), 1531 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE, 1532 &dev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], 1533 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1534 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1535 SYSCTL_CHILDREN(max_cap_sysctl_node), 1536 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE, 1537 &dev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], 1538 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1539 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1540 SYSCTL_CHILDREN(current_cap_sysctl_node), 1541 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE, 1542 &dev->hca_caps_cur[MLX5_CAP_ODP], 1543 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1544 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1545 SYSCTL_CHILDREN(max_cap_sysctl_node), 1546 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE, 1547 &dev->hca_caps_max[MLX5_CAP_ODP], 1548 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1549 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1550 SYSCTL_CHILDREN(current_cap_sysctl_node), 1551 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE, 1552 &dev->hca_caps_cur[MLX5_CAP_ATOMIC], 1553 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1554 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1555 SYSCTL_CHILDREN(max_cap_sysctl_node), 1556 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE, 1557 &dev->hca_caps_max[MLX5_CAP_ATOMIC], 1558 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1559 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1560 SYSCTL_CHILDREN(current_cap_sysctl_node), 1561 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE, 1562 &dev->hca_caps_cur[MLX5_CAP_ROCE], 1563 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1564 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1565 SYSCTL_CHILDREN(max_cap_sysctl_node), 1566 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE, 1567 &dev->hca_caps_max[MLX5_CAP_ROCE], 1568 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1569 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1570 SYSCTL_CHILDREN(current_cap_sysctl_node), 1571 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1572 &dev->hca_caps_cur[MLX5_CAP_IPOIB_OFFLOADS], 1573 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1574 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1575 SYSCTL_CHILDREN(max_cap_sysctl_node), 1576 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1577 &dev->hca_caps_max[MLX5_CAP_IPOIB_OFFLOADS], 1578 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1579 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1580 SYSCTL_CHILDREN(current_cap_sysctl_node), 1581 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1582 &dev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], 1583 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1584 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1585 SYSCTL_CHILDREN(max_cap_sysctl_node), 1586 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1587 &dev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], 1588 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1589 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1590 SYSCTL_CHILDREN(current_cap_sysctl_node), 1591 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1592 &dev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], 1593 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1594 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1595 SYSCTL_CHILDREN(max_cap_sysctl_node), 1596 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1597 &dev->hca_caps_max[MLX5_CAP_FLOW_TABLE], 1598 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1599 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1600 SYSCTL_CHILDREN(current_cap_sysctl_node), 1601 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1602 &dev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], 1603 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1604 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1605 SYSCTL_CHILDREN(max_cap_sysctl_node), 1606 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1607 &dev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], 1608 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1609 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1610 SYSCTL_CHILDREN(current_cap_sysctl_node), 1611 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE, 1612 &dev->hca_caps_cur[MLX5_CAP_ESWITCH], 1613 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1614 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1615 SYSCTL_CHILDREN(max_cap_sysctl_node), 1616 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE, 1617 &dev->hca_caps_max[MLX5_CAP_ESWITCH], 1618 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1619 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1620 SYSCTL_CHILDREN(current_cap_sysctl_node), 1621 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE, 1622 &dev->hca_caps_cur[MLX5_CAP_SNAPSHOT], 1623 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1624 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1625 SYSCTL_CHILDREN(max_cap_sysctl_node), 1626 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE, 1627 &dev->hca_caps_max[MLX5_CAP_SNAPSHOT], 1628 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1629 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1630 SYSCTL_CHILDREN(current_cap_sysctl_node), 1631 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE, 1632 &dev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], 1633 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1634 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1635 SYSCTL_CHILDREN(max_cap_sysctl_node), 1636 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE, 1637 &dev->hca_caps_max[MLX5_CAP_VECTOR_CALC], 1638 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1639 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1640 SYSCTL_CHILDREN(current_cap_sysctl_node), 1641 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE, 1642 &dev->hca_caps_cur[MLX5_CAP_QOS], 1643 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1644 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1645 SYSCTL_CHILDREN(max_cap_sysctl_node), 1646 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE, 1647 &dev->hca_caps_max[MLX5_CAP_QOS], 1648 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1649 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1650 SYSCTL_CHILDREN(current_cap_sysctl_node), 1651 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1652 &dev->hca_caps_cur[MLX5_CAP_DEBUG], 1653 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1654 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1655 SYSCTL_CHILDREN(max_cap_sysctl_node), 1656 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1657 &dev->hca_caps_max[MLX5_CAP_DEBUG], 1658 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1659 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1660 SYSCTL_CHILDREN(cap_sysctl_node), 1661 OID_AUTO, "pcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1662 &dev->caps.pcam, sizeof(dev->caps.pcam), "IU", ""); 1663 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1664 SYSCTL_CHILDREN(cap_sysctl_node), 1665 OID_AUTO, "mcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1666 &dev->caps.mcam, sizeof(dev->caps.mcam), "IU", ""); 1667 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1668 SYSCTL_CHILDREN(cap_sysctl_node), 1669 OID_AUTO, "qcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1670 &dev->caps.qcam, sizeof(dev->caps.qcam), "IU", ""); 1671 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1672 SYSCTL_CHILDREN(cap_sysctl_node), 1673 OID_AUTO, "fpga", CTLFLAG_RD | CTLFLAG_MPSAFE, 1674 &dev->caps.fpga, sizeof(dev->caps.fpga), "IU", ""); 1675 1676 INIT_LIST_HEAD(&priv->ctx_list); 1677 spin_lock_init(&priv->ctx_lock); 1678 mutex_init(&dev->pci_status_mutex); 1679 mutex_init(&dev->intf_state_mutex); 1680 1681 mutex_init(&priv->bfregs.reg_head.lock); 1682 mutex_init(&priv->bfregs.wc_head.lock); 1683 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1684 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1685 1686 mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW); 1687 err = mlx5_pci_init(dev, priv); 1688 if (err) { 1689 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err); 1690 goto clean_dev; 1691 } 1692 1693 err = mlx5_health_init(dev); 1694 if (err) { 1695 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err); 1696 goto close_pci; 1697 } 1698 1699 mlx5_pagealloc_init(dev); 1700 1701 err = mlx5_fs_core_alloc(dev); 1702 if (err) { 1703 mlx5_core_err(dev, "Failed to alloc flow steering\n"); 1704 goto clean_health; 1705 } 1706 1707 err = mlx5_load_one(dev, priv, true); 1708 if (err) { 1709 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err); 1710 goto clean_fs; 1711 } 1712 1713 mlx5_fwdump_prep(dev); 1714 1715 mlx5_firmware_update(dev); 1716 1717 #ifdef PCI_IOV 1718 if (MLX5_CAP_GEN(dev, vport_group_manager)) { 1719 if (pci_find_extcap(bsddev, PCIZ_SRIOV, &sriov_pos) == 0) { 1720 num_vfs = pci_read_config(bsddev, sriov_pos + 1721 PCIR_SRIOV_TOTAL_VFS, 2); 1722 } else { 1723 mlx5_core_info(dev, "cannot find SR-IOV PCIe cap\n"); 1724 num_vfs = 0; 1725 } 1726 err = mlx5_eswitch_init(dev, 1 + num_vfs); 1727 if (err == 0) { 1728 pf_schema = pci_iov_schema_alloc_node(); 1729 vf_schema = pci_iov_schema_alloc_node(); 1730 pci_iov_schema_add_unicast_mac(vf_schema, 1731 iov_mac_addr_name, 0, NULL); 1732 pci_iov_schema_add_vlan(vf_schema, 1733 iov_vlan_name, 0, 0); 1734 pci_iov_schema_add_uint64(vf_schema, iov_node_guid_name, 1735 0, 0); 1736 pci_iov_schema_add_uint64(vf_schema, iov_port_guid_name, 1737 0, 0); 1738 err = pci_iov_attach(bsddev, pf_schema, vf_schema); 1739 if (err == 0) { 1740 dev->iov_pf = true; 1741 } else { 1742 device_printf(bsddev, 1743 "Failed to initialize SR-IOV support, error %d\n", 1744 err); 1745 } 1746 } else { 1747 mlx5_core_err(dev, "eswitch init failed, error %d\n", 1748 err); 1749 } 1750 } 1751 #endif 1752 1753 pci_save_state(pdev); 1754 return 0; 1755 1756 clean_fs: 1757 mlx5_fs_core_free(dev); 1758 clean_health: 1759 mlx5_pagealloc_cleanup(dev); 1760 mlx5_health_cleanup(dev); 1761 close_pci: 1762 mlx5_pci_close(dev, priv); 1763 clean_dev: 1764 mtx_destroy(&dev->dump_lock); 1765 clean_sysctl_ctx: 1766 sysctl_ctx_free(&dev->sysctl_ctx); 1767 kfree(dev); 1768 return err; 1769 } 1770 1771 static void remove_one(struct pci_dev *pdev) 1772 { 1773 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1774 struct mlx5_priv *priv = &dev->priv; 1775 1776 #ifdef PCI_IOV 1777 if (dev->iov_pf) { 1778 pci_iov_detach(pdev->dev.bsddev); 1779 mlx5_eswitch_disable_sriov(priv->eswitch); 1780 dev->iov_pf = false; 1781 } 1782 #endif 1783 1784 if (mlx5_unload_one(dev, priv, true)) { 1785 mlx5_core_err(dev, "mlx5_unload_one() failed, leaked %lld bytes\n", 1786 (long long)(dev->priv.fw_pages * MLX5_ADAPTER_PAGE_SIZE)); 1787 } 1788 1789 mlx5_fs_core_free(dev); 1790 mlx5_pagealloc_cleanup(dev); 1791 mlx5_health_cleanup(dev); 1792 mlx5_fwdump_clean(dev); 1793 mlx5_pci_close(dev, priv); 1794 mtx_destroy(&dev->dump_lock); 1795 pci_set_drvdata(pdev, NULL); 1796 sysctl_ctx_free(&dev->sysctl_ctx); 1797 kfree(dev); 1798 } 1799 1800 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1801 pci_channel_state_t state) 1802 { 1803 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1804 struct mlx5_priv *priv = &dev->priv; 1805 1806 mlx5_core_info(dev, "%s was called\n", __func__); 1807 mlx5_enter_error_state(dev, false); 1808 mlx5_unload_one(dev, priv, false); 1809 1810 if (state) { 1811 mlx5_drain_health_wq(dev); 1812 mlx5_pci_disable_device(dev); 1813 } 1814 1815 return state == pci_channel_io_perm_failure ? 1816 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1817 } 1818 1819 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1820 { 1821 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1822 int err = 0; 1823 1824 mlx5_core_info(dev,"%s was called\n", __func__); 1825 1826 err = mlx5_pci_enable_device(dev); 1827 if (err) { 1828 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n" 1829 ,err); 1830 return PCI_ERS_RESULT_DISCONNECT; 1831 } 1832 pci_set_master(pdev); 1833 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1834 pci_restore_state(pdev); 1835 pci_save_state(pdev); 1836 1837 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1838 } 1839 1840 /* wait for the device to show vital signs. For now we check 1841 * that we can read the device ID and that the health buffer 1842 * shows a non zero value which is different than 0xffffffff 1843 */ 1844 static void wait_vital(struct pci_dev *pdev) 1845 { 1846 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1847 struct mlx5_core_health *health = &dev->priv.health; 1848 const int niter = 100; 1849 u32 count; 1850 u16 did; 1851 int i; 1852 1853 /* Wait for firmware to be ready after reset */ 1854 msleep(1000); 1855 for (i = 0; i < niter; i++) { 1856 if (pci_read_config_word(pdev, 2, &did)) { 1857 mlx5_core_warn(dev, "failed reading config word\n"); 1858 break; 1859 } 1860 if (did == pdev->device) { 1861 mlx5_core_info(dev, 1862 "device ID correctly read after %d iterations\n", i); 1863 break; 1864 } 1865 msleep(50); 1866 } 1867 if (i == niter) 1868 mlx5_core_warn(dev, "could not read device ID\n"); 1869 1870 for (i = 0; i < niter; i++) { 1871 count = ioread32be(health->health_counter); 1872 if (count && count != 0xffffffff) { 1873 mlx5_core_info(dev, 1874 "Counter value 0x%x after %d iterations\n", count, i); 1875 break; 1876 } 1877 msleep(50); 1878 } 1879 1880 if (i == niter) 1881 mlx5_core_warn(dev, "could not read device ID\n"); 1882 } 1883 1884 static void mlx5_pci_resume(struct pci_dev *pdev) 1885 { 1886 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1887 struct mlx5_priv *priv = &dev->priv; 1888 int err; 1889 1890 mlx5_core_info(dev,"%s was called\n", __func__); 1891 1892 wait_vital(pdev); 1893 1894 err = mlx5_load_one(dev, priv, false); 1895 if (err) 1896 mlx5_core_err(dev, 1897 "mlx5_load_one failed with error code: %d\n" ,err); 1898 else 1899 mlx5_core_info(dev,"device recovered\n"); 1900 } 1901 1902 static const struct pci_error_handlers mlx5_err_handler = { 1903 .error_detected = mlx5_pci_err_detected, 1904 .slot_reset = mlx5_pci_slot_reset, 1905 .resume = mlx5_pci_resume 1906 }; 1907 1908 #ifdef PCI_IOV 1909 static int 1910 mlx5_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *pf_config) 1911 { 1912 struct pci_dev *pdev; 1913 struct mlx5_core_dev *core_dev; 1914 struct mlx5_priv *priv; 1915 int err; 1916 1917 pdev = device_get_softc(dev); 1918 core_dev = pci_get_drvdata(pdev); 1919 priv = &core_dev->priv; 1920 1921 if (priv->eswitch == NULL) 1922 return (ENXIO); 1923 if (priv->eswitch->total_vports < num_vfs + 1) 1924 num_vfs = priv->eswitch->total_vports - 1; 1925 err = mlx5_eswitch_enable_sriov(priv->eswitch, num_vfs); 1926 return (-err); 1927 } 1928 1929 static void 1930 mlx5_iov_uninit(device_t dev) 1931 { 1932 struct pci_dev *pdev; 1933 struct mlx5_core_dev *core_dev; 1934 struct mlx5_priv *priv; 1935 1936 pdev = device_get_softc(dev); 1937 core_dev = pci_get_drvdata(pdev); 1938 priv = &core_dev->priv; 1939 1940 mlx5_eswitch_disable_sriov(priv->eswitch); 1941 } 1942 1943 static int 1944 mlx5_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *vf_config) 1945 { 1946 struct pci_dev *pdev; 1947 struct mlx5_core_dev *core_dev; 1948 struct mlx5_priv *priv; 1949 const void *mac; 1950 size_t mac_size; 1951 uint64_t node_guid, port_guid; 1952 int error; 1953 1954 pdev = device_get_softc(dev); 1955 core_dev = pci_get_drvdata(pdev); 1956 priv = &core_dev->priv; 1957 1958 if (vfnum + 1 >= priv->eswitch->total_vports) 1959 return (ENXIO); 1960 1961 if (nvlist_exists_binary(vf_config, iov_mac_addr_name)) { 1962 mac = nvlist_get_binary(vf_config, iov_mac_addr_name, 1963 &mac_size); 1964 error = -mlx5_eswitch_set_vport_mac(priv->eswitch, 1965 vfnum + 1, __DECONST(u8 *, mac)); 1966 if (error != 0) { 1967 mlx5_core_err(core_dev, 1968 "setting MAC for VF %d failed, error %d\n", 1969 vfnum + 1, error); 1970 } 1971 } 1972 1973 if (nvlist_exists_number(vf_config, iov_vlan_name)) { 1974 uint16_t vlan = nvlist_get_number(vf_config, iov_vlan_name); 1975 1976 if (vlan == DOT1Q_VID_NULL) 1977 error = ENOTSUP; 1978 else { 1979 if (vlan == VF_VLAN_TRUNK) 1980 vlan = DOT1Q_VID_NULL; 1981 1982 error = -mlx5_eswitch_set_vport_vlan(priv->eswitch, 1983 vfnum + 1, vlan, 0); 1984 } 1985 if (error != 0) { 1986 mlx5_core_err(core_dev, 1987 "setting VLAN for VF %d failed, error %d\n", 1988 vfnum + 1, error); 1989 } 1990 } 1991 1992 if (nvlist_exists_number(vf_config, iov_node_guid_name)) { 1993 node_guid = nvlist_get_number(vf_config, iov_node_guid_name); 1994 error = -mlx5_modify_nic_vport_node_guid(core_dev, vfnum + 1, 1995 node_guid); 1996 if (error != 0) { 1997 mlx5_core_err(core_dev, 1998 "modifying node GUID for VF %d failed, error %d\n", 1999 vfnum + 1, error); 2000 } 2001 } 2002 2003 if (nvlist_exists_number(vf_config, iov_port_guid_name)) { 2004 port_guid = nvlist_get_number(vf_config, iov_port_guid_name); 2005 error = -mlx5_modify_nic_vport_port_guid(core_dev, vfnum + 1, 2006 port_guid); 2007 if (error != 0) { 2008 mlx5_core_err(core_dev, 2009 "modifying port GUID for VF %d failed, error %d\n", 2010 vfnum + 1, error); 2011 } 2012 } 2013 2014 error = -mlx5_eswitch_set_vport_state(priv->eswitch, vfnum + 1, 2015 VPORT_STATE_FOLLOW); 2016 if (error != 0) { 2017 mlx5_core_err(core_dev, 2018 "upping vport for VF %d failed, error %d\n", 2019 vfnum + 1, error); 2020 } 2021 error = -mlx5_core_enable_hca(core_dev, vfnum + 1); 2022 if (error != 0) { 2023 mlx5_core_err(core_dev, "enabling VF %d failed, error %d\n", 2024 vfnum + 1, error); 2025 } 2026 return (error); 2027 } 2028 #endif 2029 2030 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 2031 { 2032 bool fast_teardown, force_teardown; 2033 int err; 2034 2035 if (!mlx5_fast_unload_enabled) { 2036 mlx5_core_dbg(dev, "fast unload is disabled by user\n"); 2037 return -EOPNOTSUPP; 2038 } 2039 2040 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 2041 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 2042 2043 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 2044 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 2045 2046 if (!fast_teardown && !force_teardown) 2047 return -EOPNOTSUPP; 2048 2049 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 2050 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 2051 return -EAGAIN; 2052 } 2053 2054 /* Panic tear down fw command will stop the PCI bus communication 2055 * with the HCA, so the health polll is no longer needed. 2056 */ 2057 mlx5_drain_health_wq(dev); 2058 mlx5_stop_health_poll(dev, false); 2059 2060 err = mlx5_cmd_fast_teardown_hca(dev); 2061 if (!err) 2062 goto done; 2063 2064 err = mlx5_cmd_force_teardown_hca(dev); 2065 if (!err) 2066 goto done; 2067 2068 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 2069 mlx5_start_health_poll(dev); 2070 return err; 2071 done: 2072 mlx5_enter_error_state(dev, true); 2073 return 0; 2074 } 2075 2076 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev) 2077 { 2078 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 2079 int x; 2080 2081 mdev->priv.disable_irqs = 1; 2082 2083 /* wait for all IRQ handlers to finish processing */ 2084 for (x = 0; x != nvec; x++) 2085 synchronize_irq(mdev->priv.msix_arr[x].vector); 2086 } 2087 2088 static void shutdown_one(struct pci_dev *pdev) 2089 { 2090 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2091 struct mlx5_priv *priv = &dev->priv; 2092 int err; 2093 2094 /* enter polling mode */ 2095 mlx5_cmd_use_polling(dev); 2096 2097 set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state); 2098 2099 /* disable all interrupts */ 2100 mlx5_shutdown_disable_interrupts(dev); 2101 2102 err = mlx5_try_fast_unload(dev); 2103 if (err) 2104 mlx5_unload_one(dev, priv, false); 2105 mlx5_pci_disable_device(dev); 2106 } 2107 2108 static const struct pci_device_id mlx5_core_pci_table[] = { 2109 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 2110 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 2111 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 2112 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 2113 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 2114 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 2115 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5, PCIe 3.0 */ 2116 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 2117 { PCI_VDEVICE(MELLANOX, 4121) }, /* ConnectX-5 Ex */ 2118 { PCI_VDEVICE(MELLANOX, 4122) }, /* ConnectX-5 Ex VF */ 2119 { PCI_VDEVICE(MELLANOX, 4123) }, /* ConnectX-6 */ 2120 { PCI_VDEVICE(MELLANOX, 4124) }, /* ConnectX-6 VF */ 2121 { PCI_VDEVICE(MELLANOX, 4125) }, /* ConnectX-6 Dx */ 2122 { PCI_VDEVICE(MELLANOX, 4126) }, /* ConnectX Family mlx5Gen Virtual Function */ 2123 { PCI_VDEVICE(MELLANOX, 4127) }, /* ConnectX-6 LX */ 2124 { PCI_VDEVICE(MELLANOX, 4128) }, 2125 { PCI_VDEVICE(MELLANOX, 4129) }, /* ConnectX-7 */ 2126 { PCI_VDEVICE(MELLANOX, 4130) }, 2127 { PCI_VDEVICE(MELLANOX, 4131) }, /* ConnectX-8 */ 2128 { PCI_VDEVICE(MELLANOX, 4132) }, 2129 { PCI_VDEVICE(MELLANOX, 4133) }, 2130 { PCI_VDEVICE(MELLANOX, 4134) }, 2131 { PCI_VDEVICE(MELLANOX, 4135) }, 2132 { PCI_VDEVICE(MELLANOX, 4136) }, 2133 { PCI_VDEVICE(MELLANOX, 4137) }, 2134 { PCI_VDEVICE(MELLANOX, 4138) }, 2135 { PCI_VDEVICE(MELLANOX, 4139) }, 2136 { PCI_VDEVICE(MELLANOX, 4140) }, 2137 { PCI_VDEVICE(MELLANOX, 4141) }, 2138 { PCI_VDEVICE(MELLANOX, 4142) }, 2139 { PCI_VDEVICE(MELLANOX, 4143) }, 2140 { PCI_VDEVICE(MELLANOX, 4144) }, 2141 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2142 { PCI_VDEVICE(MELLANOX, 0xa2d3) }, /* BlueField integrated ConnectX-5 network controller VF */ 2143 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2144 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2145 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 2146 { } 2147 }; 2148 2149 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2150 2151 void mlx5_disable_device(struct mlx5_core_dev *dev) 2152 { 2153 mlx5_pci_err_detected(dev->pdev, 0); 2154 } 2155 2156 void mlx5_recover_device(struct mlx5_core_dev *dev) 2157 { 2158 mlx5_pci_disable_device(dev); 2159 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 2160 mlx5_pci_resume(dev->pdev); 2161 } 2162 2163 struct pci_driver mlx5_core_driver = { 2164 .name = DRIVER_NAME, 2165 .id_table = mlx5_core_pci_table, 2166 .shutdown = shutdown_one, 2167 .probe = init_one, 2168 .remove = remove_one, 2169 .err_handler = &mlx5_err_handler, 2170 #ifdef PCI_IOV 2171 .bsd_iov_init = mlx5_iov_init, 2172 .bsd_iov_uninit = mlx5_iov_uninit, 2173 .bsd_iov_add_vf = mlx5_iov_add_vf, 2174 #endif 2175 }; 2176 2177 static int __init init(void) 2178 { 2179 int err; 2180 2181 err = pci_register_driver(&mlx5_core_driver); 2182 if (err) 2183 goto err_debug; 2184 2185 err = mlx5_ctl_init(); 2186 if (err) 2187 goto err_ctl; 2188 2189 return 0; 2190 2191 err_ctl: 2192 pci_unregister_driver(&mlx5_core_driver); 2193 2194 err_debug: 2195 return err; 2196 } 2197 2198 static void __exit cleanup(void) 2199 { 2200 mlx5_ctl_fini(); 2201 pci_unregister_driver(&mlx5_core_driver); 2202 } 2203 2204 module_init_order(init, SI_ORDER_FIRST); 2205 module_exit_order(cleanup, SI_ORDER_FIRST); 2206