1//===-- SPIRVRegisterInfo.td - SPIR-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// Declarations that describe the SPIR-V register file. 10// 11//===----------------------------------------------------------------------===// 12 13let Namespace = "SPIRV" in { 14 // Pointer types for patterns with the GlobalISelEmitter 15 def p32 : PtrValueType <i32, 0>; 16 def p64 : PtrValueType <i64, 0>; 17 18 class VTPtrVec<int nelem, PtrValueType ptr> 19 : VTVec<nelem, ValueType<ptr.Size, ptr.Value>, ptr.Value> { 20 int isPointer = true; 21 } 22 23 def v2p32 : VTPtrVec<2, p32>; 24 def v2p64 : VTPtrVec<2, p64>; 25 26 // Class for type registers 27 def TYPE0 : Register<"TYPE0">; 28 def TYPE : RegisterClass<"SPIRV", [i32], 32, (add TYPE0)>; 29 30 // Class for non-type registers 31 def ID0 : Register<"ID0">; 32 def ID640 : Register<"ID640">; 33 def fID0 : Register<"fID0">; 34 def fID640 : Register<"fID640">; 35 def pID320 : Register<"pID320">; 36 def pID640 : Register<"pID640">; 37 def vID0 : Register<"vID0">; 38 def vfID0 : Register<"vfID0">; 39 def vpID320 : Register<"vpID320">; 40 def vpID640 : Register<"vpID640">; 41 42 def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>; 43 def ID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>; 44 def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>; 45 def fID64 : RegisterClass<"SPIRV", [f64], 32, (add fID640)>; 46 def pID32 : RegisterClass<"SPIRV", [p32], 32, (add pID320)>; 47 def pID64 : RegisterClass<"SPIRV", [p64], 32, (add pID640)>; 48 def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>; 49 def vfID : RegisterClass<"SPIRV", [v2f32], 32, (add vfID0)>; 50 def vpID32 : RegisterClass<"SPIRV", [v2p32], 32, (add vpID320)>; 51 def vpID64 : RegisterClass<"SPIRV", [v2p64], 32, (add vpID640)>; 52 53 def ANYID : RegisterClass< 54 "SPIRV", 55 [i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64], 56 32, 57 (add ID0, ID640, fID0, fID640, pID320, pID640, vID0, vfID0, vpID320, vpID640)>; 58 59 // A few instructions like OpName can take ids from both type and non-type 60 // instructions, so we need a super-class to allow for both to count as valid 61 // arguments for these instructions. 62 def ANY : RegisterClass<"SPIRV", [i32], 32, (add TYPE, ID)>; 63} 64