1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2022 Intel Corporation 3 * SFF-8636 standards based QSFP EEPROM Field Definitions 4 */ 5 6 #ifndef _SFF_8636_H_ 7 #define _SFF_8636_H_ 8 9 /*------------------------------------------------------------------------------ 10 * 11 * QSFP EEPROM data structures 12 * 13 * register info from SFF-8636 Rev 2.7 14 */ 15 16 /*------------------------------------------------------------------------------ 17 * 18 * Lower Memory Page 00h 19 * Measurement, Diagnostic and Control Functions 20 */ 21 /* Identifier - 0 */ 22 /* Values are defined under SFF_8024_ID_OFFSET */ 23 #define SFF_8636_ID_OFFSET 0x00 24 25 #define SFF_8636_REV_COMPLIANCE_OFFSET 0x01 26 #define SFF_8636_REV_UNSPECIFIED 0x00 27 #define SFF_8636_REV_8436_48 0x01 28 #define SFF_8636_REV_8436_8636 0x02 29 #define SFF_8636_REV_8636_13 0x03 30 #define SFF_8636_REV_8636_14 0x04 31 #define SFF_8636_REV_8636_15 0x05 32 #define SFF_8636_REV_8636_20 0x06 33 #define SFF_8636_REV_8636_27 0x07 34 35 #define SFF_8636_STATUS_2_OFFSET 0x02 36 /* Flat Memory:0- Paging, 1- Page 0 only */ 37 #define SFF_8636_STATUS_PAGE_3_PRESENT RTE_BIT32(2) 38 #define SFF_8636_STATUS_INTL_OUTPUT RTE_BIT32(1) 39 #define SFF_8636_STATUS_DATA_NOT_READY RTE_BIT32(0) 40 41 /* Channel Status Interrupt Flags - 3-5 */ 42 #define SFF_8636_LOS_AW_OFFSET 0x03 43 #define SFF_8636_TX4_LOS_AW RTE_BIT32(7) 44 #define SFF_8636_TX3_LOS_AW RTE_BIT32(6) 45 #define SFF_8636_TX2_LOS_AW RTE_BIT32(5) 46 #define SFF_8636_TX1_LOS_AW RTE_BIT32(4) 47 #define SFF_8636_RX4_LOS_AW RTE_BIT32(3) 48 #define SFF_8636_RX3_LOS_AW RTE_BIT32(2) 49 #define SFF_8636_RX2_LOS_AW RTE_BIT32(1) 50 #define SFF_8636_RX1_LOS_AW RTE_BIT32(0) 51 52 #define SFF_8636_FAULT_AW_OFFSET 0x04 53 #define SFF_8636_TX4_FAULT_AW RTE_BIT32(3) 54 #define SFF_8636_TX3_FAULT_AW RTE_BIT32(2) 55 #define SFF_8636_TX2_FAULT_AW RTE_BIT32(1) 56 #define SFF_8636_TX1_FAULT_AW RTE_BIT32(0) 57 58 /* Module Monitor Interrupt Flags - 6-8 */ 59 #define SFF_8636_TEMP_AW_OFFSET 0x06 60 #define SFF_8636_TEMP_HALARM_STATUS RTE_BIT32(7) 61 #define SFF_8636_TEMP_LALARM_STATUS RTE_BIT32(6) 62 #define SFF_8636_TEMP_HWARN_STATUS RTE_BIT32(5) 63 #define SFF_8636_TEMP_LWARN_STATUS RTE_BIT32(4) 64 65 #define SFF_8636_VCC_AW_OFFSET 0x07 66 #define SFF_8636_VCC_HALARM_STATUS RTE_BIT32(7) 67 #define SFF_8636_VCC_LALARM_STATUS RTE_BIT32(6) 68 #define SFF_8636_VCC_HWARN_STATUS RTE_BIT32(5) 69 #define SFF_8636_VCC_LWARN_STATUS RTE_BIT32(4) 70 71 /* Channel Monitor Interrupt Flags - 9-21 */ 72 #define SFF_8636_RX_PWR_12_AW_OFFSET 0x09 73 #define SFF_8636_RX_PWR_1_HALARM RTE_BIT32(7) 74 #define SFF_8636_RX_PWR_1_LALARM RTE_BIT32(6) 75 #define SFF_8636_RX_PWR_1_HWARN RTE_BIT32(5) 76 #define SFF_8636_RX_PWR_1_LWARN RTE_BIT32(4) 77 #define SFF_8636_RX_PWR_2_HALARM RTE_BIT32(3) 78 #define SFF_8636_RX_PWR_2_LALARM RTE_BIT32(2) 79 #define SFF_8636_RX_PWR_2_HWARN RTE_BIT32(1) 80 #define SFF_8636_RX_PWR_2_LWARN RTE_BIT32(0) 81 82 #define SFF_8636_RX_PWR_34_AW_OFFSET 0x0A 83 #define SFF_8636_RX_PWR_3_HALARM RTE_BIT32(7) 84 #define SFF_8636_RX_PWR_3_LALARM RTE_BIT32(6) 85 #define SFF_8636_RX_PWR_3_HWARN RTE_BIT32(5) 86 #define SFF_8636_RX_PWR_3_LWARN RTE_BIT32(4) 87 #define SFF_8636_RX_PWR_4_HALARM RTE_BIT32(3) 88 #define SFF_8636_RX_PWR_4_LALARM RTE_BIT32(2) 89 #define SFF_8636_RX_PWR_4_HWARN RTE_BIT32(1) 90 #define SFF_8636_RX_PWR_4_LWARN RTE_BIT32(0) 91 92 #define SFF_8636_TX_BIAS_12_AW_OFFSET 0x0B 93 #define SFF_8636_TX_BIAS_1_HALARM RTE_BIT32(7) 94 #define SFF_8636_TX_BIAS_1_LALARM RTE_BIT32(6) 95 #define SFF_8636_TX_BIAS_1_HWARN RTE_BIT32(5) 96 #define SFF_8636_TX_BIAS_1_LWARN RTE_BIT32(4) 97 #define SFF_8636_TX_BIAS_2_HALARM RTE_BIT32(3) 98 #define SFF_8636_TX_BIAS_2_LALARM RTE_BIT32(2) 99 #define SFF_8636_TX_BIAS_2_HWARN RTE_BIT32(1) 100 #define SFF_8636_TX_BIAS_2_LWARN RTE_BIT32(0) 101 102 #define SFF_8636_TX_BIAS_34_AW_OFFSET 0xC 103 #define SFF_8636_TX_BIAS_3_HALARM RTE_BIT32(7) 104 #define SFF_8636_TX_BIAS_3_LALARM RTE_BIT32(6) 105 #define SFF_8636_TX_BIAS_3_HWARN RTE_BIT32(5) 106 #define SFF_8636_TX_BIAS_3_LWARN RTE_BIT32(4) 107 #define SFF_8636_TX_BIAS_4_HALARM RTE_BIT32(3) 108 #define SFF_8636_TX_BIAS_4_LALARM RTE_BIT32(2) 109 #define SFF_8636_TX_BIAS_4_HWARN RTE_BIT32(1) 110 #define SFF_8636_TX_BIAS_4_LWARN RTE_BIT32(0) 111 112 #define SFF_8636_TX_PWR_12_AW_OFFSET 0x0D 113 #define SFF_8636_TX_PWR_1_HALARM RTE_BIT32(7) 114 #define SFF_8636_TX_PWR_1_LALARM RTE_BIT32(6) 115 #define SFF_8636_TX_PWR_1_HWARN RTE_BIT32(5) 116 #define SFF_8636_TX_PWR_1_LWARN RTE_BIT32(4) 117 #define SFF_8636_TX_PWR_2_HALARM RTE_BIT32(3) 118 #define SFF_8636_TX_PWR_2_LALARM RTE_BIT32(2) 119 #define SFF_8636_TX_PWR_2_HWARN RTE_BIT32(1) 120 #define SFF_8636_TX_PWR_2_LWARN RTE_BIT32(0) 121 122 #define SFF_8636_TX_PWR_34_AW_OFFSET 0x0E 123 #define SFF_8636_TX_PWR_3_HALARM RTE_BIT32(7) 124 #define SFF_8636_TX_PWR_3_LALARM RTE_BIT32(6) 125 #define SFF_8636_TX_PWR_3_HWARN RTE_BIT32(5) 126 #define SFF_8636_TX_PWR_3_LWARN RTE_BIT32(4) 127 #define SFF_8636_TX_PWR_4_HALARM RTE_BIT32(3) 128 #define SFF_8636_TX_PWR_4_LALARM RTE_BIT32(2) 129 #define SFF_8636_TX_PWR_4_HWARN RTE_BIT32(1) 130 #define SFF_8636_TX_PWR_4_LWARN RTE_BIT32(0) 131 132 /* Module Monitoring Values - 22-33 */ 133 #define SFF_8636_TEMP_CURR 0x16 134 #define SFF_8636_TEMP_MSB_OFFSET 0x16 135 #define SFF_8636_TEMP_LSB_OFFSET 0x17 136 137 #define SFF_8636_VCC_CURR 0x1A 138 #define SFF_8636_VCC_MSB_OFFSET 0x1A 139 #define SFF_8636_VCC_LSB_OFFSET 0x1B 140 141 /* Channel Monitoring Values - 34-81 */ 142 #define SFF_8636_RX_PWR_1_OFFSET 0x22 143 #define SFF_8636_RX_PWR_2_OFFSET 0x24 144 #define SFF_8636_RX_PWR_3_OFFSET 0x26 145 #define SFF_8636_RX_PWR_4_OFFSET 0x28 146 147 #define SFF_8636_TX_BIAS_1_OFFSET 0x2A 148 #define SFF_8636_TX_BIAS_2_OFFSET 0x2C 149 #define SFF_8636_TX_BIAS_3_OFFSET 0x2E 150 #define SFF_8636_TX_BIAS_4_OFFSET 0x30 151 152 #define SFF_8636_TX_PWR_1_OFFSET 0x32 153 #define SFF_8636_TX_PWR_2_OFFSET 0x34 154 #define SFF_8636_TX_PWR_3_OFFSET 0x36 155 #define SFF_8636_TX_PWR_4_OFFSET 0x38 156 157 /* Control Bytes - 86 - 99 */ 158 #define SFF_8636_TX_DISABLE_OFFSET 0x56 159 #define SFF_8636_TX_DISABLE_4 RTE_BIT32(3) 160 #define SFF_8636_TX_DISABLE_3 RTE_BIT32(2) 161 #define SFF_8636_TX_DISABLE_2 RTE_BIT32(1) 162 #define SFF_8636_TX_DISABLE_1 RTE_BIT32(0) 163 164 #define SFF_8636_RX_RATE_SELECT_OFFSET 0x57 165 #define SFF_8636_RX_RATE_SELECT_4_MASK (3 << 6) 166 #define SFF_8636_RX_RATE_SELECT_3_MASK (3 << 4) 167 #define SFF_8636_RX_RATE_SELECT_2_MASK (3 << 2) 168 #define SFF_8636_RX_RATE_SELECT_1_MASK (3 << 0) 169 170 #define SFF_8636_TX_RATE_SELECT_OFFSET 0x58 171 #define SFF_8636_TX_RATE_SELECT_4_MASK (3 << 6) 172 #define SFF_8636_TX_RATE_SELECT_3_MASK (3 << 4) 173 #define SFF_8636_TX_RATE_SELECT_2_MASK (3 << 2) 174 #define SFF_8636_TX_RATE_SELECT_1_MASK (3 << 0) 175 176 #define SFF_8636_RX_APP_SELECT_4_OFFSET 0x58 177 #define SFF_8636_RX_APP_SELECT_3_OFFSET 0x59 178 #define SFF_8636_RX_APP_SELECT_2_OFFSET 0x5A 179 #define SFF_8636_RX_APP_SELECT_1_OFFSET 0x5B 180 181 #define SFF_8636_PWR_MODE_OFFSET 0x5D 182 #define SFF_8636_HIGH_PWR_ENABLE RTE_BIT32(2) 183 #define SFF_8636_LOW_PWR_MODE RTE_BIT32(1) 184 #define SFF_8636_PWR_OVERRIDE RTE_BIT32(0) 185 186 #define SFF_8636_TX_APP_SELECT_4_OFFSET 0x5E 187 #define SFF_8636_TX_APP_SELECT_3_OFFSET 0x5F 188 #define SFF_8636_TX_APP_SELECT_2_OFFSET 0x60 189 #define SFF_8636_TX_APP_SELECT_1_OFFSET 0x61 190 191 #define SFF_8636_LOS_MASK_OFFSET 0x64 192 #define SFF_8636_TX_LOS_4_MASK RTE_BIT32(7) 193 #define SFF_8636_TX_LOS_3_MASK RTE_BIT32(6) 194 #define SFF_8636_TX_LOS_2_MASK RTE_BIT32(5) 195 #define SFF_8636_TX_LOS_1_MASK RTE_BIT32(4) 196 #define SFF_8636_RX_LOS_4_MASK RTE_BIT32(3) 197 #define SFF_8636_RX_LOS_3_MASK RTE_BIT32(2) 198 #define SFF_8636_RX_LOS_2_MASK RTE_BIT32(1) 199 #define SFF_8636_RX_LOS_1_MASK RTE_BIT32(0) 200 201 #define SFF_8636_FAULT_MASK_OFFSET 0x65 202 #define SFF_8636_TX_FAULT_1_MASK RTE_BIT32(3) 203 #define SFF_8636_TX_FAULT_2_MASK RTE_BIT32(2) 204 #define SFF_8636_TX_FAULT_3_MASK RTE_BIT32(1) 205 #define SFF_8636_TX_FAULT_4_MASK RTE_BIT32(0) 206 207 #define SFF_8636_TEMP_MASK_OFFSET 0x67 208 #define SFF_8636_TEMP_HALARM_MASK RTE_BIT32(7) 209 #define SFF_8636_TEMP_LALARM_MASK RTE_BIT32(6) 210 #define SFF_8636_TEMP_HWARN_MASK RTE_BIT32(5) 211 #define SFF_8636_TEMP_LWARN_MASK RTE_BIT32(4) 212 213 #define SFF_8636_VCC_MASK_OFFSET 0x68 214 #define SFF_8636_VCC_HALARM_MASK RTE_BIT32(7) 215 #define SFF_8636_VCC_LALARM_MASK RTE_BIT32(6) 216 #define SFF_8636_VCC_HWARN_MASK RTE_BIT32(5) 217 #define SFF_8636_VCC_LWARN_MASK RTE_BIT32(4) 218 219 /*------------------------------------------------------------------------------ 220 * 221 * Upper Memory Page 00h 222 * Serial ID - Base ID, Extended ID and Vendor Specific ID fields 223 */ 224 /* Identifier - 128 */ 225 /* Identifier values same as Lower Memory Page 00h */ 226 #define SFF_8636_UPPER_PAGE_0_ID_OFFSET 0x80 227 228 /* Extended Identifier - 128 */ 229 #define SFF_8636_EXT_ID_OFFSET 0x81 230 #define SFF_8636_EXT_ID_PWR_CLASS_MASK 0xC0 231 #define SFF_8636_EXT_ID_PWR_CLASS_1 (0 << 6) 232 #define SFF_8636_EXT_ID_PWR_CLASS_2 (1 << 6) 233 #define SFF_8636_EXT_ID_PWR_CLASS_3 (2 << 6) 234 #define SFF_8636_EXT_ID_PWR_CLASS_4 (3 << 6) 235 #define SFF_8636_EXT_ID_CLIE_MASK 0x10 236 #define SFF_8636_EXT_ID_CLIEI_CODE_PRESENT (1 << 4) 237 #define SFF_8636_EXT_ID_CDR_TX_MASK 0x08 238 #define SFF_8636_EXT_ID_CDR_TX_PRESENT (1 << 3) 239 #define SFF_8636_EXT_ID_CDR_RX_MASK 0x04 240 #define SFF_8636_EXT_ID_CDR_RX_PRESENT (1 << 2) 241 #define SFF_8636_EXT_ID_EPWR_CLASS_MASK 0x03 242 #define SFF_8636_EXT_ID_PWR_CLASS_LEGACY 0 243 #define SFF_8636_EXT_ID_PWR_CLASS_5 1 244 #define SFF_8636_EXT_ID_PWR_CLASS_6 2 245 #define SFF_8636_EXT_ID_PWR_CLASS_7 3 246 247 /* Connector Values offset - 130 */ 248 /* Values are defined under SFF_8024_CTOR */ 249 #define SFF_8636_CTOR_OFFSET 0x82 250 #define SFF_8636_CTOR_UNKNOWN 0x00 251 #define SFF_8636_CTOR_SC 0x01 252 #define SFF_8636_CTOR_FC_STYLE_1 0x02 253 #define SFF_8636_CTOR_FC_STYLE_2 0x03 254 #define SFF_8636_CTOR_BNC_TNC 0x04 255 #define SFF_8636_CTOR_FC_COAX 0x05 256 #define SFF_8636_CTOR_FIBER_JACK 0x06 257 #define SFF_8636_CTOR_LC 0x07 258 #define SFF_8636_CTOR_MT_RJ 0x08 259 #define SFF_8636_CTOR_MU 0x09 260 #define SFF_8636_CTOR_SG 0x0A 261 #define SFF_8636_CTOR_OPT_PT 0x0B 262 #define SFF_8636_CTOR_MPO 0x0C 263 /* 0D-1Fh --- Reserved */ 264 #define SFF_8636_CTOR_HSDC_II 0x20 265 #define SFF_8636_CTOR_COPPER_PT 0x21 266 #define SFF_8636_CTOR_RJ45 0x22 267 #define SFF_8636_CTOR_NO_SEPARABLE 0x23 268 #define SFF_8636_CTOR_MXC_2X16 0x24 269 270 /* Specification Compliance - 131-138 */ 271 /* Ethernet Compliance Codes - 131 */ 272 #define SFF_8636_ETHERNET_COMP_OFFSET 0x83 273 #define SFF_8636_ETHERNET_RSRVD RTE_BIT32(7) 274 #define SFF_8636_ETHERNET_10G_LRM RTE_BIT32(6) 275 #define SFF_8636_ETHERNET_10G_LR RTE_BIT32(5) 276 #define SFF_8636_ETHERNET_10G_SR RTE_BIT32(4) 277 #define SFF_8636_ETHERNET_40G_CR4 RTE_BIT32(3) 278 #define SFF_8636_ETHERNET_40G_SR4 RTE_BIT32(2) 279 #define SFF_8636_ETHERNET_40G_LR4 RTE_BIT32(1) 280 #define SFF_8636_ETHERNET_40G_ACTIVE RTE_BIT32(0) 281 282 /* SONET Compliance Codes - 132 */ 283 #define SFF_8636_SONET_COMP_OFFSET 0x84 284 #define SFF_8636_SONET_40G_OTN RTE_BIT32(3) 285 #define SFF_8636_SONET_OC48_LR RTE_BIT32(2) 286 #define SFF_8636_SONET_OC48_IR RTE_BIT32(1) 287 #define SFF_8636_SONET_OC48_SR RTE_BIT32(0) 288 289 /* SAS/SATA Complaince Codes - 133 */ 290 #define SFF_8636_SAS_COMP_OFFSET 0x85 291 #define SFF_8636_SAS_12G RTE_BIT32(6) 292 #define SFF_8636_SAS_6G RTE_BIT32(5) 293 #define SFF_8636_SAS_3G RTE_BIT32(4) 294 295 /* Gigabit Ethernet Compliance Codes - 134 */ 296 #define SFF_8636_GIGE_COMP_OFFSET 0x86 297 #define SFF_8636_GIGE_1000_BASE_T RTE_BIT32(3) 298 #define SFF_8636_GIGE_1000_BASE_CX RTE_BIT32(2) 299 #define SFF_8636_GIGE_1000_BASE_LX RTE_BIT32(1) 300 #define SFF_8636_GIGE_1000_BASE_SX RTE_BIT32(0) 301 302 /* Fibre Channel Link length/Transmitter Tech. - 135,136 */ 303 #define SFF_8636_FC_LEN_OFFSET 0x87 304 #define SFF_8636_FC_LEN_VERY_LONG RTE_BIT32(7) 305 #define SFF_8636_FC_LEN_SHORT RTE_BIT32(6) 306 #define SFF_8636_FC_LEN_INT RTE_BIT32(5) 307 #define SFF_8636_FC_LEN_LONG RTE_BIT32(4) 308 #define SFF_8636_FC_LEN_MED RTE_BIT32(3) 309 #define SFF_8636_FC_TECH_LONG_LC RTE_BIT32(1) 310 #define SFF_8636_FC_TECH_ELEC_INTER RTE_BIT32(0) 311 312 #define SFF_8636_FC_TECH_OFFSET 0x88 313 #define SFF_8636_FC_TECH_ELEC_INTRA RTE_BIT32(7) 314 #define SFF_8636_FC_TECH_SHORT_WO_OFC RTE_BIT32(6) 315 #define SFF_8636_FC_TECH_SHORT_W_OFC RTE_BIT32(5) 316 #define SFF_8636_FC_TECH_LONG_LL RTE_BIT32(4) 317 318 /* Fibre Channel Transmitter Media - 137 */ 319 #define SFF_8636_FC_TRANS_MEDIA_OFFSET 0x89 320 /* Twin Axial Pair */ 321 #define SFF_8636_FC_TRANS_MEDIA_TW RTE_BIT32(7) 322 /* Shielded Twisted Pair */ 323 #define SFF_8636_FC_TRANS_MEDIA_TP RTE_BIT32(6) 324 /* Miniature Coax */ 325 #define SFF_8636_FC_TRANS_MEDIA_MI RTE_BIT32(5) 326 /* Video Coax */ 327 #define SFF_8636_FC_TRANS_MEDIA_TV RTE_BIT32(4) 328 /* Multi-mode 62.5m */ 329 #define SFF_8636_FC_TRANS_MEDIA_M6 RTE_BIT32(3) 330 /* Multi-mode 50m */ 331 #define SFF_8636_FC_TRANS_MEDIA_M5 RTE_BIT32(2) 332 /* Multi-mode 50um */ 333 #define SFF_8636_FC_TRANS_MEDIA_OM3 RTE_BIT32(1) 334 /* Single Mode */ 335 #define SFF_8636_FC_TRANS_MEDIA_SM RTE_BIT32(0) 336 337 /* Fibre Channel Speed - 138 */ 338 #define SFF_8636_FC_SPEED_OFFSET 0x8A 339 #define SFF_8636_FC_SPEED_1200_MBPS RTE_BIT32(7) 340 #define SFF_8636_FC_SPEED_800_MBPS RTE_BIT32(6) 341 #define SFF_8636_FC_SPEED_1600_MBPS RTE_BIT32(5) 342 #define SFF_8636_FC_SPEED_400_MBPS RTE_BIT32(4) 343 #define SFF_8636_FC_SPEED_200_MBPS RTE_BIT32(2) 344 #define SFF_8636_FC_SPEED_100_MBPS RTE_BIT32(0) 345 346 /* Encoding - 139 */ 347 /* Values are defined under SFF_8024_ENCODING */ 348 #define SFF_8636_ENCODING_OFFSET 0x8B 349 #define SFF_8636_ENCODING_MANCHESTER 0x06 350 #define SFF_8636_ENCODING_64B66B 0x05 351 #define SFF_8636_ENCODING_SONET 0x04 352 #define SFF_8636_ENCODING_NRZ 0x03 353 #define SFF_8636_ENCODING_4B5B 0x02 354 #define SFF_8636_ENCODING_8B10B 0x01 355 #define SFF_8636_ENCODING_UNSPEC 0x00 356 357 /* BR, Nominal - 140 */ 358 #define SFF_8636_BR_NOMINAL_OFFSET 0x8C 359 360 /* Extended RateSelect - 141 */ 361 #define SFF_8636_EXT_RS_OFFSET 0x8D 362 #define SFF_8636_EXT_RS_V1 RTE_BIT32(0) 363 364 /* Length (Standard SM Fiber)-km - 142 */ 365 #define SFF_8636_SM_LEN_OFFSET 0x8E 366 367 /* Length (OM3)-Unit 2m - 143 */ 368 #define SFF_8636_OM3_LEN_OFFSET 0x8F 369 370 /* Length (OM2)-Unit 1m - 144 */ 371 #define SFF_8636_OM2_LEN_OFFSET 0x90 372 373 /* Length (OM1)-Unit 1m - 145 */ 374 #define SFF_8636_OM1_LEN_OFFSET 0x91 375 376 /* Cable Assembly Length -Unit 1m - 146 */ 377 #define SFF_8636_CBL_LEN_OFFSET 0x92 378 379 /* Device Technology - 147 */ 380 #define SFF_8636_DEVICE_TECH_OFFSET 0x93 381 /* Transmitter Technology */ 382 #define SFF_8636_TRANS_TECH_MASK 0xF0 383 /* Copper cable, linear active equalizers */ 384 #define SFF_8636_TRANS_COPPER_LNR_EQUAL (15 << 4) 385 /* Copper cable, near end limiting active equalizers */ 386 #define SFF_8636_TRANS_COPPER_NEAR_EQUAL (14 << 4) 387 /* Copper cable, far end limiting active equalizers */ 388 #define SFF_8636_TRANS_COPPER_FAR_EQUAL (13 << 4) 389 /* Copper cable, near & far end limiting active equalizers */ 390 #define SFF_8636_TRANS_COPPER_LNR_FAR_EQUAL (12 << 4) 391 /* Copper cable, passive equalized */ 392 #define SFF_8636_TRANS_COPPER_PAS_EQUAL (11 << 4) 393 /* Copper cable, unequalized */ 394 #define SFF_8636_TRANS_COPPER_PAS_UNEQUAL (10 << 4) 395 /* 1490 nm DFB */ 396 #define SFF_8636_TRANS_1490_DFB (9 << 4) 397 /* Others */ 398 #define SFF_8636_TRANS_OTHERS (8 << 4) 399 /* 1550 nm EML */ 400 #define SFF_8636_TRANS_1550_EML (7 << 4) 401 /* 1310 nm EML */ 402 #define SFF_8636_TRANS_1310_EML (6 << 4) 403 /* 1550 nm DFB */ 404 #define SFF_8636_TRANS_1550_DFB (5 << 4) 405 /* 1310 nm DFB */ 406 #define SFF_8636_TRANS_1310_DFB (4 << 4) 407 /* 1310 nm FP */ 408 #define SFF_8636_TRANS_1310_FP (3 << 4) 409 /* 1550 nm VCSEL */ 410 #define SFF_8636_TRANS_1550_VCSEL (2 << 4) 411 /* 1310 nm VCSEL */ 412 #define SFF_8636_TRANS_1310_VCSEL (1 << 4) 413 /* 850 nm VCSEL */ 414 #define SFF_8636_TRANS_850_VCSEL (0 << 4) 415 416 /* Active/No wavelength control */ 417 #define SFF_8636_DEV_TECH_ACTIVE_WAVE_LEN RTE_BIT32(3) 418 /* Cooled transmitter */ 419 #define SFF_8636_DEV_TECH_COOL_TRANS RTE_BIT32(2) 420 /* APD/Pin Detector */ 421 #define SFF_8636_DEV_TECH_APD_DETECTOR RTE_BIT32(1) 422 /* Transmitter tunable */ 423 #define SFF_8636_DEV_TECH_TUNABLE RTE_BIT32(0) 424 425 /* Vendor Name - 148-163 */ 426 #define SFF_8636_VENDOR_NAME_START_OFFSET 0x94 427 #define SFF_8636_VENDOR_NAME_END_OFFSET 0xA3 428 429 /* Extended Module Codes - 164 */ 430 #define SFF_8636_EXT_MOD_CODE_OFFSET 0xA4 431 #define SFF_8636_EXT_MOD_INFINIBAND_EDR RTE_BIT32(4) 432 #define SFF_8636_EXT_MOD_INFINIBAND_FDR RTE_BIT32(3) 433 #define SFF_8636_EXT_MOD_INFINIBAND_QDR RTE_BIT32(2) 434 #define SFF_8636_EXT_MOD_INFINIBAND_DDR RTE_BIT32(1) 435 #define SFF_8636_EXT_MOD_INFINIBAND_SDR RTE_BIT32(0) 436 437 /* Vendor OUI - 165-167 */ 438 #define SFF_8636_VENDOR_OUI_OFFSET 0xA5 439 #define SFF_8636_VENDOR_OUI_LEN 3 440 441 /* Vendor OUI - 165-167 */ 442 #define SFF_8636_VENDOR_PN_START_OFFSET 0xA8 443 #define SFF_8636_VENDOR_PN_END_OFFSET 0xB7 444 445 /* Vendor Revision - 184-185 */ 446 #define SFF_8636_VENDOR_REV_START_OFFSET 0xB8 447 #define SFF_8636_VENDOR_REV_END_OFFSET 0xB9 448 449 /* Wavelength - 186-187 */ 450 #define SFF_8636_WAVELEN_HIGH_BYTE_OFFSET 0xBA 451 #define SFF_8636_WAVELEN_LOW_BYTE_OFFSET 0xBB 452 453 /* Wavelength Tolerance- 188-189 */ 454 #define SFF_8636_WAVE_TOL_HIGH_BYTE_OFFSET 0xBC 455 #define SFF_8636_WAVE_TOL_LOW_BYTE_OFFSET 0xBD 456 457 /* Max case temp - Other than 70 C - 190 */ 458 #define SFF_8636_MAXCASE_TEMP_OFFSET 0xBE 459 460 /* CC_BASE - 191 */ 461 #define SFF_8636_CC_BASE_OFFSET 0xBF 462 463 /* Option Values - 192-195 */ 464 #define SFF_8636_OPTION_1_OFFSET 0xC0 465 #define SFF_8636_ETHERNET_UNSPECIFIED 0x00 466 #define SFF_8636_ETHERNET_100G_AOC 0x01 467 #define SFF_8636_ETHERNET_100G_SR4 0x02 468 #define SFF_8636_ETHERNET_100G_LR4 0x03 469 #define SFF_8636_ETHERNET_100G_ER4 0x04 470 #define SFF_8636_ETHERNET_100G_SR10 0x05 471 #define SFF_8636_ETHERNET_100G_CWDM4_FEC 0x06 472 #define SFF_8636_ETHERNET_100G_PSM4 0x07 473 #define SFF_8636_ETHERNET_100G_ACC 0x08 474 #define SFF_8636_ETHERNET_100G_CWDM4_NO_FEC 0x09 475 #define SFF_8636_ETHERNET_100G_RSVD1 0x0A 476 #define SFF_8636_ETHERNET_100G_CR4 0x0B 477 #define SFF_8636_ETHERNET_25G_CR_CA_S 0x0C 478 #define SFF_8636_ETHERNET_25G_CR_CA_N 0x0D 479 #define SFF_8636_ETHERNET_40G_ER4 0x10 480 #define SFF_8636_ETHERNET_4X10_SR 0x11 481 #define SFF_8636_ETHERNET_40G_PSM4 0x12 482 #define SFF_8636_ETHERNET_G959_P1I1_2D1 0x13 483 #define SFF_8636_ETHERNET_G959_P1S1_2D2 0x14 484 #define SFF_8636_ETHERNET_G959_P1L1_2D2 0x15 485 #define SFF_8636_ETHERNET_10GT_SFI 0x16 486 #define SFF_8636_ETHERNET_100G_CLR4 0x17 487 #define SFF_8636_ETHERNET_100G_AOC2 0x18 488 #define SFF_8636_ETHERNET_100G_ACC2 0x19 489 490 #define SFF_8636_OPTION_2_OFFSET 0xC1 491 /* Rx output amplitude */ 492 #define SFF_8636_O2_RX_OUTPUT_AMP RTE_BIT32(0) 493 #define SFF_8636_OPTION_3_OFFSET 0xC2 494 /* Rx Squelch Disable */ 495 #define SFF_8636_O3_RX_SQL_DSBL RTE_BIT32(3) 496 /* Rx Output Disable capable */ 497 #define SFF_8636_O3_RX_OUTPUT_DSBL RTE_BIT32(2) 498 /* Tx Squelch Disable */ 499 #define SFF_8636_O3_TX_SQL_DSBL RTE_BIT32(1) 500 /* Tx Squelch Impl */ 501 #define SFF_8636_O3_TX_SQL_IMPL RTE_BIT32(0) 502 #define SFF_8636_OPTION_4_OFFSET 0xC3 503 /* Memory Page 02 present */ 504 #define SFF_8636_O4_PAGE_02_PRESENT RTE_BIT32(7) 505 /* Memory Page 01 present */ 506 #define SFF_8636_O4_PAGE_01_PRESENT RTE_BIT32(6) 507 /* Rate Select implemented */ 508 #define SFF_8636_O4_RATE_SELECT RTE_BIT32(5) 509 /* Tx_DISABLE implemented */ 510 #define SFF_8636_O4_TX_DISABLE RTE_BIT32(4) 511 /* Tx_FAULT implemented */ 512 #define SFF_8636_O4_TX_FAULT RTE_BIT32(3) 513 /* Tx Squelch implemented */ 514 #define SFF_8636_O4_TX_SQUELCH RTE_BIT32(2) 515 /* Tx Loss of Signal */ 516 #define SFF_8636_O4_TX_LOS RTE_BIT32(1) 517 518 /* Vendor SN - 196-211 */ 519 #define SFF_8636_VENDOR_SN_START_OFFSET 0xC4 520 #define SFF_8636_VENDOR_SN_END_OFFSET 0xD3 521 522 /* Vendor Date - 212-219 */ 523 #define SFF_8636_DATE_YEAR_OFFSET 0xD4 524 #define SFF_8636_DATE_YEAR_LEN 2 525 #define SFF_8636_DATE_MONTH_OFFSET 0xD6 526 #define SFF_8636_DATE_MONTH_LEN 2 527 #define SFF_8636_DATE_DAY_OFFSET 0xD8 528 #define SFF_8636_DATE_DAY_LEN 2 529 #define SFF_8636_DATE_VENDOR_LOT_OFFSET 0xDA 530 #define SFF_8636_DATE_VENDOR_LOT_LEN 2 531 532 /* Diagnostic Monitoring Type - 220 */ 533 #define SFF_8636_DIAG_TYPE_OFFSET 0xDC 534 #define SFF_8636_RX_PWR_TYPE_MASK 0x8 535 #define SFF_8636_RX_PWR_TYPE_AVG_PWR RTE_BIT32(3) 536 #define SFF_8636_RX_PWR_TYPE_OMA (0 << 3) 537 #define SFF_8636_TX_PWR_TYPE_MASK 0x4 538 #define SFF_8636_TX_PWR_TYPE_AVG_PWR RTE_BIT32(2) 539 540 /* Enhanced Options - 221 */ 541 #define SFF_8636_ENH_OPTIONS_OFFSET 0xDD 542 #define SFF_8636_RATE_SELECT_EXT_SUPPORT RTE_BIT32(3) 543 #define SFF_8636_RATE_SELECT_APP_TABLE_SUPPORT RTE_BIT32(2) 544 545 /* Check code - 223 */ 546 #define SFF_8636_CC_EXT_OFFSET 0xDF 547 #define SFF_8636_CC_EXT_LEN 1 548 549 /*------------------------------------------------------------------------------ 550 * 551 * Upper Memory Page 03h 552 * Contains module thresholds, channel thresholds and masks, 553 * and optional channel controls 554 * 555 * Offset - Page Num(3) * PageSize(0x80) + Page offset 556 */ 557 558 /* Module Thresholds (48 Bytes) 128-175 */ 559 /* MSB at low address, LSB at high address */ 560 #define SFF_8636_TEMP_HALRM 0x200 561 #define SFF_8636_TEMP_LALRM 0x202 562 #define SFF_8636_TEMP_HWARN 0x204 563 #define SFF_8636_TEMP_LWARN 0x206 564 565 #define SFF_8636_VCC_HALRM 0x210 566 #define SFF_8636_VCC_LALRM 0x212 567 #define SFF_8636_VCC_HWARN 0x214 568 #define SFF_8636_VCC_LWARN 0x216 569 570 #define SFF_8636_RX_PWR_HALRM 0x230 571 #define SFF_8636_RX_PWR_LALRM 0x232 572 #define SFF_8636_RX_PWR_HWARN 0x234 573 #define SFF_8636_RX_PWR_LWARN 0x236 574 575 #define SFF_8636_TX_BIAS_HALRM 0x238 576 #define SFF_8636_TX_BIAS_LALRM 0x23A 577 #define SFF_8636_TX_BIAS_HWARN 0x23C 578 #define SFF_8636_TX_BIAS_LWARN 0x23E 579 580 #define SFF_8636_TX_PWR_HALRM 0x240 581 #define SFF_8636_TX_PWR_LALRM 0x242 582 #define SFF_8636_TX_PWR_HWARN 0x244 583 #define SFF_8636_TX_PWR_LWARN 0x246 584 585 #define ETH_MODULE_SFF_8636_MAX_LEN 640 586 #define ETH_MODULE_SFF_8436_MAX_LEN 640 587 588 #endif /* _SFF_8636_H_ */ 589