xref: /dpdk/lib/eal/loongarch/rte_cycles.c (revision 29631ee5c8906aba039c26d092137b09dbc949d8)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2022 Loongson Technology Corporation Limited
3  */
4 
5 #include "eal_private.h"
6 
7 #define LOONGARCH_CPUCFG4	0x4
8 #define CPUCFG4_CCFREQ_MASK	0xFFFFFFFF
9 #define CPUCFG4_CCFREQ_SHIFT	0
10 
11 #define LOONGARCH_CPUCFG5	0x5
12 #define CPUCFG5_CCMUL_MASK	0xFFFF
13 #define CPUCFG5_CCMUL_SHIFT	0
14 
15 #define CPUCFG5_CCDIV_MASK	0xFFFF0000
16 #define CPUCFG5_CCDIV_SHIFT	16
17 
18 static __rte_noinline uint32_t
read_cpucfg(int arg)19 read_cpucfg(int arg)
20 {
21 	int ret = 0;
22 
23 	__asm__ __volatile__ (
24 		"cpucfg %[var], %[index]\n"
25 		: [var]"=r"(ret)
26 		: [index]"r"(arg)
27 		:
28 		);
29 
30 	return ret;
31 }
32 
33 uint64_t
get_tsc_freq_arch(void)34 get_tsc_freq_arch(void)
35 {
36 	uint32_t base_freq, mul_factor, div_factor;
37 
38 	base_freq = read_cpucfg(LOONGARCH_CPUCFG4);
39 	mul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >>
40 		CPUCFG5_CCMUL_SHIFT;
41 	div_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >>
42 		CPUCFG5_CCDIV_SHIFT;
43 
44 	return base_freq * mul_factor / div_factor;
45 }
46