1*5f7de255SJasvinder Singh; SPDX-License-Identifier: BSD-3-Clause 2*5f7de255SJasvinder Singh; Copyright(c) 2010-2018 Intel Corporation 3*5f7de255SJasvinder Singh 4*5f7de255SJasvinder Singh; _______________ 5*5f7de255SJasvinder Singh; LINK0 RXQ0 --->| |---> LINK0 TXQ0 6*5f7de255SJasvinder Singh; | | 7*5f7de255SJasvinder Singh; LINK1 RXQ0 --->| |---> LINK1 TXQ0 8*5f7de255SJasvinder Singh; | Routing | 9*5f7de255SJasvinder Singh; LINK2 RXQ0 --->| |---> LINK2 TXQ0 10*5f7de255SJasvinder Singh; | | 11*5f7de255SJasvinder Singh; LINK3 RXQ0 --->| |---> LINK3 TXQ0 12*5f7de255SJasvinder Singh; |_______________| 13*5f7de255SJasvinder Singh; | 14*5f7de255SJasvinder Singh; +-----------> SINK0 (route miss) 15*5f7de255SJasvinder Singh; 16*5f7de255SJasvinder Singh; Input packet: Ethernet/IPv4 17*5f7de255SJasvinder Singh; 18*5f7de255SJasvinder Singh; Packet buffer layout: 19*5f7de255SJasvinder Singh; # Field Name Offset (Bytes) Size (Bytes) 20*5f7de255SJasvinder Singh; 0 Mbuf 0 128 21*5f7de255SJasvinder Singh; 1 Headroom 128 128 22*5f7de255SJasvinder Singh; 2 Ethernet header 256 14 23*5f7de255SJasvinder Singh; 3 IPv4 header 270 20 24*5f7de255SJasvinder Singh 25*5f7de255SJasvinder Singhmempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 26*5f7de255SJasvinder Singh 27*5f7de255SJasvinder Singhlink LINK0 dev 0000:02:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 28*5f7de255SJasvinder Singhlink LINK1 dev 0000:02:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 29*5f7de255SJasvinder Singhlink LINK2 dev 0000:06:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 30*5f7de255SJasvinder Singhlink LINK3 dev 0000:06:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 31*5f7de255SJasvinder Singh 32*5f7de255SJasvinder Singhtable action profile AP0 ipv4 offset 270 fwd encap ether 33*5f7de255SJasvinder Singh 34*5f7de255SJasvinder Singhpipeline PIPELINE0 period 10 offset_port_id 0 cpu 0 35*5f7de255SJasvinder Singh 36*5f7de255SJasvinder Singhpipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0 37*5f7de255SJasvinder Singhpipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0 38*5f7de255SJasvinder Singhpipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0 39*5f7de255SJasvinder Singhpipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0 40*5f7de255SJasvinder Singh 41*5f7de255SJasvinder Singhpipeline PIPELINE0 port out bsz 32 link LINK0 txq 0 42*5f7de255SJasvinder Singhpipeline PIPELINE0 port out bsz 32 link LINK1 txq 0 43*5f7de255SJasvinder Singhpipeline PIPELINE0 port out bsz 32 link LINK2 txq 0 44*5f7de255SJasvinder Singhpipeline PIPELINE0 port out bsz 32 link LINK3 txq 0 45*5f7de255SJasvinder Singhpipeline PIPELINE0 port out bsz 32 sink 46*5f7de255SJasvinder Singh 47*5f7de255SJasvinder Singhpipeline PIPELINE0 table match lpm ipv4 offset 286 size 4K action AP0 48*5f7de255SJasvinder Singh 49*5f7de255SJasvinder Singhpipeline PIPELINE0 port in 0 table 0 50*5f7de255SJasvinder Singhpipeline PIPELINE0 port in 1 table 0 51*5f7de255SJasvinder Singhpipeline PIPELINE0 port in 2 table 0 52*5f7de255SJasvinder Singhpipeline PIPELINE0 port in 3 table 0 53*5f7de255SJasvinder Singh 54*5f7de255SJasvinder Singhthread 1 pipeline PIPELINE0 enable 55*5f7de255SJasvinder Singh 56*5f7de255SJasvinder Singhpipeline PIPELINE0 table 0 rule add match default action fwd port 4 57*5f7de255SJasvinder Singhpipeline PIPELINE0 table 0 rule add match lpm ipv4 100.0.0.0 10 action fwd port 0 encap ether a0:a1:a2:a3:a4:a5 00:01:02:03:04:05 58*5f7de255SJasvinder Singhpipeline PIPELINE0 table 0 rule add match lpm ipv4 100.64.0.0 10 action fwd port 1 encap ether b0:b1:b2:b3:b4:b5 10:11:12:13:14:15 59*5f7de255SJasvinder Singhpipeline PIPELINE0 table 0 rule add match lpm ipv4 100.128.0.0 10 action fwd port 2 encap ether c0:c1:c2:c3:c4:c5 20:21:22:23:24:25 60*5f7de255SJasvinder Singhpipeline PIPELINE0 table 0 rule add match lpm ipv4 100.192.0.0 10 action fwd port 3 encap ether d0:d1:d2:d3:d4:d5 30:31:32:33:34:35 61