1; SPDX-License-Identifier: BSD-3-Clause 2; Copyright(c) 2010-2018 Intel Corporation 3 4; _______________ 5; LINK0 RXQ0 --->| |---> LINK0 TXQ0 6; | | 7; LINK1 RXQ0 --->| |---> LINK1 TXQ0 8; | Routing | 9; LINK2 RXQ0 --->| |---> LINK2 TXQ0 10; | | 11; LINK3 RXQ0 --->| |---> LINK3 TXQ0 12; |_______________| 13; | 14; +-----------> SINK0 (route miss) 15; 16; Input packet: Ethernet/IPv4 17; 18; Packet buffer layout: 19; # Field Name Offset (Bytes) Size (Bytes) 20; 0 Mbuf 0 128 21; 1 Headroom 128 128 22; 2 Ethernet header 256 14 23; 3 IPv4 header 270 20 24 25mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 26 27link LINK0 dev 0000:02:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 28link LINK1 dev 0000:02:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 29link LINK2 dev 0000:06:00.0 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 30link LINK3 dev 0000:06:00.1 rxq 1 128 MEMPOOL0 txq 1 512 promiscuous on 31 32table action profile AP0 ipv4 offset 270 fwd encap ether 33 34pipeline PIPELINE0 period 10 offset_port_id 0 cpu 0 35 36pipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0 37pipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0 38pipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0 39pipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0 40 41pipeline PIPELINE0 port out bsz 32 link LINK0 txq 0 42pipeline PIPELINE0 port out bsz 32 link LINK1 txq 0 43pipeline PIPELINE0 port out bsz 32 link LINK2 txq 0 44pipeline PIPELINE0 port out bsz 32 link LINK3 txq 0 45pipeline PIPELINE0 port out bsz 32 sink 46 47pipeline PIPELINE0 table match lpm ipv4 offset 286 size 4K action AP0 48 49pipeline PIPELINE0 port in 0 table 0 50pipeline PIPELINE0 port in 1 table 0 51pipeline PIPELINE0 port in 2 table 0 52pipeline PIPELINE0 port in 3 table 0 53 54thread 1 pipeline PIPELINE0 enable 55 56pipeline PIPELINE0 table 0 rule add match default action fwd port 4 57pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.0.0.0 10 action fwd port 0 encap ether a0:a1:a2:a3:a4:a5 00:01:02:03:04:05 58pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.64.0.0 10 action fwd port 1 encap ether b0:b1:b2:b3:b4:b5 10:11:12:13:14:15 59pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.128.0.0 10 action fwd port 2 encap ether c0:c1:c2:c3:c4:c5 20:21:22:23:24:25 60pipeline PIPELINE0 table 0 rule add match lpm ipv4 100.192.0.0 10 action fwd port 3 encap ether d0:d1:d2:d3:d4:d5 30:31:32:33:34:35 61