1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2022 Intel Corporation 3 */ 4 5 #ifndef AFU_PMD_N3000_H 6 #define AFU_PMD_N3000_H 7 8 #include "afu_pmd_core.h" 9 #include "rte_pmd_afu.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 #define N3000_AFU_UUID_L 0xc000c9660d824272 16 #define N3000_AFU_UUID_H 0x9aeffe5f84570612 17 #define N3000_NLB0_UUID_L 0xf89e433683f9040b 18 #define N3000_NLB0_UUID_H 0xd8424dc4a4a3c413 19 #define N3000_DMA_UUID_L 0xa9149a35bace01ea 20 #define N3000_DMA_UUID_H 0xef82def7f6ec40fc 21 22 #define NUM_N3000_DMA 4 23 #define MAX_MSIX_VEC 7 24 25 /* N3000 DFL definition */ 26 #define DFH_UUID_L_OFFSET 8 27 #define DFH_UUID_H_OFFSET 16 28 #define DFH_TYPE(hdr) (((hdr) >> 60) & 0xf) 29 #define DFH_TYPE_AFU 1 30 #define DFH_TYPE_BBB 2 31 #define DFH_TYPE_PRIVATE 3 32 #define DFH_EOL(hdr) (((hdr) >> 40) & 0x1) 33 #define DFH_NEXT_OFFSET(hdr) (((hdr) >> 16) & 0xffffff) 34 #define DFH_FEATURE_ID(hdr) ((hdr) & 0xfff) 35 #define PORT_ATTR_REG(n) (((n) << 3) + 0x38) 36 #define PORT_IMPLEMENTED(attr) (((attr) >> 60) & 0x1) 37 #define PORT_BAR(attr) (((attr) >> 32) & 0x7) 38 #define PORT_OFFSET(attr) ((attr) & 0xffffff) 39 #define PORT_FEATURE_UINT_ID 0x12 40 #define PORT_UINT_CAP_REG 0x8 41 #define PORT_VEC_START(cap) (((cap) >> 12) & 0xfff) 42 #define PORT_VEC_COUNT(cap) ((cap) >> 12 & 0xfff) 43 #define PORT_CTRL_REG 0x38 44 #define PORT_SOFT_RESET (0x1 << 0) 45 46 /* NLB registers definition */ 47 #define CSR_SCRATCHPAD0 0x100 48 #define CSR_SCRATCHPAD1 0x108 49 #define CSR_AFU_DSM_BASEL 0x110 50 #define CSR_AFU_DSM_BASEH 0x114 51 #define CSR_SRC_ADDR 0x120 52 #define CSR_DST_ADDR 0x128 53 #define CSR_NUM_LINES 0x130 54 #define CSR_CTL 0x138 55 #define CSR_CFG 0x140 56 #define CSR_INACT_THRESH 0x148 57 #define CSR_INTERRUPT0 0x150 58 #define CSR_SWTEST_MSG 0x158 59 #define CSR_STATUS0 0x160 60 #define CSR_STATUS1 0x168 61 #define CSR_ERROR 0x170 62 #define CSR_STRIDE 0x178 63 #define CSR_HE_INFO0 0x180 64 65 #define DSM_SIZE 0x200000 66 #define DSM_STATUS 0x40 67 #define DSM_POLL_INTERVAL 5 /* ms */ 68 #define DSM_TIMEOUT 1000 /* ms */ 69 70 #define NLB_BUF_SIZE 0x400000 71 #define TEST_MEM_ALIGN 1024 72 73 struct nlb_csr_ctl { 74 union { 75 uint32_t csr; 76 struct { 77 uint32_t reset:1; 78 uint32_t start:1; 79 uint32_t force_completion:1; 80 uint32_t reserved:29; 81 }; 82 }; 83 }; 84 85 struct nlb_csr_cfg { 86 union { 87 uint32_t csr; 88 struct { 89 uint32_t wrthru_en:1; 90 uint32_t cont:1; 91 uint32_t mode:3; 92 uint32_t multicl_len:2; 93 uint32_t rsvd1:1; 94 uint32_t delay_en:1; 95 uint32_t rdsel:2; 96 uint32_t rsvd2:1; 97 uint32_t chsel:3; 98 uint32_t rsvd3:1; 99 uint32_t wrpush_i:1; 100 uint32_t wr_chsel:3; 101 uint32_t rsvd4:3; 102 uint32_t test_cfg:5; 103 uint32_t interrupt_on_error:1; 104 uint32_t interrupt_testmode:1; 105 uint32_t wrfence_chsel:2; 106 }; 107 }; 108 }; 109 110 struct nlb_status0 { 111 union { 112 uint64_t csr; 113 struct { 114 uint32_t num_writes; 115 uint32_t num_reads; 116 }; 117 }; 118 }; 119 120 struct nlb_status1 { 121 union { 122 uint64_t csr; 123 struct { 124 uint32_t num_pend_writes; 125 uint32_t num_pend_reads; 126 }; 127 }; 128 }; 129 130 struct nlb_dsm_status { 131 uint32_t test_complete; 132 uint32_t test_error; 133 uint64_t num_clocks; 134 uint32_t num_reads; 135 uint32_t num_writes; 136 uint32_t start_overhead; 137 uint32_t end_overhead; 138 }; 139 140 /* DMA registers definition */ 141 #define DMA_CSR 0x40 142 #define DMA_DESC 0x60 143 #define DMA_ASE_CTRL 0x200 144 #define DMA_ASE_DATA 0x1000 145 146 #define DMA_ASE_WINDOW 4096 147 #define DMA_ASE_WINDOW_MASK ((uint64_t)(DMA_ASE_WINDOW - 1)) 148 #define INVALID_ASE_PAGE 0xffffffffffffffffULL 149 150 #define DMA_WF_MAGIC 0x5772745F53796E63ULL 151 #define DMA_WF_MAGIC_ROM 0x1000000000000 152 #define DMA_HOST_ADDR(addr) ((addr) | 0x2000000000000) 153 #define DMA_WF_HOST_ADDR(addr) ((addr) | 0x3000000000000) 154 155 #define NUM_DMA_BUF 8 156 #define HALF_DMA_BUF (NUM_DMA_BUF / 2) 157 158 #define DMA_MASK_32_BIT 0xFFFFFFFF 159 160 #define DMA_CSR_BUSY 0x1 161 #define DMA_DESC_BUFFER_EMPTY 0x2 162 #define DMA_DESC_BUFFER_FULL 0x4 163 164 #define DWORD_BYTES 4 165 #define IS_ALIGNED_DWORD(addr) (((addr) % DWORD_BYTES) == 0) 166 167 #define QWORD_BYTES 8 168 #define IS_ALIGNED_QWORD(addr) (((addr) % QWORD_BYTES) == 0) 169 170 #define DMA_ALIGN_BYTES 64 171 #define IS_DMA_ALIGNED(addr) (((addr) % DMA_ALIGN_BYTES) == 0) 172 173 #define CCIP_ALIGN_BYTES (DMA_ALIGN_BYTES << 2) 174 175 #define DMA_TIMEOUT_MSEC 5000 176 177 #define MAGIC_BUF_SIZE 64 178 #define ERR_CHECK_LIMIT 64 179 180 #ifndef MIN 181 #define MIN(a, b) ((a) < (b) ? (a) : (b)) 182 #endif 183 184 #ifndef ARRAY_SIZE 185 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 186 #endif 187 188 typedef enum { 189 HOST_TO_FPGA = 0, 190 FPGA_TO_HOST, 191 FPGA_TO_FPGA, 192 FPGA_MAX_TRANSFER_TYPE, 193 } fpga_dma_type; 194 195 typedef union { 196 uint32_t csr; 197 struct { 198 uint32_t tx_channel:8; 199 uint32_t generate_sop:1; 200 uint32_t generate_eop:1; 201 uint32_t park_reads:1; 202 uint32_t park_writes:1; 203 uint32_t end_on_eop:1; 204 uint32_t reserved_1:1; 205 uint32_t transfer_irq_en:1; 206 uint32_t early_term_irq_en:1; 207 uint32_t trans_error_irq_en:8; 208 uint32_t early_done_en:1; 209 uint32_t reserved_2:6; 210 uint32_t go:1; 211 }; 212 } msgdma_desc_ctrl; 213 214 typedef struct __rte_packed_begin { 215 uint32_t rd_address; 216 uint32_t wr_address; 217 uint32_t len; 218 uint16_t seq_num; 219 uint8_t rd_burst_count; 220 uint8_t wr_burst_count; 221 uint16_t rd_stride; 222 uint16_t wr_stride; 223 uint32_t rd_address_ext; 224 uint32_t wr_address_ext; 225 msgdma_desc_ctrl control; 226 } __rte_packed_end msgdma_ext_desc; 227 228 typedef union { 229 uint32_t csr; 230 struct { 231 uint32_t busy:1; 232 uint32_t desc_buf_empty:1; 233 uint32_t desc_buf_full:1; 234 uint32_t rsp_buf_empty:1; 235 uint32_t rsp_buf_full:1; 236 uint32_t stopped:1; 237 uint32_t resetting:1; 238 uint32_t stopped_on_error:1; 239 uint32_t stopped_on_early_term:1; 240 uint32_t irq:1; 241 uint32_t reserved:22; 242 }; 243 } msgdma_status; 244 245 typedef union { 246 uint32_t csr; 247 struct { 248 uint32_t stop_dispatcher:1; 249 uint32_t reset_dispatcher:1; 250 uint32_t stop_on_error:1; 251 uint32_t stopped_on_early_term:1; 252 uint32_t global_intr_en_mask:1; 253 uint32_t stop_descriptors:1; 254 uint32_t reserved:22; 255 }; 256 } msgdma_ctrl; 257 258 typedef union { 259 uint32_t csr; 260 struct { 261 uint32_t rd_fill_level:16; 262 uint32_t wr_fill_level:16; 263 }; 264 } msgdma_fill_level; 265 266 typedef union { 267 uint32_t csr; 268 struct { 269 uint32_t rsp_fill_level:16; 270 uint32_t reserved:16; 271 }; 272 } msgdma_rsp_level; 273 274 typedef union { 275 uint32_t csr; 276 struct { 277 uint32_t rd_seq_num:16; 278 uint32_t wr_seq_num:16; 279 }; 280 } msgdma_seq_num; 281 282 typedef struct __rte_packed_begin { 283 msgdma_status status; 284 msgdma_ctrl ctrl; 285 msgdma_fill_level fill_level; 286 msgdma_rsp_level rsp; 287 msgdma_seq_num seq_num; 288 } __rte_packed_end msgdma_csr; 289 290 #define CSR_STATUS(csr) (&(((msgdma_csr *)(csr))->status)) 291 #define CSR_CONTROL(csr) (&(((msgdma_csr *)(csr))->ctrl)) 292 293 struct nlb_afu_ctx { 294 uint8_t *addr; 295 uint8_t *dsm_ptr; 296 uint64_t dsm_iova; 297 uint8_t *src_ptr; 298 uint64_t src_iova; 299 uint8_t *dest_ptr; 300 uint64_t dest_iova; 301 struct nlb_dsm_status *status_ptr; 302 }; 303 304 struct dma_afu_ctx { 305 int index; 306 uint8_t *addr; 307 uint8_t *csr_addr; 308 uint8_t *desc_addr; 309 uint8_t *ase_ctrl_addr; 310 uint8_t *ase_data_addr; 311 uint64_t mem_size; 312 uint64_t cur_ase_page; 313 int event_fd; 314 int verbose; 315 int pattern; 316 void *data_buf; 317 void *ref_buf; 318 msgdma_ext_desc *desc_buf; 319 uint64_t *magic_buf; 320 uint64_t magic_iova; 321 uint32_t dma_buf_size; 322 uint64_t *dma_buf[NUM_DMA_BUF]; 323 uint64_t dma_iova[NUM_DMA_BUF]; 324 }; 325 326 struct n3000_afu_priv { 327 struct rte_pmd_afu_nlb_cfg nlb_cfg; 328 struct rte_pmd_afu_dma_cfg dma_cfg; 329 struct nlb_afu_ctx nlb_ctx; 330 struct dma_afu_ctx dma_ctx[NUM_N3000_DMA]; 331 int num_dma; 332 int cfg_type; 333 }; 334 335 #ifdef __cplusplus 336 } 337 #endif 338 339 #endif /* AFU_PMD_N3000_H */ 340