xref: /dpdk/drivers/raw/ifpga/afu_pmd_he_mem.h (revision 719834a6849e1daf4a70ff7742bbcc3ae7e25607)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2022 Intel Corporation
3  */
4 
5 #ifndef AFU_PMD_HE_MEM_H
6 #define AFU_PMD_HE_MEM_H
7 
8 #include "afu_pmd_core.h"
9 #include "rte_pmd_afu.h"
10 
11 #ifdef __cplusplus
12 extern "C" {
13 #endif
14 
15 #define HE_MEM_TG_UUID_L  0xa3dc5b831f5cecbb
16 #define HE_MEM_TG_UUID_H  0x4dadea342c7848cb
17 
18 #define NUM_MEM_TG_CHANNELS      4
19 #define MEM_TG_TIMEOUT_MS     5000
20 #define MEM_TG_POLL_INTERVAL_MS 10
21 
22 /* MEM-TG registers definition */
23 #define MEM_TG_SCRATCHPAD   0x28
24 #define MEM_TG_CTRL         0x30
25 #define   TGCONTROL(n)      (1 << (n))
26 #define MEM_TG_STAT         0x38
27 #define   TGSTATUS(v, n)    (((v) >> (n << 2)) & 0xf)
28 #define   TGPASS(v, n)      (((v) >> ((n << 2) + 3)) & 0x1)
29 #define   TGFAIL(v, n)      (((v) >> ((n << 2) + 2)) & 0x1)
30 #define   TGTIMEOUT(v, n)   (((v) >> ((n << 2) + 1)) & 0x1)
31 #define   TGACTIVE(v, n)    (((v) >> (n << 2)) & 0x1)
32 
33 struct he_mem_tg_ctx {
34 	uint8_t *addr;
35 };
36 
37 struct he_mem_tg_priv {
38 	struct rte_pmd_afu_he_mem_tg_cfg he_mem_tg_cfg;
39 	struct he_mem_tg_ctx he_mem_tg_ctx;
40 };
41 
42 #ifdef __cplusplus
43 }
44 #endif
45 
46 #endif /* AFU_PMD_HE_MEM_H */
47