1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2024 ZTE Corporation 3 */ 4 5 #ifndef ZXDH_PCI_H 6 #define ZXDH_PCI_H 7 8 #include <stdint.h> 9 #include <stdbool.h> 10 11 #include <bus_pci_driver.h> 12 13 #include "zxdh_ethdev.h" 14 15 enum zxdh_msix_status { 16 ZXDH_MSIX_NONE = 0, 17 ZXDH_MSIX_DISABLED = 1, 18 ZXDH_MSIX_ENABLED = 2 19 }; 20 21 /* The bit of the ISR which indicates a device has an interrupt. */ 22 #define ZXDH_PCI_ISR_INTR 0x1 23 /* The bit of the ISR which indicates a device configuration change. */ 24 #define ZXDH_PCI_ISR_CONFIG 0x2 25 /* Vector value used to disable MSI for queue. */ 26 #define ZXDH_MSI_NO_VECTOR 0x7F 27 28 #define ZXDH_PCI_VRING_ALIGN 4096 29 30 #define ZXDH_NET_F_CSUM 0 /* Host handles pkts w/ partial csum */ 31 #define ZXDH_NET_F_GUEST_CSUM 1 /* Guest handles pkts w/ partial csum */ 32 #define ZXDH_NET_F_MTU 3 /* Initial MTU advice. */ 33 #define ZXDH_NET_F_MAC 5 /* Host has given MAC address. */ 34 #define ZXDH_NET_F_GUEST_TSO4 7 /* Guest can handle TSOv4 in. */ 35 #define ZXDH_NET_F_GUEST_TSO6 8 /* Guest can handle TSOv6 in. */ 36 #define ZXDH_NET_F_GUEST_ECN 9 /* Guest can handle TSO[6] w/ ECN in. */ 37 #define ZXDH_NET_F_GUEST_UFO 10 /* Guest can handle UFO in. */ 38 39 #define ZXDH_NET_F_HOST_UFO 14 /* Host can handle UFO in. */ 40 #define ZXDH_NET_F_HOST_TSO4 11 /* Host can handle TSOv4 in. */ 41 #define ZXDH_NET_F_HOST_TSO6 12 /* Host can handle TSOv6 in. */ 42 #define ZXDH_NET_F_MRG_RXBUF 15 /* Host can merge receive buffers. */ 43 #define ZXDH_NET_F_STATUS 16 /* zxdh_net_config.status available */ 44 #define ZXDH_NET_F_MQ 22 /* Device supports Receive Flow Steering */ 45 #define ZXDH_F_ANY_LAYOUT 27 /* Can the device handle any descriptor layout */ 46 #define ZXDH_F_VERSION_1 32 47 #define ZXDH_F_RING_PACKED 34 48 #define ZXDH_F_IN_ORDER 35 49 #define ZXDH_F_NOTIFICATION_DATA 38 50 51 #define ZXDH_PCI_CAP_COMMON_CFG 1 /* Common configuration */ 52 #define ZXDH_PCI_CAP_NOTIFY_CFG 2 /* Notifications */ 53 #define ZXDH_PCI_CAP_ISR_CFG 3 /* ISR Status */ 54 #define ZXDH_PCI_CAP_DEVICE_CFG 4 /* Device specific configuration */ 55 #define ZXDH_PCI_CAP_PCI_CFG 5 /* PCI configuration access */ 56 57 /* Status byte for guest to report progress. */ 58 #define ZXDH_CONFIG_STATUS_RESET 0x00 59 #define ZXDH_CONFIG_STATUS_ACK 0x01 60 #define ZXDH_CONFIG_STATUS_DRIVER 0x02 61 #define ZXDH_CONFIG_STATUS_DRIVER_OK 0x04 62 #define ZXDH_CONFIG_STATUS_FEATURES_OK 0x08 63 #define ZXDH_CONFIG_STATUS_DEV_NEED_RESET 0x40 64 #define ZXDH_CONFIG_STATUS_FAILED 0x80 65 #define ZXDH_PCI_QUEUE_ADDR_SHIFT 12 66 67 struct __rte_packed_begin zxdh_net_config { 68 /* The config defining mac address (if ZXDH_NET_F_MAC) */ 69 uint8_t mac[RTE_ETHER_ADDR_LEN]; 70 /* See ZXDH_NET_F_STATUS and ZXDH_NET_S_* above */ 71 uint16_t status; 72 uint16_t max_virtqueue_pairs; 73 uint16_t mtu; 74 uint32_t speed; 75 uint8_t duplex; 76 } __rte_packed_end; 77 78 /* This is the PCI capability header: */ 79 struct zxdh_pci_cap { 80 uint8_t cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ 81 uint8_t cap_next; /* Generic PCI field: next ptr. */ 82 uint8_t cap_len; /* Generic PCI field: capability length */ 83 uint8_t cfg_type; /* Identifies the structure. */ 84 uint8_t bar; /* Where to find it. */ 85 uint8_t padding[3]; /* Pad to full dword. */ 86 uint32_t offset; /* Offset within bar. */ 87 uint32_t length; /* Length of the structure, in bytes. */ 88 }; 89 90 /* Fields in ZXDH_PCI_CAP_COMMON_CFG: */ 91 struct zxdh_pci_common_cfg { 92 /* About the whole device. */ 93 uint32_t device_feature_select; /* read-write */ 94 uint32_t device_feature; /* read-only */ 95 uint32_t guest_feature_select; /* read-write */ 96 uint32_t guest_feature; /* read-write */ 97 uint16_t msix_config; /* read-write */ 98 uint16_t num_queues; /* read-only */ 99 uint8_t device_status; /* read-write */ 100 uint8_t config_generation; /* read-only */ 101 102 /* About a specific virtqueue. */ 103 uint16_t queue_select; /* read-write */ 104 uint16_t queue_size; /* read-write, power of 2. */ 105 uint16_t queue_msix_vector; /* read-write */ 106 uint16_t queue_enable; /* read-write */ 107 uint16_t queue_notify_off; /* read-only */ 108 uint32_t queue_desc_lo; /* read-write */ 109 uint32_t queue_desc_hi; /* read-write */ 110 uint32_t queue_avail_lo; /* read-write */ 111 uint32_t queue_avail_hi; /* read-write */ 112 uint32_t queue_used_lo; /* read-write */ 113 uint32_t queue_used_hi; /* read-write */ 114 }; 115 116 static inline int32_t 117 vtpci_with_feature(struct zxdh_hw *hw, uint64_t bit) 118 { 119 return (hw->guest_features & (1ULL << bit)) != 0; 120 } 121 122 static inline int32_t 123 vtpci_packed_queue(struct zxdh_hw *hw) 124 { 125 return vtpci_with_feature(hw, ZXDH_F_RING_PACKED); 126 } 127 128 struct zxdh_pci_ops { 129 void (*read_dev_cfg)(struct zxdh_hw *hw, size_t offset, void *dst, int32_t len); 130 void (*write_dev_cfg)(struct zxdh_hw *hw, size_t offset, const void *src, int32_t len); 131 132 uint8_t (*get_status)(struct zxdh_hw *hw); 133 void (*set_status)(struct zxdh_hw *hw, uint8_t status); 134 135 uint64_t (*get_features)(struct zxdh_hw *hw); 136 void (*set_features)(struct zxdh_hw *hw, uint64_t features); 137 uint16_t (*set_queue_irq)(struct zxdh_hw *hw, struct zxdh_virtqueue *vq, uint16_t vec); 138 uint16_t (*set_config_irq)(struct zxdh_hw *hw, uint16_t vec); 139 uint8_t (*get_isr)(struct zxdh_hw *hw); 140 uint16_t (*get_queue_num)(struct zxdh_hw *hw, uint16_t queue_id); 141 void (*set_queue_num)(struct zxdh_hw *hw, uint16_t queue_id, uint16_t vq_size); 142 143 int32_t (*setup_queue)(struct zxdh_hw *hw, struct zxdh_virtqueue *vq); 144 void (*del_queue)(struct zxdh_hw *hw, struct zxdh_virtqueue *vq); 145 }; 146 147 struct zxdh_hw_internal { 148 const struct zxdh_pci_ops *zxdh_vtpci_ops; 149 }; 150 151 #define ZXDH_VTPCI_OPS(hw) (zxdh_hw_internal[(hw)->port_id].zxdh_vtpci_ops) 152 153 extern struct zxdh_hw_internal zxdh_hw_internal[RTE_MAX_ETHPORTS]; 154 extern const struct zxdh_pci_ops zxdh_dev_pci_ops; 155 156 void zxdh_pci_reset(struct zxdh_hw *hw); 157 void zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, 158 void *dst, int32_t length); 159 160 int32_t zxdh_read_pci_caps(struct rte_pci_device *dev, struct zxdh_hw *hw); 161 void zxdh_get_pci_dev_config(struct zxdh_hw *hw); 162 163 uint16_t zxdh_pci_get_features(struct zxdh_hw *hw); 164 enum zxdh_msix_status zxdh_pci_msix_detect(struct rte_pci_device *dev); 165 uint8_t zxdh_pci_isr(struct zxdh_hw *hw); 166 void zxdh_pci_reinit_complete(struct zxdh_hw *hw); 167 void zxdh_pci_set_status(struct zxdh_hw *hw, uint8_t status); 168 169 #endif /* ZXDH_PCI_H */ 170