1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 #ifndef _OTX_EP_VF_H_ 5 #define _OTX_EP_VF_H_ 6 7 #define OTX_EP_RING_OFFSET (0x1ull << 17) 8 9 /* OTX_EP VF IQ Registers */ 10 #define OTX_EP_R_IN_CONTROL_START (0x10000) 11 #define OTX_EP_R_IN_ENABLE_START (0x10010) 12 #define OTX_EP_R_IN_INSTR_BADDR_START (0x10020) 13 #define OTX_EP_R_IN_INSTR_RSIZE_START (0x10030) 14 #define OTX_EP_R_IN_INSTR_DBELL_START (0x10040) 15 #define OTX_EP_R_IN_CNTS_START (0x10050) 16 #define OTX_EP_R_IN_INT_LEVELS_START (0x10060) 17 18 #define OTX_EP_R_IN_CONTROL(ring) \ 19 (OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET)) 20 21 #define OTX_EP_R_IN_ENABLE(ring) \ 22 (OTX_EP_R_IN_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET)) 23 24 #define OTX_EP_R_IN_INSTR_BADDR(ring) \ 25 (OTX_EP_R_IN_INSTR_BADDR_START + ((ring) * OTX_EP_RING_OFFSET)) 26 27 #define OTX_EP_R_IN_INSTR_RSIZE(ring) \ 28 (OTX_EP_R_IN_INSTR_RSIZE_START + ((ring) * OTX_EP_RING_OFFSET)) 29 30 #define OTX_EP_R_IN_INSTR_DBELL(ring) \ 31 (OTX_EP_R_IN_INSTR_DBELL_START + ((ring) * OTX_EP_RING_OFFSET)) 32 33 #define OTX_EP_R_IN_CNTS(ring) \ 34 (OTX_EP_R_IN_CNTS_START + ((ring) * OTX_EP_RING_OFFSET)) 35 36 #define OTX_EP_R_IN_INT_LEVELS(ring) \ 37 (OTX_EP_R_IN_INT_LEVELS_START + ((ring) * OTX_EP_RING_OFFSET)) 38 39 /* OTX_EP VF IQ Masks */ 40 #define OTX_EP_R_IN_CTL_RPVF_MASK (0xF) 41 #define OTX_EP_R_IN_CTL_RPVF_POS (48) 42 43 #define OTX_EP_R_IN_CTL_IDLE (0x1ull << 28) 44 #define OTX_EP_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */ 45 #define OTX_EP_R_IN_CTL_IS_64B (0x1ull << 24) 46 #define OTX_EP_R_IN_CTL_ESR (0x1ull << 1) 47 /* OTX_EP VF OQ Registers */ 48 #define OTX_EP_R_OUT_CNTS_START (0x10100) 49 #define OTX_EP_R_OUT_INT_LEVELS_START (0x10110) 50 #define OTX_EP_R_OUT_SLIST_BADDR_START (0x10120) 51 #define OTX_EP_R_OUT_SLIST_RSIZE_START (0x10130) 52 #define OTX_EP_R_OUT_SLIST_DBELL_START (0x10140) 53 #define OTX_EP_R_OUT_CONTROL_START (0x10150) 54 #define OTX_EP_R_OUT_ENABLE_START (0x10160) 55 56 #define OTX_EP_R_OUT_CONTROL(ring) \ 57 (OTX_EP_R_OUT_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET)) 58 59 #define OTX_EP_R_OUT_ENABLE(ring) \ 60 (OTX_EP_R_OUT_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET)) 61 62 #define OTX_EP_R_OUT_SLIST_BADDR(ring) \ 63 (OTX_EP_R_OUT_SLIST_BADDR_START + ((ring) * OTX_EP_RING_OFFSET)) 64 65 #define OTX_EP_R_OUT_SLIST_RSIZE(ring) \ 66 (OTX_EP_R_OUT_SLIST_RSIZE_START + ((ring) * OTX_EP_RING_OFFSET)) 67 68 #define OTX_EP_R_OUT_SLIST_DBELL(ring) \ 69 (OTX_EP_R_OUT_SLIST_DBELL_START + ((ring) * OTX_EP_RING_OFFSET)) 70 71 #define OTX_EP_R_OUT_CNTS(ring) \ 72 (OTX_EP_R_OUT_CNTS_START + ((ring) * OTX_EP_RING_OFFSET)) 73 74 #define OTX_EP_R_OUT_INT_LEVELS(ring) \ 75 (OTX_EP_R_OUT_INT_LEVELS_START + ((ring) * OTX_EP_RING_OFFSET)) 76 77 /* OTX_EP VF OQ Masks */ 78 79 #define OTX_EP_R_OUT_CTL_IDLE (1ull << 36) 80 #define OTX_EP_R_OUT_CTL_ES_I (1ull << 34) 81 #define OTX_EP_R_OUT_CTL_NSR_I (1ull << 33) 82 #define OTX_EP_R_OUT_CTL_ROR_I (1ull << 32) 83 #define OTX_EP_R_OUT_CTL_ES_D (1ull << 30) 84 #define OTX_EP_R_OUT_CTL_NSR_D (1ull << 29) 85 #define OTX_EP_R_OUT_CTL_ROR_D (1ull << 28) 86 #define OTX_EP_R_OUT_CTL_ES_P (1ull << 26) 87 #define OTX_EP_R_OUT_CTL_NSR_P (1ull << 25) 88 #define OTX_EP_R_OUT_CTL_ROR_P (1ull << 24) 89 #define OTX_EP_R_OUT_CTL_IMODE (1ull << 23) 90 91 #define PCI_DEVID_OCTEONTX_EP_VF 0xa303 92 93 /* this is a static value set by SLI PF driver in octeon 94 * No handshake is available 95 * Change this if changing the value in SLI PF driver 96 */ 97 #define SDP_GBL_WMARK 0x100 98 99 100 /* Optional PKI Instruction Header(PKI IH) */ 101 typedef union { 102 uint64_t u64; 103 struct { 104 /** Tag Value */ 105 uint64_t tag:32; 106 107 /** QPG Value */ 108 uint64_t qpg:11; 109 110 /** Reserved1 */ 111 uint64_t reserved1:2; 112 113 /** Tag type */ 114 uint64_t tagtype:2; 115 116 /** Use Tag Type */ 117 uint64_t utt:1; 118 119 /** Skip Length */ 120 uint64_t sl:8; 121 122 /** Parse Mode */ 123 uint64_t pm:3; 124 125 /** Reserved2 */ 126 uint64_t reserved2:1; 127 128 /** Use QPG */ 129 uint64_t uqpg:1; 130 131 /** Use Tag */ 132 uint64_t utag:1; 133 134 /** Raw mode indicator 1 = RAW */ 135 uint64_t raw:1; 136 137 /** Wider bit */ 138 uint64_t w:1; 139 } s; 140 } otx_ep_instr_pki_ih3_t; 141 142 143 /* OTX_EP 64B instruction format */ 144 struct otx_ep_instr_64B { 145 /* Pointer where the input data is available. */ 146 uint64_t dptr; 147 148 /* OTX_EP Instruction Header. */ 149 union otx_ep_instr_ih ih; 150 151 /* PKI Optional Instruction Header. */ 152 otx_ep_instr_pki_ih3_t pki_ih3; 153 154 /** Pointer where the response for a RAW mode packet 155 * will be written by OCTEON TX. 156 */ 157 uint64_t rptr; 158 159 /* Input Request Header. */ 160 union otx_ep_instr_irh irh; 161 162 /* Additional headers available in a 64-byte instruction. */ 163 uint64_t exhdr[3]; 164 }; 165 166 int 167 otx_ep_vf_setup_device(struct otx_ep_device *otx_ep); 168 #endif /*_OTX_EP_VF_H_ */ 169