1 /* 2 * SPDX-License-Identifier: BSD-3-Clause 3 * Copyright(c) 2024 Napatech A/S 4 */ 5 6 /* 7 * nthw_fpga_reg_defs_dbs.h 8 * 9 * Auto-generated file - do *NOT* edit 10 * 11 */ 12 13 #ifndef _NTHW_FPGA_REG_DEFS_DBS_ 14 #define _NTHW_FPGA_REG_DEFS_DBS_ 15 16 /* DBS */ 17 #define DBS_RX_AM_CTRL (0x7359feUL) 18 #define DBS_RX_AM_CTRL_ADR (0x4704a1UL) 19 #define DBS_RX_AM_CTRL_CNT (0x104f9d70UL) 20 #define DBS_RX_AM_DATA (0xafa2dbe7UL) 21 #define DBS_RX_AM_DATA_ENABLE (0x11658278UL) 22 #define DBS_RX_AM_DATA_GPA (0xbf307344UL) 23 #define DBS_RX_AM_DATA_HID (0x5f0669eeUL) 24 #define DBS_RX_AM_DATA_INT (0xc32857aUL) 25 #define DBS_RX_AM_DATA_PCKED (0x7d840fb4UL) 26 #define DBS_RX_CONTROL (0xb18b2866UL) 27 #define DBS_RX_CONTROL_AME (0x1f9219acUL) 28 #define DBS_RX_CONTROL_AMS (0xeb46acfdUL) 29 #define DBS_RX_CONTROL_LQ (0xe65f90b2UL) 30 #define DBS_RX_CONTROL_QE (0x3e928d3UL) 31 #define DBS_RX_CONTROL_UWE (0xb490e8dbUL) 32 #define DBS_RX_CONTROL_UWS (0x40445d8aUL) 33 #define DBS_RX_DR_CTRL (0xa0cbc617UL) 34 #define DBS_RX_DR_CTRL_ADR (0xa7b57286UL) 35 #define DBS_RX_DR_CTRL_CNT (0xb7bdeb57UL) 36 #define DBS_RX_DR_DATA (0xf1a440eUL) 37 #define DBS_RX_DR_DATA_GPA (0x18c20563UL) 38 #define DBS_RX_DR_DATA_HDR (0xb98ed4d5UL) 39 #define DBS_RX_DR_DATA_HID (0xf8f41fc9UL) 40 #define DBS_RX_DR_DATA_PCKED (0x1e27ce2aUL) 41 #define DBS_RX_DR_DATA_QS (0xffb980ddUL) 42 #define DBS_RX_IDLE (0x93c723bfUL) 43 #define DBS_RX_IDLE_BUSY (0x8e043b5bUL) 44 #define DBS_RX_IDLE_IDLE (0x9dba27ccUL) 45 #define DBS_RX_IDLE_QUEUE (0xbbddab49UL) 46 #define DBS_RX_INIT (0x899772deUL) 47 #define DBS_RX_INIT_BUSY (0x8576d90aUL) 48 #define DBS_RX_INIT_INIT (0x8c9894fcUL) 49 #define DBS_RX_INIT_QUEUE (0xa7bab8c9UL) 50 #define DBS_RX_INIT_VAL (0x7789b4d8UL) 51 #define DBS_RX_INIT_VAL_IDX (0xead0e2beUL) 52 #define DBS_RX_INIT_VAL_PTR (0x5330810eUL) 53 #define DBS_RX_PTR (0x628ce523UL) 54 #define DBS_RX_PTR_PTR (0x7f834481UL) 55 #define DBS_RX_PTR_QUEUE (0x4f3fa6d1UL) 56 #define DBS_RX_PTR_VALID (0xbcc5ec4dUL) 57 #define DBS_RX_UW_CTRL (0x31afc0deUL) 58 #define DBS_RX_UW_CTRL_ADR (0x2ee4a2c9UL) 59 #define DBS_RX_UW_CTRL_CNT (0x3eec3b18UL) 60 #define DBS_RX_UW_DATA (0x9e7e42c7UL) 61 #define DBS_RX_UW_DATA_GPA (0x9193d52cUL) 62 #define DBS_RX_UW_DATA_HID (0x71a5cf86UL) 63 #define DBS_RX_UW_DATA_INT (0x22912312UL) 64 #define DBS_RX_UW_DATA_ISTK (0xd469a7ddUL) 65 #define DBS_RX_UW_DATA_PCKED (0xef15c665UL) 66 #define DBS_RX_UW_DATA_QS (0x7d422f44UL) 67 #define DBS_RX_UW_DATA_VEC (0x55cc9b53UL) 68 #define DBS_STATUS (0xb5f35220UL) 69 #define DBS_STATUS_OK (0xcf09a30fUL) 70 #define DBS_TX_AM_CTRL (0xd6d29b9UL) 71 #define DBS_TX_AM_CTRL_ADR (0xf8854f17UL) 72 #define DBS_TX_AM_CTRL_CNT (0xe88dd6c6UL) 73 #define DBS_TX_AM_DATA (0xa2bcaba0UL) 74 #define DBS_TX_AM_DATA_ENABLE (0xb6513570UL) 75 #define DBS_TX_AM_DATA_GPA (0x47f238f2UL) 76 #define DBS_TX_AM_DATA_HID (0xa7c42258UL) 77 #define DBS_TX_AM_DATA_INT (0xf4f0ceccUL) 78 #define DBS_TX_AM_DATA_PCKED (0x2e156650UL) 79 #define DBS_TX_CONTROL (0xbc955821UL) 80 #define DBS_TX_CONTROL_AME (0xe750521aUL) 81 #define DBS_TX_CONTROL_AMS (0x1384e74bUL) 82 #define DBS_TX_CONTROL_LQ (0x46ba4f6fUL) 83 #define DBS_TX_CONTROL_QE (0xa30cf70eUL) 84 #define DBS_TX_CONTROL_UWE (0x4c52a36dUL) 85 #define DBS_TX_CONTROL_UWS (0xb886163cUL) 86 #define DBS_TX_DR_CTRL (0xadd5b650UL) 87 #define DBS_TX_DR_CTRL_ADR (0x5f773930UL) 88 #define DBS_TX_DR_CTRL_CNT (0x4f7fa0e1UL) 89 #define DBS_TX_DR_DATA (0x2043449UL) 90 #define DBS_TX_DR_DATA_GPA (0xe0004ed5UL) 91 #define DBS_TX_DR_DATA_HDR (0x414c9f63UL) 92 #define DBS_TX_DR_DATA_HID (0x36547fUL) 93 #define DBS_TX_DR_DATA_PCKED (0x4db6a7ceUL) 94 #define DBS_TX_DR_DATA_PORT (0xf306968cUL) 95 #define DBS_TX_DR_DATA_QS (0x5f5c5f00UL) 96 #define DBS_TX_IDLE (0xf0171685UL) 97 #define DBS_TX_IDLE_BUSY (0x61399ebbUL) 98 #define DBS_TX_IDLE_IDLE (0x7287822cUL) 99 #define DBS_TX_IDLE_QUEUE (0x1b387494UL) 100 #define DBS_TX_INIT (0xea4747e4UL) 101 #define DBS_TX_INIT_BUSY (0x6a4b7ceaUL) 102 #define DBS_TX_INIT_INIT (0x63a5311cUL) 103 #define DBS_TX_INIT_QUEUE (0x75f6714UL) 104 #define DBS_TX_INIT_VAL (0x9f3c7e9bUL) 105 #define DBS_TX_INIT_VAL_IDX (0xc82a364cUL) 106 #define DBS_TX_INIT_VAL_PTR (0x71ca55fcUL) 107 #define DBS_TX_PTR (0xb4d5063eUL) 108 #define DBS_TX_PTR_PTR (0x729d34c6UL) 109 #define DBS_TX_PTR_QUEUE (0xa0020331UL) 110 #define DBS_TX_PTR_VALID (0x53f849adUL) 111 #define DBS_TX_QOS_CTRL (0x3b2c3286UL) 112 #define DBS_TX_QOS_CTRL_ADR (0x666600acUL) 113 #define DBS_TX_QOS_CTRL_CNT (0x766e997dUL) 114 #define DBS_TX_QOS_DATA (0x94fdb09fUL) 115 #define DBS_TX_QOS_DATA_BS (0x2c394071UL) 116 #define DBS_TX_QOS_DATA_EN (0x7eba6fUL) 117 #define DBS_TX_QOS_DATA_IR (0xb8caa92cUL) 118 #define DBS_TX_QOS_DATA_MUL (0xd7407a67UL) 119 #define DBS_TX_QOS_RATE (0xe6e27cc5UL) 120 #define DBS_TX_QOS_RATE_DIV (0x8cd07ba3UL) 121 #define DBS_TX_QOS_RATE_MUL (0x9814e40bUL) 122 #define DBS_TX_QP_CTRL (0xd5fba432UL) 123 #define DBS_TX_QP_CTRL_ADR (0x84238184UL) 124 #define DBS_TX_QP_CTRL_CNT (0x942b1855UL) 125 #define DBS_TX_QP_DATA (0x7a2a262bUL) 126 #define DBS_TX_QP_DATA_VPORT (0xda741d67UL) 127 #define DBS_TX_UW_CTRL (0x3cb1b099UL) 128 #define DBS_TX_UW_CTRL_ADR (0xd626e97fUL) 129 #define DBS_TX_UW_CTRL_CNT (0xc62e70aeUL) 130 #define DBS_TX_UW_DATA (0x93603280UL) 131 #define DBS_TX_UW_DATA_GPA (0x69519e9aUL) 132 #define DBS_TX_UW_DATA_HID (0x89678430UL) 133 #define DBS_TX_UW_DATA_INO (0x5036a148UL) 134 #define DBS_TX_UW_DATA_INT (0xda5368a4UL) 135 #define DBS_TX_UW_DATA_ISTK (0xf693732fUL) 136 #define DBS_TX_UW_DATA_PCKED (0xbc84af81UL) 137 #define DBS_TX_UW_DATA_QS (0xdda7f099UL) 138 #define DBS_TX_UW_DATA_VEC (0xad0ed0e5UL) 139 140 #endif /* _NTHW_FPGA_REG_DEFS_DBS_ */ 141 142 /* 143 * Auto-generated file - do *NOT* edit 144 */ 145