1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd. 3 * Copyright(c) 2010-2017 Intel Corporation 4 */ 5 6 #ifndef _NGBE_REGS_H_ 7 #define _NGBE_REGS_H_ 8 9 #define NGBE_PVMBX_QSIZE (16) /* 16*4B */ 10 #define NGBE_PVMBX_BSIZE (NGBE_PVMBX_QSIZE * 4) 11 12 #define NGBE_REMOVED(a) (0) 13 14 #define NGBE_REG_DUMMY 0xFFFFFF 15 16 #define MS8(shift, mask) (((u8)(mask)) << (shift)) 17 #define LS8(val, shift, mask) (((u8)(val) & (u8)(mask)) << (shift)) 18 #define RS8(reg, shift, mask) (((u8)(reg) >> (shift)) & (u8)(mask)) 19 20 #define MS16(shift, mask) (((u16)(mask)) << (shift)) 21 #define LS16(val, shift, mask) (((u16)(val) & (u16)(mask)) << (shift)) 22 #define RS16(reg, shift, mask) (((u16)(reg) >> (shift)) & (u16)(mask)) 23 24 #define MS32(shift, mask) (((u32)(mask)) << (shift)) 25 #define LS32(val, shift, mask) (((u32)(val) & (u32)(mask)) << (shift)) 26 #define RS32(reg, shift, mask) (((u32)(reg) >> (shift)) & (u32)(mask)) 27 28 #define MS64(shift, mask) (((u64)(mask)) << (shift)) 29 #define LS64(val, shift, mask) (((u64)(val) & (u64)(mask)) << (shift)) 30 #define RS64(reg, shift, mask) (((u64)(reg) >> (shift)) & (u64)(mask)) 31 32 #define MS(shift, mask) MS32(shift, mask) 33 #define LS(val, shift, mask) LS32(val, shift, mask) 34 #define RS(reg, shift, mask) RS32(reg, shift, mask) 35 36 #define ROUND_UP(x, y) (((x) + (y) - 1) / (y) * (y)) 37 #define ROUND_DOWN(x, y) ((x) / (y) * (y)) 38 #define ROUND_OVER(x, maxbits, unitbits) \ 39 ((x) >= 1 << (maxbits) ? 0 : (x) >> (unitbits)) 40 41 /* autoc bits definition */ 42 #define NGBE_AUTOC NGBE_REG_DUMMY 43 #define NGBE_AUTOC_FLU MS64(0, 0x1) 44 #define NGBE_AUTOC_10G_PMA_PMD_MASK MS64(7, 0x3) /* parallel */ 45 #define NGBE_AUTOC_10G_XAUI LS64(0, 7, 0x3) 46 #define NGBE_AUTOC_10G_KX4 LS64(1, 7, 0x3) 47 #define NGBE_AUTOC_10G_CX4 LS64(2, 7, 0x3) 48 #define NGBE_AUTOC_10G_KR LS64(3, 7, 0x3) /* fixme */ 49 #define NGBE_AUTOC_1G_PMA_PMD_MASK MS64(9, 0x7) 50 #define NGBE_AUTOC_1G_BX LS64(0, 9, 0x7) 51 #define NGBE_AUTOC_1G_KX LS64(1, 9, 0x7) 52 #define NGBE_AUTOC_1G_SFI LS64(0, 9, 0x7) 53 #define NGBE_AUTOC_1G_KX_BX LS64(1, 9, 0x7) 54 #define NGBE_AUTOC_AN_RESTART MS64(12, 0x1) 55 #define NGBE_AUTOC_LMS_MASK MS64(13, 0x7) 56 #define NGBE_AUTOC_LMS_10G LS64(3, 13, 0x7) 57 #define NGBE_AUTOC_LMS_KX4_KX_KR LS64(4, 13, 0x7) 58 #define NGBE_AUTOC_LMS_SGMII_1G_100M LS64(5, 13, 0x7) 59 #define NGBE_AUTOC_LMS_KX4_KX_KR_1G_AN LS64(6, 13, 0x7) 60 #define NGBE_AUTOC_LMS_KX4_KX_KR_SGMII LS64(7, 13, 0x7) 61 #define NGBE_AUTOC_LMS_1G_LINK_NO_AN LS64(0, 13, 0x7) 62 #define NGBE_AUTOC_LMS_10G_LINK_NO_AN LS64(1, 13, 0x7) 63 #define NGBE_AUTOC_LMS_1G_AN LS64(2, 13, 0x7) 64 #define NGBE_AUTOC_LMS_KX4_AN LS64(4, 13, 0x7) 65 #define NGBE_AUTOC_LMS_KX4_AN_1G_AN LS64(6, 13, 0x7) 66 #define NGBE_AUTOC_LMS_ATTACH_TYPE LS64(7, 13, 0x7) 67 #define NGBE_AUTOC_LMS_AN MS64(15, 0x7) 68 69 #define NGBE_AUTOC_KR_SUPP MS64(16, 0x1) 70 #define NGBE_AUTOC_FECR MS64(17, 0x1) 71 #define NGBE_AUTOC_FECA MS64(18, 0x1) 72 #define NGBE_AUTOC_AN_RX_ALIGN MS64(18, 0x1F) /* fixme */ 73 #define NGBE_AUTOC_AN_RX_DRIFT MS64(23, 0x3) 74 #define NGBE_AUTOC_AN_RX_LOOSE MS64(24, 0x3) 75 #define NGBE_AUTOC_PD_TMR MS64(25, 0x3) 76 #define NGBE_AUTOC_RF MS64(27, 0x1) 77 #define NGBE_AUTOC_ASM_PAUSE MS64(29, 0x1) 78 #define NGBE_AUTOC_SYM_PAUSE MS64(28, 0x1) 79 #define NGBE_AUTOC_PAUSE MS64(28, 0x3) 80 #define NGBE_AUTOC_KX_SUPP MS64(30, 0x1) 81 #define NGBE_AUTOC_KX4_SUPP MS64(31, 0x1) 82 83 #define NGBE_AUTOC_10GS_PMA_PMD_MASK MS64(48, 0x3) /* serial */ 84 #define NGBE_AUTOC_10GS_KR LS64(0, 48, 0x3) 85 #define NGBE_AUTOC_10GS_XFI LS64(1, 48, 0x3) 86 #define NGBE_AUTOC_10GS_SFI LS64(2, 48, 0x3) 87 #define NGBE_AUTOC_LINK_DIA_MASK MS64(60, 0x7) 88 #define NGBE_AUTOC_LINK_DIA_D3_MASK LS64(5, 60, 0x7) 89 90 #define NGBE_AUTOC_SPEED_MASK MS64(32, 0xFFFF) 91 #define NGBD_AUTOC_SPEED(r) RS64(r, 32, 0xFFFF) 92 #define NGBE_AUTOC_SPEED(v) LS64(v, 32, 0xFFFF) 93 #define NGBE_LINK_SPEED_UNKNOWN 0 94 #define NGBE_LINK_SPEED_10M_FULL 0x0002 95 #define NGBE_LINK_SPEED_100M_FULL 0x0008 96 #define NGBE_LINK_SPEED_1GB_FULL 0x0020 97 #define NGBE_LINK_SPEED_2_5GB_FULL 0x0400 98 #define NGBE_LINK_SPEED_5GB_FULL 0x0800 99 #define NGBE_LINK_SPEED_10GB_FULL 0x0080 100 #define NGBE_LINK_SPEED_40GB_FULL 0x0100 101 #define NGBE_AUTOC_AUTONEG MS64(63, 0x1) 102 103 104 105 /* Hardware Datapath: 106 * RX: / Queue <- Filter \ 107 * Host | TC <=> SEC <=> MAC <=> PHY 108 * TX: \ Queue -> Filter / 109 * 110 * Packet Filter: 111 * RX: RSS < FDIR < Filter < Encrypt 112 * 113 * Macro Argument Naming: 114 * rp = ring pair [0,127] 115 * tc = traffic class [0,7] 116 * up = user priority [0,7] 117 * pi = pool index [0,63] 118 * r = register 119 * v = value 120 * s = shift 121 * m = mask 122 * i,j,k = array index 123 * H,L = high/low bits 124 * HI,LO = high/low state 125 */ 126 127 #define NGBE_ETHPHYIF NGBE_REG_DUMMY 128 #define NGBE_ETHPHYIF_MDIO_ACT MS(1, 0x1) 129 #define NGBE_ETHPHYIF_MDIO_MODE MS(2, 0x1) 130 #define NGBE_ETHPHYIF_MDIO_BASE(r) RS(r, 3, 0x1F) 131 #define NGBE_ETHPHYIF_MDIO_SHARED MS(13, 0x1) 132 #define NGBE_ETHPHYIF_SPEED_10M MS(17, 0x1) 133 #define NGBE_ETHPHYIF_SPEED_100M MS(18, 0x1) 134 #define NGBE_ETHPHYIF_SPEED_1G MS(19, 0x1) 135 #define NGBE_ETHPHYIF_SPEED_2_5G MS(20, 0x1) 136 #define NGBE_ETHPHYIF_SPEED_10G MS(21, 0x1) 137 #define NGBE_ETHPHYIF_SGMII_ENABLE MS(25, 0x1) 138 #define NGBE_ETHPHYIF_INT_PHY_MODE MS(24, 0x1) 139 #define NGBE_ETHPHYIF_IO_XPCS MS(30, 0x1) 140 #define NGBE_ETHPHYIF_IO_EPHY MS(31, 0x1) 141 142 /****************************************************************************** 143 * Chip Registers 144 ******************************************************************************/ 145 /** 146 * Chip Status 147 **/ 148 #define NGBE_PWR 0x010000 149 #define NGBE_PWR_LAN(r) RS(r, 28, 0xC) 150 #define NGBE_PWR_LAN_0 (1) 151 #define NGBE_PWR_LAN_1 (2) 152 #define NGBE_PWR_LAN_2 (3) 153 #define NGBE_PWR_LAN_3 (4) 154 #define NGBE_CTL 0x010004 155 #define NGBE_LOCKPF 0x010008 156 #define NGBE_RST 0x01000C 157 #define NGBE_RST_SW MS(0, 0x1) 158 #define NGBE_RST_LAN(i) MS(((i) + 1), 0x1) 159 #define NGBE_RST_FW MS(5, 0x1) 160 #define NGBE_RST_ETH(i) MS(((i) + 29), 0x1) 161 #define NGBE_RST_GLB MS(31, 0x1) 162 #define NGBE_RST_DEFAULT (NGBE_RST_SW | \ 163 NGBE_RST_LAN(0) | \ 164 NGBE_RST_LAN(1) | \ 165 NGBE_RST_LAN(2) | \ 166 NGBE_RST_LAN(3)) 167 #define NGBE_PROB 0x010010 168 #define NGBE_IODRV 0x010024 169 #define NGBE_STAT 0x010028 170 #define NGBE_STAT_MNGINIT MS(0, 0x1) 171 #define NGBE_STAT_MNGVETO MS(8, 0x1) 172 #define NGBE_STAT_ECCLAN0 MS(16, 0x1) 173 #define NGBE_STAT_ECCLAN1 MS(17, 0x1) 174 #define NGBE_STAT_ECCLAN2 MS(18, 0x1) 175 #define NGBE_STAT_ECCLAN3 MS(19, 0x1) 176 #define NGBE_STAT_ECCMNG MS(20, 0x1) 177 #define NGBE_STAT_ECCPCORE MS(21, 0X1) 178 #define NGBE_STAT_ECCPCIW MS(22, 0x1) 179 #define NGBE_STAT_ECCPCIEPHY MS(23, 0x1) 180 #define NGBE_STAT_ECCFMGR MS(24, 0x1) 181 #define NGBE_STAT_GPHY_IN_RST(i) MS(((i) + 9), 0x1) 182 #define NGBE_RSTSTAT 0x010030 183 #define NGBE_RSTSTAT_PROG MS(20, 0x1) 184 #define NGBE_RSTSTAT_PREP MS(19, 0x1) 185 #define NGBE_RSTSTAT_TYPE_MASK MS(16, 0x7) 186 #define NGBE_RSTSTAT_TYPE(r) RS(r, 16, 0x7) 187 #define NGBE_RSTSTAT_TYPE_PE LS(0, 16, 0x7) 188 #define NGBE_RSTSTAT_TYPE_PWR LS(1, 16, 0x7) 189 #define NGBE_RSTSTAT_TYPE_HOT LS(2, 16, 0x7) 190 #define NGBE_RSTSTAT_TYPE_SW LS(3, 16, 0x7) 191 #define NGBE_RSTSTAT_TYPE_FW LS(4, 16, 0x7) 192 #define NGBE_RSTSTAT_TMRINIT_MASK MS(8, 0xFF) 193 #define NGBE_RSTSTAT_TMRINIT(v) LS(v, 8, 0xFF) 194 #define NGBE_RSTSTAT_TMRCNT_MASK MS(0, 0xFF) 195 #define NGBE_RSTSTAT_TMRCNT(v) LS(v, 0, 0xFF) 196 #define NGBE_PWRTMR 0x010034 197 198 /** 199 * SPI(Flash) 200 **/ 201 #define NGBE_SPICMD 0x010104 202 #define NGBE_SPICMD_ADDR(v) LS(v, 0, 0xFFFFFF) 203 #define NGBE_SPICMD_CLK(v) LS(v, 25, 0x7) 204 #define NGBE_SPICMD_CMD(v) LS(v, 28, 0x7) 205 #define NGBE_SPIDAT 0x010108 206 #define NGBE_SPIDAT_BYPASS MS(31, 0x1) 207 #define NGBE_SPIDAT_STATUS(v) LS(v, 16, 0xFF) 208 #define NGBE_SPIDAT_OPDONE MS(0, 0x1) 209 #define NGBE_SPISTAT 0x01010C 210 #define NGBE_SPISTAT_OPDONE MS(0, 0x1) 211 #define NGBE_SPISTAT_BPFLASH MS(31, 0x1) 212 #define NGBE_SPIUSRCMD 0x010110 213 #define NGBE_SPICFG0 0x010114 214 #define NGBE_SPICFG1 0x010118 215 216 /* FMGR Registers */ 217 #define NGBE_ILDRSTAT 0x010120 218 #define NGBE_ILDRSTAT_PCIRST MS(0, 0x1) 219 #define NGBE_ILDRSTAT_PWRRST MS(1, 0x1) 220 #define NGBE_ILDRSTAT_SWRST MS(11, 0x1) 221 #define NGBE_ILDRSTAT_SWRST_LAN0 MS(13, 0x1) 222 #define NGBE_ILDRSTAT_SWRST_LAN1 MS(14, 0x1) 223 #define NGBE_ILDRSTAT_SWRST_LAN2 MS(15, 0x1) 224 #define NGBE_ILDRSTAT_SWRST_LAN3 MS(16, 0x1) 225 226 #define NGBE_SRAM 0x010124 227 #define NGBE_SRAM_SZ(v) LS(v, 28, 0x7) 228 #define NGBE_SRAMCTLECC 0x010130 229 #define NGBE_SRAMINJECC 0x010134 230 #define NGBE_SRAMECC 0x010138 231 232 /* Sensors for PVT(Process Voltage Temperature) */ 233 #define NGBE_TSCTRL 0x010300 234 #define NGBE_TSCTRL_EVALMD MS(31, 0x1) 235 #define NGBE_TSEN 0x010304 236 #define NGBE_TSEN_ENA MS(0, 0x1) 237 #define NGBE_TSSTAT 0x010308 238 #define NGBE_TSSTAT_VLD MS(16, 0x1) 239 #define NGBE_TSSTAT_DATA(r) RS(r, 0, 0x3FF) 240 #define NGBE_TSATHRE 0x01030C 241 #define NGBE_TSDTHRE 0x010310 242 #define NGBE_TSINTR 0x010314 243 #define NGBE_TSINTR_AEN MS(0, 0x1) 244 #define NGBE_TSINTR_DEN MS(1, 0x1) 245 #define NGBE_TSALM 0x010318 246 #define NGBE_TSALM_LO MS(0, 0x1) 247 #define NGBE_TSALM_HI MS(1, 0x1) 248 249 #define NGBE_EFUSE_WDATA0 0x010320 250 #define NGBE_EFUSE_WDATA1 0x010324 251 #define NGBE_EFUSE_RDATA0 0x010328 252 #define NGBE_EFUSE_RDATA1 0x01032C 253 #define NGBE_EFUSE_STATUS 0x010330 254 255 /****************************************************************************** 256 * Port Registers 257 ******************************************************************************/ 258 /* Internal PHY reg_offset [0,31] */ 259 #define NGBE_PHY_CONFIG(reg_offset) (0x014000 + (reg_offset) * 4) 260 261 /* Port Control */ 262 #define NGBE_PORTCTL 0x014400 263 #define NGBE_PORTCTL_VLANEXT MS(0, 0x1) 264 #define NGBE_PORTCTL_ETAG MS(1, 0x1) 265 #define NGBE_PORTCTL_QINQ MS(2, 0x1) 266 #define NGBE_PORTCTL_DRVLOAD MS(3, 0x1) 267 #define NGBE_PORTCTL_NUMVT_MASK MS(12, 0x1) 268 #define NGBE_PORTCTL_NUMVT_8 LS(1, 12, 0x1) 269 #define NGBE_PORTCTL_RSTDONE MS(14, 0x1) 270 #define NGBE_PORTCTL_TEREDODIA MS(27, 0x1) 271 #define NGBE_PORTCTL_GENEVEDIA MS(28, 0x1) 272 #define NGBE_PORTCTL_VXLANGPEDIA MS(30, 0x1) 273 #define NGBE_PORTCTL_VXLANDIA MS(31, 0x1) 274 275 /* Port Status */ 276 #define NGBE_PORTSTAT 0x014404 277 #define NGBE_PORTSTAT_BW_MASK MS(1, 0x7) 278 #define NGBE_PORTSTAT_BW_1G MS(1, 0x1) 279 #define NGBE_PORTSTAT_BW_100M MS(2, 0x1) 280 #define NGBE_PORTSTAT_BW_10M MS(3, 0x1) 281 #define NGBE_PORTSTAT_ID(r) RS(r, 8, 0x3) 282 283 #define NGBE_EXTAG 0x014408 284 #define NGBE_EXTAG_ETAG_MASK MS(0, 0xFFFF) 285 #define NGBE_EXTAG_ETAG(v) LS(v, 0, 0xFFFF) 286 #define NGBE_EXTAG_VLAN_MASK MS(16, 0xFFFF) 287 #define NGBE_EXTAG_VLAN(v) LS(v, 16, 0xFFFF) 288 289 #define NGBE_TCPTIME 0x014420 290 291 #define NGBE_LEDCTL 0x014424 292 #define NGBE_LEDCTL_SEL(s) MS((s), 0x1) 293 #define NGBE_LEDCTL_OD(s) MS(((s) + 16), 0x1) 294 /* s=1G(1),100M(2),10M(3) */ 295 #define NGBE_LEDCTL_100M (NGBE_LEDCTL_SEL(2) | NGBE_LEDCTL_OD(2)) 296 297 #define NGBE_TAGTPID(i) (0x014430 + (i) * 4) /*0-3*/ 298 #define NGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF) 299 #define NGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF) 300 #define NGBE_TAGTPID_MSB_MASK MS(16, 0xFFFF) 301 #define NGBE_TAGTPID_MSB(v) LS(v, 16, 0xFFFF) 302 303 #define NGBE_LAN_SPEED 0x014440 304 #define NGBE_LAN_SPEED_MASK MS(0, 0x3) 305 306 /* GPIO Registers */ 307 #define NGBE_GPIODATA 0x014800 308 #define NGBE_GPIOBIT_0 MS(0, 0x1) /* O:tx fault */ 309 #define NGBE_GPIOBIT_1 MS(1, 0x1) /* O:tx disabled */ 310 #define NGBE_GPIOBIT_2 MS(2, 0x1) /* I:sfp module absent */ 311 #define NGBE_GPIOBIT_3 MS(3, 0x1) /* I:rx signal lost */ 312 #define NGBE_GPIOBIT_4 MS(4, 0x1) /* O:rate select, 1G(0) 10G(1) */ 313 #define NGBE_GPIOBIT_5 MS(5, 0x1) /* O:rate select, 1G(0) 10G(1) */ 314 #define NGBE_GPIOBIT_6 MS(6, 0x1) /* I:ext phy interrupt */ 315 #define NGBE_GPIOBIT_7 MS(7, 0x1) /* I:fan speed alarm */ 316 #define NGBE_GPIODIR 0x014804 317 #define NGBE_GPIODIR_DDR(v) LS(v, 0, 0x3) 318 #define NGBE_GPIOCTL 0x014808 319 #define NGBE_GPIOINTEN 0x014830 320 #define NGBE_GPIOINTEN_INT(v) LS(v, 0, 0x3) 321 #define NGBE_GPIOINTMASK 0x014834 322 #define NGBE_GPIOINTTYPE 0x014838 323 #define NGBE_GPIOINTTYPE_LEVEL(v) LS(v, 0, 0x3) 324 #define NGBE_GPIOINTPOL 0x01483C 325 #define NGBE_GPIOINTPOL_ACT(v) LS(v, 0, 0x3) 326 #define NGBE_GPIOINTSTAT 0x014840 327 #define NGBE_GPIOINTDB 0x014848 328 #define NGBE_GPIOEOI 0x01484C 329 #define NGBE_GPIODAT 0x014850 330 331 /* TPH */ 332 #define NGBE_TPHCFG 0x014F00 333 334 /****************************************************************************** 335 * Transmit DMA Registers 336 ******************************************************************************/ 337 /* TDMA Control */ 338 #define NGBE_DMATXCTRL 0x018000 339 #define NGBE_DMATXCTRL_ENA MS(0, 0x1) 340 #define NGBE_DMATXCTRL_TPID_MASK MS(16, 0xFFFF) 341 #define NGBE_DMATXCTRL_TPID(v) LS(v, 16, 0xFFFF) 342 #define NGBE_POOLTXENA(i) (0x018004 + (i) * 4) /*0*/ 343 #define NGBE_PRBTXDMACTL 0x018010 344 #define NGBE_ECCTXDMACTL 0x018014 345 #define NGBE_ECCTXDMAINJ 0x018018 346 #define NGBE_ECCTXDMA 0x01801C 347 #define NGBE_PBTXDMATH 0x018020 348 #define NGBE_QPTXLLI 0x018040 349 #define NGBE_POOLTXLBET 0x018050 350 #define NGBE_POOLTXASET 0x018058 351 #define NGBE_POOLTXASMAC 0x018060 352 #define NGBE_POOLTXASVLAN 0x018070 353 #define NGBE_POOLTXDSA 0x0180A0 354 #define NGBE_POOLTAG(pl) (0x018100 + (pl) * 4) /*0-7*/ 355 #define NGBE_POOLTAG_VTAG(v) LS(v, 0, 0xFFFF) 356 #define NGBE_POOLTAG_VTAG_MASK MS(0, 0xFFFF) 357 #define TXGBD_POOLTAG_VTAG_UP(r) RS(r, 13, 0x7) 358 #define NGBE_POOLTAG_TPIDSEL(v) LS(v, 24, 0x7) 359 #define NGBE_POOLTAG_ETAG_MASK MS(27, 0x3) 360 #define NGBE_POOLTAG_ETAG LS(2, 27, 0x3) 361 #define NGBE_POOLTAG_ACT_MASK MS(30, 0x3) 362 #define NGBE_POOLTAG_ACT_ALWAYS LS(1, 30, 0x3) 363 #define NGBE_POOLTAG_ACT_NEVER LS(2, 30, 0x3) 364 365 /* Queue Arbiter(QoS) */ 366 #define NGBE_QARBTXCTL 0x018200 367 #define NGBE_QARBTXCTL_DA MS(6, 0x1) 368 #define NGBE_QARBTXRATE 0x018404 369 #define NGBE_QARBTXRATE_MIN(v) LS(v, 0, 0x3FFF) 370 #define NGBE_QARBTXRATE_MAX(v) LS(v, 16, 0x3FFF) 371 372 /* ETAG */ 373 #define NGBE_POOLETAG(pl) (0x018700 + (pl) * 4) 374 375 /****************************************************************************** 376 * Receive DMA Registers 377 ******************************************************************************/ 378 /* Receive Control */ 379 #define NGBE_ARBRXCTL 0x012000 380 #define NGBE_ARBRXCTL_DIA MS(6, 0x1) 381 #define NGBE_POOLRXENA(i) (0x012004 + (i) * 4) /*0*/ 382 #define NGBE_PRBRDMA 0x012010 383 #define NGBE_ECCRXDMACTL 0x012014 384 #define NGBE_ECCRXDMAINJ 0x012018 385 #define NGBE_ECCRXDMA 0x01201C 386 #define NGBE_POOLRXDNA 0x0120A0 387 #define NGBE_QPRXDROP 0x012080 388 #define NGBE_QPRXSTRPVLAN 0x012090 389 390 /****************************************************************************** 391 * Packet Buffer 392 ******************************************************************************/ 393 /* Flow Control */ 394 #define NGBE_FCXOFFTM 0x019200 395 #define NGBE_FCWTRLO 0x019220 396 #define NGBE_FCWTRLO_TH(v) LS(v, 10, 0x1FF) /*KB*/ 397 #define NGBE_FCWTRLO_XON MS(31, 0x1) 398 #define NGBE_FCWTRHI 0x019260 399 #define NGBE_FCWTRHI_TH(v) LS(v, 10, 0x1FF) /*KB*/ 400 #define NGBE_FCWTRHI_XOFF MS(31, 0x1) 401 #define NGBE_RXFCRFSH 0x0192A0 402 #define NGBE_RXFCFSH_TIME(v) LS(v, 0, 0xFFFF) 403 #define NGBE_FCSTAT 0x01CE00 404 #define NGBE_FCSTAT_DLNK MS(0, 0x1) 405 #define NGBE_FCSTAT_ULNK MS(8, 0x1) 406 407 #define NGBE_RXFCCFG 0x011090 408 #define NGBE_RXFCCFG_FC MS(0, 0x1) 409 #define NGBE_TXFCCFG 0x0192A4 410 #define NGBE_TXFCCFG_FC MS(3, 0x1) 411 412 /* Data Buffer */ 413 #define NGBE_PBRXCTL 0x019000 414 #define NGBE_PBRXCTL_ST MS(0, 0x1) 415 #define NGBE_PBRXCTL_ENA MS(31, 0x1) 416 #define NGBE_PBRXSTAT 0x019004 417 #define NGBE_PBRXSIZE 0x019020 418 #define NGBE_PBRXSIZE_KB(v) LS(v, 10, 0x3F) 419 420 #define NGBE_PBRXOFTMR 0x019094 421 #define NGBE_PBRXDBGCMD 0x019090 422 #define NGBE_PBRXDBGDAT 0x0190A0 423 424 #define NGBE_PBTXSIZE 0x01CC00 425 426 /* LLI */ 427 #define NGBE_PBRXLLI 0x19080 428 #define NGBE_PBRXLLI_SZLT(v) LS(v, 0, 0xFFF) 429 #define NGBE_PBRXLLI_UPLT(v) LS(v, 16, 0x7) 430 #define NGBE_PBRXLLI_UPEA MS(19, 0x1) 431 432 /* Port Arbiter(QoS) */ 433 #define NGBE_PARBTXCTL 0x01CD00 434 #define NGBE_PARBTXCTL_DA MS(6, 0x1) 435 436 /****************************************************************************** 437 * Packet Filter (L2-7) 438 ******************************************************************************/ 439 /** 440 * Receive Scaling 441 **/ 442 #define NGBE_POOLRSS(pl) (0x019300 + (pl) * 4) /*0-7*/ 443 #define NGBE_POOLRSS_L4HDR MS(1, 0x1) 444 #define NGBE_POOLRSS_L3HDR MS(2, 0x1) 445 #define NGBE_POOLRSS_L2HDR MS(3, 0x1) 446 #define NGBE_POOLRSS_L2TUN MS(4, 0x1) 447 #define NGBE_POOLRSS_TUNHDR MS(5, 0x1) 448 #define NGBE_RSSTBL(i) (0x019400 + (i) * 4) /*32*/ 449 #define NGBE_RSSKEY(i) (0x019480 + (i) * 4) /*10*/ 450 #define NGBE_RACTL 0x0194F4 451 #define NGBE_RACTL_RSSENA MS(2, 0x1) 452 #define NGBE_RACTL_RSSMASK MS(16, 0xFFFF) 453 #define NGBE_RACTL_RSSIPV4TCP MS(16, 0x1) 454 #define NGBE_RACTL_RSSIPV4 MS(17, 0x1) 455 #define NGBE_RACTL_RSSIPV6 MS(20, 0x1) 456 #define NGBE_RACTL_RSSIPV6TCP MS(21, 0x1) 457 #define NGBE_RACTL_RSSIPV4UDP MS(22, 0x1) 458 #define NGBE_RACTL_RSSIPV6UDP MS(23, 0x1) 459 460 /** 461 * Flow Director 462 **/ 463 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */ 464 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */ 465 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */ 466 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */ 467 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */ 468 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */ 469 470 /** 471 * 5-tuple Filter 472 **/ 473 #define NGBE_5TFPORT(i) (0x019A00 + (i) * 4) /*0-7*/ 474 #define NGBE_5TFPORT_SRC(v) LS(v, 0, 0xFFFF) 475 #define NGBE_5TFPORT_DST(v) LS(v, 16, 0xFFFF) 476 #define NGBE_5TFCTL0(i) (0x019C00 + (i) * 4) /*0-7*/ 477 #define NGBE_5TFCTL0_PROTO(v) LS(v, 0, 0x3) 478 enum ngbe_5tuple_protocol { 479 NGBE_5TF_PROT_TCP = 0, 480 NGBE_5TF_PROT_UDP, 481 NGBE_5TF_PROT_SCTP, 482 NGBE_5TF_PROT_NONE, 483 }; 484 #define NGBE_5TFCTL0_PRI(v) LS(v, 2, 0x7) 485 #define NGBE_5TFCTL0_POOL(v) LS(v, 8, 0x7) 486 #define NGBE_5TFCTL0_MASK MS(27, 0xF) 487 #define NGBE_5TFCTL0_MSPORT MS(27, 0x1) 488 #define NGBE_5TFCTL0_MDPORT MS(28, 0x1) 489 #define NGBE_5TFCTL0_MPROTO MS(29, 0x1) 490 #define NGBE_5TFCTL0_MPOOL MS(30, 0x1) 491 #define NGBE_5TFCTL0_ENA MS(31, 0x1) 492 #define NGBE_5TFCTL1(i) (0x019E00 + (i) * 4) /*0-7*/ 493 #define NGBE_5TFCTL1_CHKSZ MS(12, 0x1) 494 #define NGBE_5TFCTL1_LLI MS(20, 0x1) 495 #define NGBE_5TFCTL1_QP(v) LS(v, 21, 0x7) 496 497 /** 498 * Storm Control 499 **/ 500 #define NGBE_STRMCTL 0x015004 501 #define NGBE_STRMCTL_MCPNSH MS(0, 0x1) 502 #define NGBE_STRMCTL_MCDROP MS(1, 0x1) 503 #define NGBE_STRMCTL_BCPNSH MS(2, 0x1) 504 #define NGBE_STRMCTL_BCDROP MS(3, 0x1) 505 #define NGBE_STRMCTL_DFTPOOL MS(4, 0x1) 506 #define NGBE_STRMCTL_ITVL(v) LS(v, 8, 0x3FF) 507 #define NGBE_STRMTH 0x015008 508 #define NGBE_STRMTH_MC(v) LS(v, 0, 0xFFFF) 509 #define NGBE_STRMTH_BC(v) LS(v, 16, 0xFFFF) 510 511 /****************************************************************************** 512 * Ether Flow 513 ******************************************************************************/ 514 #define NGBE_PSRCTL 0x015000 515 #define NGBE_PSRCTL_TPE MS(4, 0x1) 516 #define NGBE_PSRCTL_ADHF12_MASK MS(5, 0x3) 517 #define NGBE_PSRCTL_ADHF12(v) LS(v, 5, 0x3) 518 #define NGBE_PSRCTL_UCHFENA MS(7, 0x1) 519 #define NGBE_PSRCTL_MCHFENA MS(7, 0x1) 520 #define NGBE_PSRCTL_MCP MS(8, 0x1) 521 #define NGBE_PSRCTL_UCP MS(9, 0x1) 522 #define NGBE_PSRCTL_BCA MS(10, 0x1) 523 #define NGBE_PSRCTL_L4CSUM MS(12, 0x1) 524 #define NGBE_PSRCTL_PCSD MS(13, 0x1) 525 #define NGBE_PSRCTL_LBENA MS(18, 0x1) 526 #define NGBE_FRMSZ 0x015020 527 #define NGBE_FRMSZ_MAX_MASK MS(0, 0xFFFF) 528 #define NGBE_FRMSZ_MAX(v) LS((v) + 4, 0, 0xFFFF) 529 #define NGBE_VLANCTL 0x015088 530 #define NGBE_VLANCTL_TPID_MASK MS(0, 0xFFFF) 531 #define NGBE_VLANCTL_TPID(v) LS(v, 0, 0xFFFF) 532 #define NGBE_VLANCTL_CFI MS(28, 0x1) 533 #define NGBE_VLANCTL_CFIENA MS(29, 0x1) 534 #define NGBE_VLANCTL_VFE MS(30, 0x1) 535 #define NGBE_POOLCTL 0x0151B0 536 #define NGBE_POOLCTL_DEFDSA MS(29, 0x1) 537 #define NGBE_POOLCTL_RPLEN MS(30, 0x1) 538 #define NGBE_POOLCTL_MODE_MASK MS(16, 0x3) 539 #define NGBE_PSRPOOL_MODE_MAC LS(0, 16, 0x3) 540 #define NGBE_PSRPOOL_MODE_ETAG LS(1, 16, 0x3) 541 #define NGBE_POOLCTL_DEFPL(v) LS(v, 7, 0x7) 542 #define NGBE_POOLCTL_DEFPL_MASK MS(7, 0x7) 543 544 #define NGBE_ETFLT(i) (0x015128 + (i) * 4) /*0-7*/ 545 #define NGBE_ETFLT_ETID(v) LS(v, 0, 0xFFFF) 546 #define NGBE_ETFLT_ETID_MASK MS(0, 0xFFFF) 547 #define NGBE_ETFLT_POOL(v) LS(v, 20, 0x7) 548 #define NGBE_ETFLT_POOLENA MS(26, 0x1) 549 #define NGBE_ETFLT_TXAS MS(29, 0x1) 550 #define NGBE_ETFLT_1588 MS(30, 0x1) 551 #define NGBE_ETFLT_ENA MS(31, 0x1) 552 #define NGBE_ETCLS(i) (0x019100 + (i) * 4) /*0-7*/ 553 #define NGBE_ETCLS_QPID(v) LS(v, 16, 0x7) 554 #define NGBD_ETCLS_QPID(r) RS(r, 16, 0x7) 555 #define NGBE_ETCLS_LLI MS(29, 0x1) 556 #define NGBE_ETCLS_QENA MS(31, 0x1) 557 #define NGBE_SYNCLS 0x019130 558 #define NGBE_SYNCLS_ENA MS(0, 0x1) 559 #define NGBE_SYNCLS_QPID(v) LS(v, 1, 0x7) 560 #define NGBD_SYNCLS_QPID(r) RS(r, 1, 0x7) 561 #define NGBE_SYNCLS_QPID_MASK MS(1, 0x7) 562 #define NGBE_SYNCLS_HIPRIO MS(31, 0x1) 563 564 /* MAC & VLAN & NVE */ 565 #define NGBE_PSRVLANIDX 0x016230 /*0-31*/ 566 #define NGBE_PSRVLAN 0x016220 567 #define NGBE_PSRVLAN_VID(v) LS(v, 0, 0xFFF) 568 #define NGBE_PSRVLAN_EA MS(31, 0x1) 569 #define NGBE_PSRVLANPLM(i) (0x016224 + (i) * 4) /*0-1*/ 570 571 /** 572 * Mirror Rules 573 **/ 574 #define NGBE_MIRRCTL(i) (0x015B00 + (i) * 4) 575 #define NGBE_MIRRCTL_POOL MS(0, 0x1) 576 #define NGBE_MIRRCTL_UPLINK MS(1, 0x1) 577 #define NGBE_MIRRCTL_DNLINK MS(2, 0x1) 578 #define NGBE_MIRRCTL_VLAN MS(3, 0x1) 579 #define NGBE_MIRRCTL_DESTP(v) LS(v, 8, 0x7) 580 #define NGBE_MIRRVLANL(i) (0x015B10 + (i) * 8) 581 #define NGBE_MIRRPOOLL(i) (0x015B30 + (i) * 8) 582 583 /** 584 * Time Stamp 585 **/ 586 #define NGBE_TSRXCTL 0x015188 587 #define NGBE_TSRXCTL_VLD MS(0, 0x1) 588 #define NGBE_TSRXCTL_TYPE(v) LS(v, 1, 0x7) 589 #define NGBE_TSRXCTL_TYPE_V2L2 (0) 590 #define NGBE_TSRXCTL_TYPE_V1L4 (1) 591 #define NGBE_TSRXCTL_TYPE_V2L24 (2) 592 #define NGBE_TSRXCTL_TYPE_V2EVENT (5) 593 #define NGBE_TSRXCTL_ENA MS(4, 0x1) 594 #define NGBE_TSRXSTMPL 0x0151E8 595 #define NGBE_TSRXSTMPH 0x0151A4 596 #define NGBE_TSTXCTL 0x011F00 597 #define NGBE_TSTXCTL_VLD MS(0, 0x1) 598 #define NGBE_TSTXCTL_ENA MS(4, 0x1) 599 #define NGBE_TSTXSTMPL 0x011F04 600 #define NGBE_TSTXSTMPH 0x011F08 601 #define NGBE_TSTIMEL 0x011F0C 602 #define NGBE_TSTIMEH 0x011F10 603 #define NGBE_TSTIMEINC 0x011F14 604 #define NGBE_TSTIMEINC_IV(v) LS(v, 0, 0x7FFFFFF) 605 606 /** 607 * Wake on Lan 608 **/ 609 #define NGBE_WOLCTL 0x015B80 610 #define NGBE_WOLIPCTL 0x015B84 611 #define NGBE_WOLIP4(i) (0x015BC0 + (i) * 4) /* 0-3 */ 612 #define NGBE_WOLIP6(i) (0x015BE0 + (i) * 4) /* 0-3 */ 613 614 #define NGBE_WOLFLEXCTL 0x015CFC 615 #define NGBE_WOLFLEXI 0x015B8C 616 #define NGBE_WOLFLEXDAT(i) (0x015C00 + (i) * 16) /* 0-15 */ 617 #define NGBE_WOLFLEXMSK(i) (0x015C08 + (i) * 16) /* 0-15 */ 618 619 /****************************************************************************** 620 * Security Registers 621 ******************************************************************************/ 622 #define NGBE_SECRXCTL 0x017000 623 #define NGBE_SECRXCTL_ODSA MS(0, 0x1) 624 #define NGBE_SECRXCTL_XDSA MS(1, 0x1) 625 #define NGBE_SECRXCTL_CRCSTRIP MS(2, 0x1) 626 #define NGBE_SECRXCTL_SAVEBAD MS(6, 0x1) 627 #define NGBE_SECRXSTAT 0x017004 628 #define NGBE_SECRXSTAT_RDY MS(0, 0x1) 629 #define NGBE_SECRXSTAT_ECC MS(1, 0x1) 630 631 #define NGBE_SECTXCTL 0x01D000 632 #define NGBE_SECTXCTL_ODSA MS(0, 0x1) 633 #define NGBE_SECTXCTL_XDSA MS(1, 0x1) 634 #define NGBE_SECTXCTL_STFWD MS(2, 0x1) 635 #define NGBE_SECTXCTL_MSKIV MS(3, 0x1) 636 #define NGBE_SECTXSTAT 0x01D004 637 #define NGBE_SECTXSTAT_RDY MS(0, 0x1) 638 #define NGBE_SECTXSTAT_ECC MS(1, 0x1) 639 #define NGBE_SECTXBUFAF 0x01D008 640 #define NGBE_SECTXBUFAE 0x01D00C 641 #define NGBE_SECTXIFG 0x01D020 642 #define NGBE_SECTXIFG_MIN(v) LS(v, 0, 0xF) 643 #define NGBE_SECTXIFG_MIN_MASK MS(0, 0xF) 644 645 /** 646 * LinkSec 647 **/ 648 #define NGBE_LSECRXCAP 0x017200 649 #define NGBE_LSECRXCTL 0x017204 650 /* disabled(0),check(1),strict(2),drop(3) */ 651 #define NGBE_LSECRXCTL_MODE_MASK MS(2, 0x3) 652 #define NGBE_LSECRXCTL_MODE_STRICT LS(2, 2, 0x3) 653 #define NGBE_LSECRXCTL_POSTHDR MS(6, 0x1) 654 #define NGBE_LSECRXCTL_REPLAY MS(7, 0x1) 655 #define NGBE_LSECRXSCIL 0x017208 656 #define NGBE_LSECRXSCIH 0x01720C 657 #define NGBE_LSECRXSA(i) (0x017210 + (i) * 4) /* 0-1 */ 658 #define NGBE_LSECRXPN(i) (0x017218 + (i) * 4) /* 0-1 */ 659 #define NGBE_LSECRXKEY(n, i) (0x017220 + 0x10 * (n) + 4 * (i)) /*0-3*/ 660 #define NGBE_LSECTXCAP 0x01D200 661 #define NGBE_LSECTXCTL 0x01D204 662 /* disabled(0), auth(1), auth+encrypt(2) */ 663 #define NGBE_LSECTXCTL_MODE_MASK MS(0, 0x3) 664 #define NGBE_LSECTXCTL_MODE_AUTH LS(1, 0, 0x3) 665 #define NGBE_LSECTXCTL_MODE_AENC LS(2, 0, 0x3) 666 #define NGBE_LSECTXCTL_PNTRH_MASK MS(8, 0xFFFFFF) 667 #define NGBE_LSECTXCTL_PNTRH(v) LS(v, 8, 0xFFFFFF) 668 #define NGBE_LSECTXSCIL 0x01D208 669 #define NGBE_LSECTXSCIH 0x01D20C 670 #define NGBE_LSECTXSA 0x01D210 671 #define NGBE_LSECTXPN0 0x01D214 672 #define NGBE_LSECTXPN1 0x01D218 673 #define NGBE_LSECTXKEY0(i) (0x01D21C + (i) * 4) /* 0-3 */ 674 #define NGBE_LSECTXKEY1(i) (0x01D22C + (i) * 4) /* 0-3 */ 675 676 #define NGBE_LSECRX_UTPKT 0x017240 677 #define NGBE_LSECRX_DECOCT 0x017244 678 #define NGBE_LSECRX_VLDOCT 0x017248 679 #define NGBE_LSECRX_BTPKT 0x01724C 680 #define NGBE_LSECRX_NOSCIPKT 0x017250 681 #define NGBE_LSECRX_UNSCIPKT 0x017254 682 #define NGBE_LSECRX_UNCHKPKT 0x017258 683 #define NGBE_LSECRX_DLYPKT 0x01725C 684 #define NGBE_LSECRX_LATEPKT 0x017260 685 #define NGBE_LSECRX_OKPKT(i) (0x017264 + (i) * 4) /* 0-1 */ 686 #define NGBE_LSECRX_BADPKT(i) (0x01726C + (i) * 4) /* 0-1 */ 687 #define NGBE_LSECRX_INVPKT(i) (0x017274 + (i) * 4) /* 0-1 */ 688 #define NGBE_LSECRX_BADSAPKT(i) (0x01727C + (i) * 8) /* 0-3 */ 689 #define NGBE_LSECRX_INVSAPKT(i) (0x017280 + (i) * 8) /* 0-3 */ 690 #define NGBE_LSECTX_UTPKT 0x01D23C 691 #define NGBE_LSECTX_ENCPKT 0x01D240 692 #define NGBE_LSECTX_PROTPKT 0x01D244 693 #define NGBE_LSECTX_ENCOCT 0x01D248 694 #define NGBE_LSECTX_PROTOCT 0x01D24C 695 696 /****************************************************************************** 697 * MAC Registers 698 ******************************************************************************/ 699 #define NGBE_MACRXCFG 0x011004 700 #define NGBE_MACRXCFG_ENA MS(0, 0x1) 701 #define NGBE_MACRXCFG_JUMBO MS(8, 0x1) 702 #define NGBE_MACRXCFG_LB MS(10, 0x1) 703 #define NGBE_MACCNTCTL 0x011800 704 #define NGBE_MACCNTCTL_RC MS(2, 0x1) 705 706 #define NGBE_MACRXFLT 0x011008 707 #define NGBE_MACRXFLT_PROMISC MS(0, 0x1) 708 #define NGBE_MACRXFLT_CTL_MASK MS(6, 0x3) 709 #define NGBE_MACRXFLT_CTL_DROP LS(0, 6, 0x3) 710 #define NGBE_MACRXFLT_CTL_NOPS LS(1, 6, 0x3) 711 #define NGBE_MACRXFLT_CTL_NOFT LS(2, 6, 0x3) 712 #define NGBE_MACRXFLT_CTL_PASS LS(3, 6, 0x3) 713 #define NGBE_MACRXFLT_RXALL MS(31, 0x1) 714 715 #define NGBE_MAC_WDG_TIMEOUT 0x01100C 716 717 /****************************************************************************** 718 * Statistic Registers 719 ******************************************************************************/ 720 /* Ring Counter */ 721 #define NGBE_QPRXPKT(rp) (0x001014 + 0x40 * (rp)) 722 #define NGBE_QPRXOCTL(rp) (0x001018 + 0x40 * (rp)) 723 #define NGBE_QPRXOCTH(rp) (0x00101C + 0x40 * (rp)) 724 #define NGBE_QPRXMPKT(rp) (0x001020 + 0x40 * (rp)) 725 #define NGBE_QPRXBPKT(rp) (0x001024 + 0x40 * (rp)) 726 #define NGBE_QPTXPKT(rp) (0x003014 + 0x40 * (rp)) 727 #define NGBE_QPTXOCTL(rp) (0x003018 + 0x40 * (rp)) 728 #define NGBE_QPTXOCTH(rp) (0x00301C + 0x40 * (rp)) 729 #define NGBE_QPTXMPKT(rp) (0x003020 + 0x40 * (rp)) 730 #define NGBE_QPTXBPKT(rp) (0x003024 + 0x40 * (rp)) 731 732 /* TDMA Counter */ 733 #define NGBE_DMATXDROP 0x018300 734 #define NGBE_DMATXSECDROP 0x018304 735 #define NGBE_DMATXPKT 0x018308 736 #define NGBE_DMATXOCTL 0x01830C 737 #define NGBE_DMATXOCTH 0x018310 738 #define NGBE_DMATXMNG 0x018314 739 740 /* RDMA Counter */ 741 #define NGBE_DMARXDROP 0x012500 742 #define NGBE_DMARXPKT 0x012504 743 #define NGBE_DMARXOCTL 0x012508 744 #define NGBE_DMARXOCTH 0x01250C 745 #define NGBE_DMARXMNG 0x012510 746 747 /* Packet Buffer Counter */ 748 #define NGBE_PBRXMISS 0x019040 749 #define NGBE_PBRXPKT 0x019060 750 #define NGBE_PBRXREP 0x019064 751 #define NGBE_PBRXDROP 0x019068 752 #define NGBE_PBLBSTAT 0x01906C 753 #define NGBE_PBLBSTAT_FREE(r) RS(r, 0, 0x3FF) 754 #define NGBE_PBLBSTAT_FULL MS(11, 0x1) 755 #define NGBE_PBRXWRPTR 0x019180 756 #define NGBE_PBRXWRPTR_HEAD(r) RS(r, 0, 0xFFFF) 757 #define NGBE_PBRXWRPTR_TAIL(r) RS(r, 16, 0xFFFF) 758 #define NGBE_PBRXRDPTR 0x0191A0 759 #define NGBE_PBRXRDPTR_HEAD(r) RS(r, 0, 0xFFFF) 760 #define NGBE_PBRXRDPTR_TAIL(r) RS(r, 16, 0xFFFF) 761 #define NGBE_PBRXDATA 0x0191C0 762 #define NGBE_PBRXDATA_RDPTR(r) RS(r, 0, 0xFFFF) 763 #define NGBE_PBRXDATA_WRPTR(r) RS(r, 16, 0xFFFF) 764 #define NGBE_PBRX_USDSP 0x0191E0 765 #define NGBE_RXPBPFCDMACL 0x019210 766 #define NGBE_RXPBPFCDMACH 0x019214 767 #define NGBE_PBTXLNKXOFF 0x019218 768 #define NGBE_PBTXLNKXON 0x01921C 769 770 #define NGBE_PBTXSTAT 0x01C004 771 #define NGBE_PBTXSTAT_EMPT(tc, r) ((1 << (tc) & (r)) >> (tc)) 772 773 #define NGBE_PBRXLNKXOFF 0x011988 774 #define NGBE_PBRXLNKXON 0x011E0C 775 776 #define NGBE_PBLPBK 0x01CF08 777 778 /* Ether Flow Counter */ 779 #define NGBE_LANPKTDROP 0x0151C0 780 #define NGBE_MNGPKTDROP 0x0151C4 781 782 #define NGBE_PSRLANPKTCNT 0x0151B8 783 #define NGBE_PSRMNGPKTCNT 0x0151BC 784 785 /* MAC Counter */ 786 #define NGBE_MACRXERRCRCL 0x011928 787 #define NGBE_MACRXERRCRCH 0x01192C 788 #define NGBE_MACRXERRLENL 0x011978 789 #define NGBE_MACRXERRLENH 0x01197C 790 #define NGBE_MACRX1TO64L 0x011940 791 #define NGBE_MACRX1TO64H 0x011944 792 #define NGBE_MACRX65TO127L 0x011948 793 #define NGBE_MACRX65TO127H 0x01194C 794 #define NGBE_MACRX128TO255L 0x011950 795 #define NGBE_MACRX128TO255H 0x011954 796 #define NGBE_MACRX256TO511L 0x011958 797 #define NGBE_MACRX256TO511H 0x01195C 798 #define NGBE_MACRX512TO1023L 0x011960 799 #define NGBE_MACRX512TO1023H 0x011964 800 #define NGBE_MACRX1024TOMAXL 0x011968 801 #define NGBE_MACRX1024TOMAXH 0x01196C 802 #define NGBE_MACTX1TO64L 0x011834 803 #define NGBE_MACTX1TO64H 0x011838 804 #define NGBE_MACTX65TO127L 0x01183C 805 #define NGBE_MACTX65TO127H 0x011840 806 #define NGBE_MACTX128TO255L 0x011844 807 #define NGBE_MACTX128TO255H 0x011848 808 #define NGBE_MACTX256TO511L 0x01184C 809 #define NGBE_MACTX256TO511H 0x011850 810 #define NGBE_MACTX512TO1023L 0x011854 811 #define NGBE_MACTX512TO1023H 0x011858 812 #define NGBE_MACTX1024TOMAXL 0x01185C 813 #define NGBE_MACTX1024TOMAXH 0x011860 814 815 #define NGBE_MACRXUNDERSIZE 0x011938 816 #define NGBE_MACRXOVERSIZE 0x01193C 817 #define NGBE_MACRXJABBER 0x011934 818 819 #define NGBE_MACRXPKTL 0x011900 820 #define NGBE_MACRXPKTH 0x011904 821 #define NGBE_MACTXPKTL 0x01181C 822 #define NGBE_MACTXPKTH 0x011820 823 #define NGBE_MACRXGBOCTL 0x011908 824 #define NGBE_MACRXGBOCTH 0x01190C 825 #define NGBE_MACTXGBOCTL 0x011814 826 #define NGBE_MACTXGBOCTH 0x011818 827 828 #define NGBE_MACRXOCTL 0x011918 829 #define NGBE_MACRXOCTH 0x01191C 830 #define NGBE_MACRXMPKTL 0x011920 831 #define NGBE_MACRXMPKTH 0x011924 832 #define NGBE_MACTXOCTL 0x011824 833 #define NGBE_MACTXOCTH 0x011828 834 #define NGBE_MACTXMPKTL 0x01182C 835 #define NGBE_MACTXMPKTH 0x011830 836 837 /* Management Counter */ 838 #define NGBE_MNGOUT 0x01CF00 839 #define NGBE_MNGIN 0x01CF04 840 #define NGBE_MNGDROP 0x01CF0C 841 842 /* MAC SEC Counter */ 843 #define NGBE_LSECRXUNTAG 0x017240 844 #define NGBE_LSECRXDECOCT 0x017244 845 #define NGBE_LSECRXVLDOCT 0x017248 846 #define NGBE_LSECRXBADTAG 0x01724C 847 #define NGBE_LSECRXNOSCI 0x017250 848 #define NGBE_LSECRXUKSCI 0x017254 849 #define NGBE_LSECRXUNCHK 0x017258 850 #define NGBE_LSECRXDLY 0x01725C 851 #define NGBE_LSECRXLATE 0x017260 852 #define NGBE_LSECRXGOOD 0x017264 853 #define NGBE_LSECRXBAD 0x01726C 854 #define NGBE_LSECRXUK 0x017274 855 #define NGBE_LSECRXBADSA 0x01727C 856 #define NGBE_LSECRXUKSA 0x017280 857 #define NGBE_LSECTXUNTAG 0x01D23C 858 #define NGBE_LSECTXENC 0x01D240 859 #define NGBE_LSECTXPTT 0x01D244 860 #define NGBE_LSECTXENCOCT 0x01D248 861 #define NGBE_LSECTXPTTOCT 0x01D24C 862 863 /* Management Counter */ 864 #define NGBE_MNGOS2BMC 0x01E094 865 #define NGBE_MNGBMC2OS 0x01E090 866 867 /****************************************************************************** 868 * PF(Physical Function) Registers 869 ******************************************************************************/ 870 /* Interrupt */ 871 #define NGBE_BMECTL 0x012020 872 #define NGBE_BMECTL_VFDRP MS(1, 0x1) 873 #define NGBE_BMECTL_PFDRP MS(0, 0x1) 874 #define NGBE_ICRMISC 0x000100 875 #define NGBE_ICRMISC_MASK MS(8, 0xFFFFFF) 876 #define NGBE_ICRMISC_RST MS(10, 0x1) /* device reset event */ 877 #define NGBE_ICRMISC_TS MS(11, 0x1) /* time sync */ 878 #define NGBE_ICRMISC_STALL MS(12, 0x1) /* trans or recv path is stalled */ 879 #define NGBE_ICRMISC_LNKSEC MS(13, 0x1) /* Tx LinkSec require key exchange*/ 880 #define NGBE_ICRMISC_ERRBUF MS(14, 0x1) /* Packet Buffer Overrun */ 881 #define NGBE_ICRMISC_ERRMAC MS(17, 0x1) /* err reported by MAC */ 882 #define NGBE_ICRMISC_PHY MS(18, 0x1) /* interrupt reported by eth phy */ 883 #define NGBE_ICRMISC_ERRIG MS(20, 0x1) /* integrity error */ 884 #define NGBE_ICRMISC_SPI MS(21, 0x1) /* SPI interface */ 885 #define NGBE_ICRMISC_VFMBX MS(23, 0x1) /* VF-PF message box */ 886 #define NGBE_ICRMISC_GPIO MS(26, 0x1) /* GPIO interrupt */ 887 #define NGBE_ICRMISC_ERRPCI MS(27, 0x1) /* pcie request error */ 888 #define NGBE_ICRMISC_HEAT MS(28, 0x1) /* overheat detection */ 889 #define NGBE_ICRMISC_PROBE MS(29, 0x1) /* probe match */ 890 #define NGBE_ICRMISC_MNGMBX MS(30, 0x1) /* mng mailbox */ 891 #define NGBE_ICRMISC_TIMER MS(31, 0x1) /* tcp timer */ 892 #define NGBE_ICRMISC_DEFAULT ( \ 893 NGBE_ICRMISC_RST | \ 894 NGBE_ICRMISC_ERRMAC | \ 895 NGBE_ICRMISC_PHY | \ 896 NGBE_ICRMISC_ERRIG | \ 897 NGBE_ICRMISC_GPIO | \ 898 NGBE_ICRMISC_VFMBX | \ 899 NGBE_ICRMISC_MNGMBX | \ 900 NGBE_ICRMISC_STALL | \ 901 NGBE_ICRMISC_TIMER) 902 #define NGBE_ICSMISC 0x000104 903 #define NGBE_IENMISC 0x000108 904 #define NGBE_IVARMISC 0x0004FC 905 #define NGBE_IVARMISC_VEC(v) LS(v, 0, 0x7) 906 #define NGBE_IVARMISC_VLD MS(7, 0x1) 907 #define NGBE_ICR(i) (0x000120 + (i) * 4) /*0*/ 908 #define NGBE_ICR_MASK MS(0, 0x1FF) 909 #define NGBE_ICS(i) (0x000130 + (i) * 4) /*0*/ 910 #define NGBE_ICS_MASK NGBE_ICR_MASK 911 #define NGBE_IMS(i) (0x000140 + (i) * 4) /*0*/ 912 #define NGBE_IMS_MASK NGBE_ICR_MASK 913 #define NGBE_IMC(i) (0x000150 + (i) * 4) /*0*/ 914 #define NGBE_IMC_MASK NGBE_ICR_MASK 915 #define NGBE_IVAR(i) (0x000500 + (i) * 4) /*0-3*/ 916 #define NGBE_IVAR_VEC(v) LS(v, 0, 0x7) 917 #define NGBE_IVAR_VLD MS(7, 0x1) 918 #define NGBE_TCPTMR 0x000170 919 #define NGBE_ITRSEL 0x000180 920 921 /* P2V Mailbox */ 922 #define NGBE_MBMEM(i) (0x005000 + 0x40 * (i)) /*0-7*/ 923 #define NGBE_MBCTL(i) (0x000600 + 4 * (i)) /*0-7*/ 924 #define NGBE_MBCTL_STS MS(0, 0x1) /* Initiate message send to VF */ 925 #define NGBE_MBCTL_ACK MS(1, 0x1) /* Ack message recv'd from VF */ 926 #define NGBE_MBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */ 927 #define NGBE_MBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */ 928 #define NGBE_MBCTL_RVFU MS(4, 0x1) /* Reset VFU - used when VF stuck */ 929 #define NGBE_MBVFICR 0x000480 930 #define NGBE_MBVFICR_INDEX(vf) ((vf) >> 4) 931 #define NGBE_MBVFICR_VFREQ_MASK (0x0000FFFF) /* bits for VF messages */ 932 #define NGBE_MBVFICR_VFREQ_VF1 (0x00000001) /* bit for VF 1 message */ 933 #define NGBE_MBVFICR_VFACK_MASK (0xFFFF0000) /* bits for VF acks */ 934 #define NGBE_MBVFICR_VFACK_VF1 (0x00010000) /* bit for VF 1 ack */ 935 #define NGBE_FLRVFP 0x000490 936 #define NGBE_FLRVFE 0x0004A0 937 #define NGBE_FLRVFEC 0x0004A8 938 939 /****************************************************************************** 940 * VF(Virtual Function) Registers 941 ******************************************************************************/ 942 #define NGBE_VFPBWRAP 0x000000 943 #define NGBE_VFPBWRAP_WRAP MS(0, 0x7) 944 #define NGBE_VFPBWRAP_EMPT MS(3, 0x1) 945 #define NGBE_VFSTATUS 0x000004 946 #define NGBE_VFSTATUS_UP MS(0, 0x1) 947 #define NGBE_VFSTATUS_BW_MASK MS(1, 0x7) 948 #define NGBE_VFSTATUS_BW_1G LS(0x1, 1, 0x7) 949 #define NGBE_VFSTATUS_BW_100M LS(0x2, 1, 0x7) 950 #define NGBE_VFSTATUS_BW_10M LS(0x4, 1, 0x7) 951 #define NGBE_VFSTATUS_BUSY MS(4, 0x1) 952 #define NGBE_VFSTATUS_LANID MS(8, 0x3) 953 #define NGBE_VFRST 0x000008 954 #define NGBE_VFRST_SET MS(0, 0x1) 955 #define NGBE_VFMSIXECC 0x00000C 956 #define NGBE_VFPLCFG 0x000078 957 #define NGBE_VFPLCFG_RSV MS(0, 0x1) 958 #define NGBE_VFPLCFG_PSR(v) LS(v, 1, 0x1F) 959 #define NGBE_VFPLCFG_PSRL4HDR (0x1) 960 #define NGBE_VFPLCFG_PSRL3HDR (0x2) 961 #define NGBE_VFPLCFG_PSRL2HDR (0x4) 962 #define NGBE_VFPLCFG_PSRTUNHDR (0x8) 963 #define NGBE_VFPLCFG_PSRTUNMAC (0x10) 964 #define NGBE_VFICR 0x000100 965 #define NGBE_VFICR_MASK LS(3, 0, 0x3) 966 #define NGBE_VFICR_MBX MS(1, 0x1) 967 #define NGBE_VFICR_DONE1 MS(0, 0x1) 968 #define NGBE_VFICS 0x000104 969 #define NGBE_VFICS_MASK NGBE_VFICR_MASK 970 #define NGBE_VFIMS 0x000108 971 #define NGBE_VFIMS_MASK NGBE_VFICR_MASK 972 #define NGBE_VFIMC 0x00010C 973 #define NGBE_VFIMC_MASK NGBE_VFICR_MASK 974 #define NGBE_VFGPIE 0x000118 975 #define NGBE_VFIVAR(i) (0x000240 + 4 * (i)) /*0-1*/ 976 #define NGBE_VFIVARMISC 0x000260 977 #define NGBE_VFIVAR_ALLOC(v) LS(v, 0, 0x1) 978 #define NGBE_VFIVAR_VLD MS(7, 0x1) 979 980 #define NGBE_VFMBCTL 0x000600 981 #define NGBE_VFMBCTL_REQ MS(0, 0x1) /* Request for PF Ready bit */ 982 #define NGBE_VFMBCTL_ACK MS(1, 0x1) /* Ack PF message received */ 983 #define NGBE_VFMBCTL_VFU MS(2, 0x1) /* VF owns the mailbox buffer */ 984 #define NGBE_VFMBCTL_PFU MS(3, 0x1) /* PF owns the mailbox buffer */ 985 #define NGBE_VFMBCTL_PFSTS MS(4, 0x1) /* PF wrote a message in the MB */ 986 #define NGBE_VFMBCTL_PFACK MS(5, 0x1) /* PF ack the previous VF msg */ 987 #define NGBE_VFMBCTL_RSTI MS(6, 0x1) /* PF has reset indication */ 988 #define NGBE_VFMBCTL_RSTD MS(7, 0x1) /* PF has indicated reset done */ 989 #define NGBE_VFMBCTL_R2C_BITS (NGBE_VFMBCTL_RSTD | \ 990 NGBE_VFMBCTL_PFSTS | \ 991 NGBE_VFMBCTL_PFACK) 992 #define NGBE_VFMBX 0x000C00 /*0-15*/ 993 #define NGBE_VFTPHCTL(i) 0x000D00 994 995 /****************************************************************************** 996 * PF&VF TxRx Interface 997 ******************************************************************************/ 998 #define RNGLEN(v) ROUND_OVER(v, 13, 7) 999 #define HDRLEN(v) ROUND_OVER(v, 10, 6) 1000 #define PKTLEN(v) ROUND_OVER(v, 14, 10) 1001 #define INTTHR(v) ROUND_OVER(v, 4, 0) 1002 1003 #define NGBE_RING_DESC_ALIGN 128 1004 #define NGBE_RING_DESC_MIN 128 1005 #define NGBE_RING_DESC_MAX 8192 1006 #define NGBE_RXD_ALIGN NGBE_RING_DESC_ALIGN 1007 #define NGBE_TXD_ALIGN NGBE_RING_DESC_ALIGN 1008 1009 /* receive ring */ 1010 #define NGBE_RXBAL(rp) (0x001000 + 0x40 * (rp)) 1011 #define NGBE_RXBAH(rp) (0x001004 + 0x40 * (rp)) 1012 #define NGBE_RXRP(rp) (0x00100C + 0x40 * (rp)) 1013 #define NGBE_RXWP(rp) (0x001008 + 0x40 * (rp)) 1014 #define NGBE_RXCFG(rp) (0x001010 + 0x40 * (rp)) 1015 #define NGBE_RXCFG_ENA MS(0, 0x1) 1016 #define NGBE_RXCFG_RNGLEN(v) LS(RNGLEN(v), 1, 0x3F) 1017 #define NGBE_RXCFG_PKTLEN(v) LS(PKTLEN(v), 8, 0xF) 1018 #define NGBE_RXCFG_PKTLEN_MASK MS(8, 0xF) 1019 #define NGBE_RXCFG_HDRLEN(v) LS(HDRLEN(v), 12, 0xF) 1020 #define NGBE_RXCFG_HDRLEN_MASK MS(12, 0xF) 1021 #define NGBE_RXCFG_WTHRESH(v) LS(v, 16, 0x7) 1022 #define NGBE_RXCFG_ETAG MS(22, 0x1) 1023 #define NGBE_RXCFG_SPLIT MS(26, 0x1) 1024 #define NGBE_RXCFG_CNTAG MS(28, 0x1) 1025 #define NGBE_RXCFG_DROP MS(30, 0x1) 1026 #define NGBE_RXCFG_VLAN MS(31, 0x1) 1027 1028 /* transmit ring */ 1029 #define NGBE_TXBAL(rp) (0x003000 + 0x40 * (rp)) /*0-7*/ 1030 #define NGBE_TXBAH(rp) (0x003004 + 0x40 * (rp)) 1031 #define NGBE_TXWP(rp) (0x003008 + 0x40 * (rp)) 1032 #define NGBE_TXRP(rp) (0x00300C + 0x40 * (rp)) 1033 #define NGBE_TXCFG(rp) (0x003010 + 0x40 * (rp)) 1034 #define NGBE_TXCFG_ENA MS(0, 0x1) 1035 #define NGBE_TXCFG_BUFLEN_MASK MS(1, 0x3F) 1036 #define NGBE_TXCFG_BUFLEN(v) LS(RNGLEN(v), 1, 0x3F) 1037 #define NGBE_TXCFG_HTHRESH_MASK MS(8, 0xF) 1038 #define NGBE_TXCFG_HTHRESH(v) LS(v, 8, 0xF) 1039 #define NGBE_TXCFG_WTHRESH_MASK MS(16, 0x7F) 1040 #define NGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F) 1041 #define NGBE_TXCFG_FLUSH MS(26, 0x1) 1042 1043 /* interrupt registers */ 1044 #define NGBE_BMEPEND 0x000168 1045 #define NGBE_BMEPEND_ST MS(0, 0x1) 1046 #define NGBE_ITRI 0x000180 1047 #define NGBE_ITR(i) (0x000200 + 4 * (i)) 1048 #define NGBE_ITR_IVAL_MASK MS(2, 0x1FFF) /* 1ns/10G, 10ns/REST */ 1049 #define NGBE_ITR_IVAL(v) LS(v, 2, 0x1FFF) /*1ns/10G, 10ns/REST*/ 1050 #define NGBE_ITR_IVAL_1G(us) NGBE_ITR_IVAL((us) / 2) 1051 #define NGBE_ITR_IVAL_10G(us) NGBE_ITR_IVAL((us) / 20) 1052 #define NGBE_ITR_LLIEA MS(15, 0x1) 1053 #define NGBE_ITR_LLICREDIT(v) LS(v, 16, 0x1F) 1054 #define NGBE_ITR_CNT(v) LS(v, 21, 0x3FF) 1055 #define NGBE_ITR_WRDSA MS(31, 0x1) 1056 #define NGBE_GPIE 0x000118 1057 #define NGBE_GPIE_MSIX MS(0, 0x1) 1058 #define NGBE_GPIE_LLIEA MS(1, 0x1) 1059 #define NGBE_GPIE_LLIVAL(v) LS(v, 3, 0x1F) 1060 #define NGBE_GPIE_LLIVAL_H(v) LS(v, 16, 0x7FF) 1061 1062 /****************************************************************************** 1063 * Debug Registers 1064 ******************************************************************************/ 1065 /** 1066 * Probe 1067 **/ 1068 #define NGBE_PRBCTL 0x010200 1069 #define NGBE_PRBSTA 0x010204 1070 #define NGBE_PRBDAT 0x010220 1071 #define NGBE_PRBCNT 0x010228 1072 1073 #define NGBE_PRBPCI 0x01F010 1074 #define NGBE_PRBPSR 0x015010 1075 #define NGBE_PRBRDB 0x019010 1076 #define NGBE_PRBTDB 0x01C010 1077 #define NGBE_PRBRSEC 0x017010 1078 #define NGBE_PRBTSEC 0x01D010 1079 #define NGBE_PRBMNG 0x01E010 1080 #define NGBE_PRBRMAC 0x011014 1081 #define NGBE_PRBTMAC 0x011010 1082 #define NGBE_PRBREMAC 0x011E04 1083 #define NGBE_PRBTEMAC 0x011E00 1084 1085 /** 1086 * ECC 1087 **/ 1088 #define NGBE_ECCRXPBCTL 0x019014 1089 #define NGBE_ECCRXPBINJ 0x019018 1090 #define NGBE_ECCRXPB 0x01901C 1091 #define NGBE_ECCTXPBCTL 0x01C014 1092 #define NGBE_ECCTXPBINJ 0x01C018 1093 #define NGBE_ECCTXPB 0x01C01C 1094 1095 #define NGBE_ECCRXETHCTL 0x015014 1096 #define NGBE_ECCRXETHINJ 0x015018 1097 #define NGBE_ECCRXETH 0x01401C 1098 1099 #define NGBE_ECCRXSECCTL 0x017014 1100 #define NGBE_ECCRXSECINJ 0x017018 1101 #define NGBE_ECCRXSEC 0x01701C 1102 #define NGBE_ECCTXSECCTL 0x01D014 1103 #define NGBE_ECCTXSECINJ 0x01D018 1104 #define NGBE_ECCTXSEC 0x01D01C 1105 1106 #define NGBE_P2VMBX_SIZE (16) /* 16*4B */ 1107 #define NGBE_P2MMBX_SIZE (64) /* 64*4B */ 1108 1109 /**************** Global Registers ****************************/ 1110 #define NGBE_POOLETHCTL(pl) (0x015600 + (pl) * 4) 1111 #define NGBE_POOLETHCTL_LBDIA MS(0, 0x1) 1112 #define NGBE_POOLETHCTL_LLBDIA MS(1, 0x1) 1113 #define NGBE_POOLETHCTL_LLB MS(2, 0x1) 1114 #define NGBE_POOLETHCTL_UCP MS(4, 0x1) 1115 #define NGBE_POOLETHCTL_ETP MS(5, 0x1) 1116 #define NGBE_POOLETHCTL_VLA MS(6, 0x1) 1117 #define NGBE_POOLETHCTL_VLP MS(7, 0x1) 1118 #define NGBE_POOLETHCTL_UTA MS(8, 0x1) 1119 #define NGBE_POOLETHCTL_MCHA MS(9, 0x1) 1120 #define NGBE_POOLETHCTL_UCHA MS(10, 0x1) 1121 #define NGBE_POOLETHCTL_BCA MS(11, 0x1) 1122 #define NGBE_POOLETHCTL_MCP MS(12, 0x1) 1123 #define NGBE_POOLDROPSWBK(i) (0x0151C8 + (i) * 4) /*0-1*/ 1124 1125 /**************************** Receive DMA registers **************************/ 1126 1127 #define NGBE_RPUP2TC 0x019008 1128 #define NGBE_RPUP2TC_UP_SHIFT 3 1129 #define NGBE_RPUP2TC_UP_MASK 0x7 1130 1131 /* mac switcher */ 1132 #define NGBE_ETHADDRL 0x016200 1133 #define NGBE_ETHADDRL_AD0(v) LS(v, 0, 0xFF) 1134 #define NGBE_ETHADDRL_AD1(v) LS(v, 8, 0xFF) 1135 #define NGBE_ETHADDRL_AD2(v) LS(v, 16, 0xFF) 1136 #define NGBE_ETHADDRL_AD3(v) LS(v, 24, 0xFF) 1137 #define NGBE_ETHADDRL_ETAG(r) RS(r, 0, 0x3FFF) 1138 #define NGBE_ETHADDRH 0x016204 1139 #define NGBE_ETHADDRH_AD4(v) LS(v, 0, 0xFF) 1140 #define NGBE_ETHADDRH_AD5(v) LS(v, 8, 0xFF) 1141 #define NGBE_ETHADDRH_AD_MASK MS(0, 0xFFFF) 1142 #define NGBE_ETHADDRH_ETAG MS(30, 0x1) 1143 #define NGBE_ETHADDRH_VLD MS(31, 0x1) 1144 #define NGBE_ETHADDRASS 0x016208 1145 #define NGBE_ETHADDRIDX 0x016210 1146 1147 /* Outmost Barrier Filters */ 1148 #define NGBE_MCADDRTBL(i) (0x015200 + (i) * 4) /*0-127*/ 1149 #define NGBE_UCADDRTBL(i) (0x015400 + (i) * 4) /*0-127*/ 1150 #define NGBE_VLANTBL(i) (0x016000 + (i) * 4) /*0-127*/ 1151 1152 #define NGBE_MNGFLEXSEL 0x1582C 1153 #define NGBE_MNGFLEXDWL(i) (0x15A00 + ((i) * 16)) 1154 #define NGBE_MNGFLEXDWH(i) (0x15A04 + ((i) * 16)) 1155 #define NGBE_MNGFLEXMSK(i) (0x15A08 + ((i) * 16)) 1156 1157 #define NGBE_LANFLEXSEL 0x15B8C 1158 #define NGBE_LANFLEXDWL(i) (0x15C00 + ((i) * 16)) 1159 #define NGBE_LANFLEXDWH(i) (0x15C04 + ((i) * 16)) 1160 #define NGBE_LANFLEXMSK(i) (0x15C08 + ((i) * 16)) 1161 #define NGBE_LANFLEXCTL 0x15CFC 1162 1163 /* ipsec */ 1164 #define NGBE_IPSRXIDX 0x017100 1165 #define NGBE_IPSRXIDX_ENA MS(0, 0x1) 1166 #define NGBE_IPSRXIDX_TB_MASK MS(1, 0x3) 1167 #define NGBE_IPSRXIDX_TB_IP LS(1, 1, 0x3) 1168 #define NGBE_IPSRXIDX_TB_SPI LS(2, 1, 0x3) 1169 #define NGBE_IPSRXIDX_TB_KEY LS(3, 1, 0x3) 1170 #define NGBE_IPSRXIDX_TBIDX(v) LS(v, 3, 0xF) 1171 #define NGBE_IPSRXIDX_READ MS(30, 0x1) 1172 #define NGBE_IPSRXIDX_WRITE MS(31, 0x1) 1173 #define NGBE_IPSRXADDR(i) (0x017104 + (i) * 4) 1174 1175 #define NGBE_IPSRXSPI 0x017114 1176 #define NGBE_IPSRXADDRIDX 0x017118 1177 #define NGBE_IPSRXKEY(i) (0x01711C + (i) * 4) 1178 #define NGBE_IPSRXSALT 0x01712C 1179 #define NGBE_IPSRXMODE 0x017130 1180 #define NGBE_IPSRXMODE_IPV6 0x00000010 1181 #define NGBE_IPSRXMODE_DEC 0x00000008 1182 #define NGBE_IPSRXMODE_ESP 0x00000004 1183 #define NGBE_IPSRXMODE_AH 0x00000002 1184 #define NGBE_IPSRXMODE_VLD 0x00000001 1185 #define NGBE_IPSTXIDX 0x01D100 1186 #define NGBE_IPSTXIDX_ENA MS(0, 0x1) 1187 #define NGBE_IPSTXIDX_SAIDX(v) LS(v, 3, 0x3FF) 1188 #define NGBE_IPSTXIDX_READ MS(30, 0x1) 1189 #define NGBE_IPSTXIDX_WRITE MS(31, 0x1) 1190 #define NGBE_IPSTXSALT 0x01D104 1191 #define NGBE_IPSTXKEY(i) (0x01D108 + (i) * 4) 1192 1193 #define NGBE_MACTXCFG 0x011000 1194 #define NGBE_MACTXCFG_TE MS(0, 0x1) 1195 #define NGBE_MACTXCFG_SPEED_MASK MS(29, 0x3) 1196 #define NGBE_MACTXCFG_SPEED(v) LS(v, 29, 0x3) 1197 #define NGBE_MACTXCFG_SPEED_10G LS(0, 29, 0x3) 1198 #define NGBE_MACTXCFG_SPEED_1G LS(3, 29, 0x3) 1199 1200 #define NGBE_ISBADDRL 0x000160 1201 #define NGBE_ISBADDRH 0x000164 1202 1203 #define NGBE_ARBPOOLIDX 0x01820C 1204 #define NGBE_ARBTXRATE 0x018404 1205 #define NGBE_ARBTXRATE_MIN(v) LS(v, 0, 0x3FFF) 1206 #define NGBE_ARBTXRATE_MAX(v) LS(v, 16, 0x3FFF) 1207 1208 /* qos */ 1209 #define NGBE_ARBTXCTL 0x018200 1210 #define NGBE_ARBTXCTL_RRM MS(1, 0x1) 1211 #define NGBE_ARBTXCTL_WSP MS(2, 0x1) 1212 #define NGBE_ARBTXCTL_DIA MS(6, 0x1) 1213 #define NGBE_ARBTXMMW 0x018208 1214 1215 /* Management */ 1216 #define NGBE_MNGFWSYNC 0x01E000 1217 #define NGBE_MNGFWSYNC_REQ MS(0, 0x1) 1218 #define NGBE_MNGSWSYNC 0x01E004 1219 #define NGBE_MNGSWSYNC_REQ MS(0, 0x1) 1220 #define NGBE_SWSEM 0x01002C 1221 #define NGBE_SWSEM_PF MS(0, 0x1) 1222 #define NGBE_MNGSEM 0x01E008 1223 #define NGBE_MNGSEM_SW(v) LS(v, 0, 0xFFFF) 1224 #define NGBE_MNGSEM_SWPHY MS(0, 0x1) 1225 #define NGBE_MNGSEM_SWMBX MS(2, 0x1) 1226 #define NGBE_MNGSEM_SWFLASH MS(3, 0x1) 1227 #define NGBE_MNGSEM_FW(v) LS(v, 16, 0xFFFF) 1228 #define NGBE_MNGSEM_FWPHY MS(16, 0x1) 1229 #define NGBE_MNGSEM_FWMBX MS(18, 0x1) 1230 #define NGBE_MNGSEM_FWFLASH MS(19, 0x1) 1231 #define NGBE_MNGMBXCTL 0x01E044 1232 #define NGBE_MNGMBXCTL_SWRDY MS(0, 0x1) 1233 #define NGBE_MNGMBXCTL_SWACK MS(1, 0x1) 1234 #define NGBE_MNGMBXCTL_FWRDY MS(2, 0x1) 1235 #define NGBE_MNGMBXCTL_FWACK MS(3, 0x1) 1236 #define NGBE_MNGMBX 0x01E100 1237 1238 /** 1239 * MDIO(PHY) 1240 **/ 1241 #define NGBE_MDIOSCA 0x011200 1242 #define NGBE_MDIOSCA_REG(v) LS(v, 0, 0xFFFF) 1243 #define NGBE_MDIOSCA_PORT(v) LS(v, 16, 0x1F) 1244 #define NGBE_MDIOSCA_DEV(v) LS(v, 21, 0x1F) 1245 #define NGBE_MDIOSCD 0x011204 1246 #define NGBE_MDIOSCD_DAT_R(r) RS(r, 0, 0xFFFF) 1247 #define NGBE_MDIOSCD_DAT(v) LS(v, 0, 0xFFFF) 1248 #define NGBE_MDIOSCD_CMD_PREAD LS(2, 16, 0x3) 1249 #define NGBE_MDIOSCD_CMD_WRITE LS(1, 16, 0x3) 1250 #define NGBE_MDIOSCD_CMD_READ LS(3, 16, 0x3) 1251 #define NGBE_MDIOSCD_SADDR MS(18, 0x1) 1252 #define NGBE_MDIOSCD_CLOCK(v) LS(v, 19, 0x7) 1253 #define NGBE_MDIOSCD_BUSY MS(22, 0x1) 1254 1255 #define NGBE_MDIOMODE 0x011220 1256 #define NGBE_MDIOMODE_MASK MS(0, 0xF) 1257 #define NGBE_MDIOMODE_PRT3CL22 MS(3, 0x1) 1258 #define NGBE_MDIOMODE_PRT2CL22 MS(2, 0x1) 1259 #define NGBE_MDIOMODE_PRT1CL22 MS(1, 0x1) 1260 #define NGBE_MDIOMODE_PRT0CL22 MS(0, 0x1) 1261 1262 #define NGBE_LLDP_REG 0x0F1000 1263 1264 #define NVM_OROM_OFFSET 0x17 1265 #define NVM_OROM_BLK_LOW 0x83 1266 #define NVM_OROM_BLK_HI 0x84 1267 #define NVM_OROM_PATCH_MASK 0xFF 1268 #define NVM_OROM_SHIFT 8 1269 #define NVM_VER_MASK 0x00FF /* version mask */ 1270 #define NVM_VER_SHIFT 8 /* version bit shift */ 1271 #define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */ 1272 #define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */ 1273 #define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */ 1274 #define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */ 1275 #define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */ 1276 #define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */ 1277 #define NVM_ETK_OFF_LOW 0x2D /* version low order word */ 1278 #define NVM_ETK_OFF_HI 0x2E /* version high order word */ 1279 #define NVM_ETK_SHIFT 16 /* high version word shift */ 1280 #define NVM_VER_INVALID 0xFFFF 1281 #define NVM_ETK_VALID 0x8000 1282 #define NVM_INVALID_PTR 0xFFFF 1283 #define NVM_VER_SIZE 32 /* version string size */ 1284 1285 #define NGBE_REG_RSSTBL NGBE_RSSTBL(0) 1286 #define NGBE_REG_RSSKEY NGBE_RSSKEY(0) 1287 1288 /* 1289 * read non-rc counters 1290 */ 1291 #define NGBE_UPDCNT32(reg, last, cur) \ 1292 do { \ 1293 uint32_t latest = rd32(hw, reg); \ 1294 if (hw->offset_loaded || hw->rx_loaded) \ 1295 last = 0; \ 1296 cur += (latest - last) & UINT_MAX; \ 1297 last = latest; \ 1298 } while (0) 1299 1300 #define NGBE_UPDCNT36(regl, last, cur) \ 1301 do { \ 1302 uint64_t new_lsb = rd32(hw, regl); \ 1303 uint64_t new_msb = rd32(hw, regl + 4); \ 1304 uint64_t latest = ((new_msb << 32) | new_lsb); \ 1305 if (hw->offset_loaded || hw->rx_loaded) \ 1306 last = 0; \ 1307 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 1308 last = latest; \ 1309 } while (0) 1310 1311 /** 1312 * register operations 1313 **/ 1314 #define NGBE_REG_READ32(addr) rte_read32(addr) 1315 #define NGBE_REG_READ32_RELAXED(addr) rte_read32_relaxed(addr) 1316 #define NGBE_REG_WRITE32(addr, val) rte_write32(val, addr) 1317 #define NGBE_REG_WRITE32_RELAXED(addr, val) rte_write32_relaxed(val, addr) 1318 1319 #define NGBE_DEAD_READ_REG 0xdeadbeefU 1320 #define NGBE_FAILED_READ_REG 0xffffffffU 1321 #define NGBE_REG_ADDR(hw, reg) \ 1322 ((volatile u32 *)((char *)(hw)->hw_addr + (reg))) 1323 1324 static inline u32 1325 ngbe_get32(volatile u32 *addr) 1326 { 1327 u32 val = NGBE_REG_READ32(addr); 1328 return rte_le_to_cpu_32(val); 1329 } 1330 1331 static inline void 1332 ngbe_set32(volatile u32 *addr, u32 val) 1333 { 1334 val = rte_cpu_to_le_32(val); 1335 NGBE_REG_WRITE32(addr, val); 1336 } 1337 1338 static inline u32 1339 ngbe_get32_masked(volatile u32 *addr, u32 mask) 1340 { 1341 u32 val = ngbe_get32(addr); 1342 val &= mask; 1343 return val; 1344 } 1345 1346 static inline void 1347 ngbe_set32_masked(volatile u32 *addr, u32 mask, u32 field) 1348 { 1349 u32 val = ngbe_get32(addr); 1350 val = ((val & ~mask) | (field & mask)); 1351 ngbe_set32(addr, val); 1352 } 1353 1354 static inline u32 1355 ngbe_get32_relaxed(volatile u32 *addr) 1356 { 1357 u32 val = NGBE_REG_READ32_RELAXED(addr); 1358 return rte_le_to_cpu_32(val); 1359 } 1360 1361 static inline void 1362 ngbe_set32_relaxed(volatile u32 *addr, u32 val) 1363 { 1364 val = rte_cpu_to_le_32(val); 1365 NGBE_REG_WRITE32_RELAXED(addr, val); 1366 } 1367 1368 static inline u32 1369 rd32(struct ngbe_hw *hw, u32 reg) 1370 { 1371 if (reg == NGBE_REG_DUMMY) 1372 return 0; 1373 return ngbe_get32(NGBE_REG_ADDR(hw, reg)); 1374 } 1375 1376 static inline void 1377 wr32(struct ngbe_hw *hw, u32 reg, u32 val) 1378 { 1379 if (reg == NGBE_REG_DUMMY) 1380 return; 1381 ngbe_set32(NGBE_REG_ADDR(hw, reg), val); 1382 } 1383 1384 static inline u32 1385 rd32m(struct ngbe_hw *hw, u32 reg, u32 mask) 1386 { 1387 u32 val = rd32(hw, reg); 1388 val &= mask; 1389 return val; 1390 } 1391 1392 static inline void 1393 wr32m(struct ngbe_hw *hw, u32 reg, u32 mask, u32 field) 1394 { 1395 u32 val = rd32(hw, reg); 1396 val = ((val & ~mask) | (field & mask)); 1397 wr32(hw, reg, val); 1398 } 1399 1400 static inline u64 1401 rd64(struct ngbe_hw *hw, u32 reg) 1402 { 1403 u64 lsb = rd32(hw, reg); 1404 u64 msb = rd32(hw, reg + 4); 1405 return (lsb | msb << 32); 1406 } 1407 1408 static inline void 1409 wr64(struct ngbe_hw *hw, u32 reg, u64 val) 1410 { 1411 wr32(hw, reg, (u32)val); 1412 wr32(hw, reg + 4, (u32)(val >> 32)); 1413 } 1414 1415 /* poll register */ 1416 static inline u32 1417 po32m(struct ngbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, 1418 u32 loop, u32 slice) 1419 { 1420 bool usec = true; 1421 u32 value = 0, all = 0; 1422 1423 if (slice > 1000 * MAX_UDELAY_MS) { 1424 usec = false; 1425 slice = (slice + 500) / 1000; 1426 } 1427 1428 do { 1429 if (expect != 0) { 1430 all |= rd32(hw, reg); 1431 value |= mask & all; 1432 } else { 1433 all = rd32(hw, reg); 1434 value = mask & all; 1435 } 1436 if (value == expect) 1437 break; 1438 1439 usec ? usec_delay(slice) : msec_delay(slice); 1440 } while (--loop > 0); 1441 1442 if (actual) 1443 *actual = all; 1444 1445 return loop; 1446 } 1447 1448 /* flush all write operations */ 1449 #define ngbe_flush(hw) rd32(hw, 0x00100C) 1450 1451 #define rd32a(hw, reg, idx) ( \ 1452 rd32((hw), (reg) + ((idx) << 2))) 1453 #define wr32a(hw, reg, idx, val) \ 1454 wr32((hw), (reg) + ((idx) << 2), (val)) 1455 1456 #define rd32w(hw, reg, mask, slice) do { \ 1457 rd32((hw), reg); \ 1458 po32m((hw), reg, mask, mask, NULL, 5, slice); \ 1459 } while (0) 1460 1461 #define wr32w(hw, reg, val, mask, slice) do { \ 1462 wr32((hw), reg, val); \ 1463 po32m((hw), reg, mask, mask, NULL, 5, slice); \ 1464 } while (0) 1465 1466 #define NGBE_XPCS_IDAADDR 0x13000 1467 #define NGBE_XPCS_IDADATA 0x13004 1468 #define NGBE_EPHY_IDAADDR 0x13008 1469 #define NGBE_EPHY_IDADATA 0x1300C 1470 static inline u32 1471 rd32_epcs(struct ngbe_hw *hw, u32 addr) 1472 { 1473 u32 data; 1474 wr32(hw, NGBE_XPCS_IDAADDR, addr); 1475 data = rd32(hw, NGBE_XPCS_IDADATA); 1476 return data; 1477 } 1478 1479 static inline void 1480 wr32_epcs(struct ngbe_hw *hw, u32 addr, u32 data) 1481 { 1482 wr32(hw, NGBE_XPCS_IDAADDR, addr); 1483 wr32(hw, NGBE_XPCS_IDADATA, data); 1484 } 1485 1486 static inline u32 1487 rd32_ephy(struct ngbe_hw *hw, u32 addr) 1488 { 1489 u32 data; 1490 wr32(hw, NGBE_EPHY_IDAADDR, addr); 1491 data = rd32(hw, NGBE_EPHY_IDADATA); 1492 return data; 1493 } 1494 1495 static inline void 1496 wr32_ephy(struct ngbe_hw *hw, u32 addr, u32 data) 1497 { 1498 wr32(hw, NGBE_EPHY_IDAADDR, addr); 1499 wr32(hw, NGBE_EPHY_IDADATA, data); 1500 } 1501 1502 #endif /* _NGBE_REGS_H_ */ 1503