1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2022 NVIDIA Corporation & Affiliates 3 */ 4 5 #ifndef MLX5DR_DEFINER_H_ 6 #define MLX5DR_DEFINER_H_ 7 8 /* Max available selecotrs */ 9 #define DW_SELECTORS 9 10 #define BYTE_SELECTORS 8 11 12 /* Selectors based on match TAG */ 13 #define DW_SELECTORS_MATCH 6 14 #define DW_SELECTORS_LIMITED 3 15 16 /* Selectors based on range TAG */ 17 #define DW_SELECTORS_RANGE 2 18 #define BYTE_SELECTORS_RANGE 8 19 20 enum mlx5dr_definer_compare_ste_dw_offset { 21 /* In compare STE the matching DW's starts after the 3 actions */ 22 MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_1 = 3, 23 MLX5DR_DEFINER_COMPARE_STE_ARGUMENT_0, 24 MLX5DR_DEFINER_COMPARE_STE_BASE_1, 25 MLX5DR_DEFINER_COMPARE_STE_BASE_0, 26 MLX5DR_DEFINER_COMPARE_STE_TAG_DW_3, 27 MLX5DR_DEFINER_COMPARE_STE_TAG_DW_2, 28 MLX5DR_DEFINER_COMPARE_STE_TAG_DW_1, 29 MLX5DR_DEFINER_COMPARE_STE_TAG_DW_0, 30 }; 31 32 enum mlx5dr_definer_dw_selectors { 33 MLX5DR_DEFINER_SELECTOR_DW0, 34 MLX5DR_DEFINER_SELECTOR_DW1, 35 MLX5DR_DEFINER_SELECTOR_DW2, 36 MLX5DR_DEFINER_SELECTOR_DW3, 37 MLX5DR_DEFINER_SELECTOR_DW4, 38 MLX5DR_DEFINER_SELECTOR_DW5, 39 MLX5DR_DEFINER_SELECTOR_DW6, 40 MLX5DR_DEFINER_SELECTOR_DW7, 41 MLX5DR_DEFINER_SELECTOR_DW8, 42 }; 43 44 enum mlx5dr_definer_compare_dw_selectors { 45 MLX5DR_DEFINER_COMPARE_ARGUMENT_0 = MLX5DR_DEFINER_SELECTOR_DW4, 46 MLX5DR_DEFINER_COMPARE_ARGUMENT_1 = MLX5DR_DEFINER_SELECTOR_DW5, 47 MLX5DR_DEFINER_COMPARE_BASE_0 = MLX5DR_DEFINER_SELECTOR_DW2, 48 MLX5DR_DEFINER_COMPARE_BASE_1 = MLX5DR_DEFINER_SELECTOR_DW3, 49 }; 50 51 enum mlx5dr_definer_fname { 52 MLX5DR_DEFINER_FNAME_ETH_SMAC_48_16_O, 53 MLX5DR_DEFINER_FNAME_ETH_SMAC_48_16_I, 54 MLX5DR_DEFINER_FNAME_ETH_SMAC_15_0_O, 55 MLX5DR_DEFINER_FNAME_ETH_SMAC_15_0_I, 56 MLX5DR_DEFINER_FNAME_ETH_DMAC_48_16_O, 57 MLX5DR_DEFINER_FNAME_ETH_DMAC_48_16_I, 58 MLX5DR_DEFINER_FNAME_ETH_DMAC_15_0_O, 59 MLX5DR_DEFINER_FNAME_ETH_DMAC_15_0_I, 60 MLX5DR_DEFINER_FNAME_ETH_TYPE_O, 61 MLX5DR_DEFINER_FNAME_ETH_TYPE_I, 62 MLX5DR_DEFINER_FNAME_VLAN_TYPE_O, 63 MLX5DR_DEFINER_FNAME_VLAN_TYPE_I, 64 MLX5DR_DEFINER_FNAME_VLAN_TCI_O, 65 MLX5DR_DEFINER_FNAME_VLAN_TCI_I, 66 MLX5DR_DEFINER_FNAME_IPV4_IHL_O, 67 MLX5DR_DEFINER_FNAME_IPV4_IHL_I, 68 MLX5DR_DEFINER_FNAME_IP_TTL_O, 69 MLX5DR_DEFINER_FNAME_IP_TTL_I, 70 MLX5DR_DEFINER_FNAME_IPV4_DST_O, 71 MLX5DR_DEFINER_FNAME_IPV4_DST_I, 72 MLX5DR_DEFINER_FNAME_IPV4_SRC_O, 73 MLX5DR_DEFINER_FNAME_IPV4_SRC_I, 74 MLX5DR_DEFINER_FNAME_IP_VERSION_O, 75 MLX5DR_DEFINER_FNAME_IP_VERSION_I, 76 MLX5DR_DEFINER_FNAME_IP_FRAG_O, 77 MLX5DR_DEFINER_FNAME_IP_FRAG_I, 78 MLX5DR_DEFINER_FNAME_IP_ID_O, 79 MLX5DR_DEFINER_FNAME_IP_ID_I, 80 MLX5DR_DEFINER_FNAME_IP_LEN_O, 81 MLX5DR_DEFINER_FNAME_IP_LEN_I, 82 MLX5DR_DEFINER_FNAME_IP_TOS_O, 83 MLX5DR_DEFINER_FNAME_IP_TOS_I, 84 MLX5DR_DEFINER_FNAME_IPV6_FLOW_LABEL_O, 85 MLX5DR_DEFINER_FNAME_IPV6_FLOW_LABEL_I, 86 MLX5DR_DEFINER_FNAME_IPV6_DST_127_96_O, 87 MLX5DR_DEFINER_FNAME_IPV6_DST_95_64_O, 88 MLX5DR_DEFINER_FNAME_IPV6_DST_63_32_O, 89 MLX5DR_DEFINER_FNAME_IPV6_DST_31_0_O, 90 MLX5DR_DEFINER_FNAME_IPV6_DST_127_96_I, 91 MLX5DR_DEFINER_FNAME_IPV6_DST_95_64_I, 92 MLX5DR_DEFINER_FNAME_IPV6_DST_63_32_I, 93 MLX5DR_DEFINER_FNAME_IPV6_DST_31_0_I, 94 MLX5DR_DEFINER_FNAME_IPV6_SRC_127_96_O, 95 MLX5DR_DEFINER_FNAME_IPV6_SRC_95_64_O, 96 MLX5DR_DEFINER_FNAME_IPV6_SRC_63_32_O, 97 MLX5DR_DEFINER_FNAME_IPV6_SRC_31_0_O, 98 MLX5DR_DEFINER_FNAME_IPV6_SRC_127_96_I, 99 MLX5DR_DEFINER_FNAME_IPV6_SRC_95_64_I, 100 MLX5DR_DEFINER_FNAME_IPV6_SRC_63_32_I, 101 MLX5DR_DEFINER_FNAME_IPV6_SRC_31_0_I, 102 MLX5DR_DEFINER_FNAME_IP_PROTOCOL_O, 103 MLX5DR_DEFINER_FNAME_IP_PROTOCOL_I, 104 MLX5DR_DEFINER_FNAME_L4_SPORT_O, 105 MLX5DR_DEFINER_FNAME_L4_SPORT_I, 106 MLX5DR_DEFINER_FNAME_L4_DPORT_O, 107 MLX5DR_DEFINER_FNAME_L4_DPORT_I, 108 MLX5DR_DEFINER_FNAME_TCP_FLAGS_I, 109 MLX5DR_DEFINER_FNAME_TCP_FLAGS_O, 110 MLX5DR_DEFINER_FNAME_GTP_TEID, 111 MLX5DR_DEFINER_FNAME_GTP_MSG_TYPE, 112 MLX5DR_DEFINER_FNAME_GTP_EXT_FLAG, 113 MLX5DR_DEFINER_FNAME_GTP_NEXT_EXT_HDR, 114 MLX5DR_DEFINER_FNAME_GTP_EXT_HDR_PDU, 115 MLX5DR_DEFINER_FNAME_GTP_EXT_HDR_QFI, 116 MLX5DR_DEFINER_FNAME_FLEX_PARSER_0, 117 MLX5DR_DEFINER_FNAME_FLEX_PARSER_1, 118 MLX5DR_DEFINER_FNAME_FLEX_PARSER_2, 119 MLX5DR_DEFINER_FNAME_FLEX_PARSER_3, 120 MLX5DR_DEFINER_FNAME_FLEX_PARSER_4, 121 MLX5DR_DEFINER_FNAME_FLEX_PARSER_5, 122 MLX5DR_DEFINER_FNAME_FLEX_PARSER_6, 123 MLX5DR_DEFINER_FNAME_FLEX_PARSER_7, 124 MLX5DR_DEFINER_FNAME_VPORT_REG_C_0, 125 MLX5DR_DEFINER_FNAME_VXLAN_DW0, 126 MLX5DR_DEFINER_FNAME_VXLAN_DW1, 127 MLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS, 128 MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0, 129 MLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO, 130 MLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI, 131 MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1, 132 MLX5DR_DEFINER_FNAME_GENEVE_CTRL, 133 MLX5DR_DEFINER_FNAME_GENEVE_PROTO, 134 MLX5DR_DEFINER_FNAME_GENEVE_VNI, 135 MLX5DR_DEFINER_FNAME_SOURCE_QP, 136 MLX5DR_DEFINER_FNAME_REG_0, 137 MLX5DR_DEFINER_FNAME_REG_1, 138 MLX5DR_DEFINER_FNAME_REG_2, 139 MLX5DR_DEFINER_FNAME_REG_3, 140 MLX5DR_DEFINER_FNAME_REG_4, 141 MLX5DR_DEFINER_FNAME_REG_5, 142 MLX5DR_DEFINER_FNAME_REG_6, 143 MLX5DR_DEFINER_FNAME_REG_7, 144 MLX5DR_DEFINER_FNAME_REG_8, 145 MLX5DR_DEFINER_FNAME_REG_9, 146 MLX5DR_DEFINER_FNAME_REG_10, 147 MLX5DR_DEFINER_FNAME_REG_11, 148 MLX5DR_DEFINER_FNAME_REG_A, 149 MLX5DR_DEFINER_FNAME_REG_B, 150 MLX5DR_DEFINER_FNAME_GRE_KEY_PRESENT, 151 MLX5DR_DEFINER_FNAME_GRE_C_VER, 152 MLX5DR_DEFINER_FNAME_GRE_PROTOCOL, 153 MLX5DR_DEFINER_FNAME_GRE_OPT_KEY, 154 MLX5DR_DEFINER_FNAME_GRE_OPT_SEQ, 155 MLX5DR_DEFINER_FNAME_GRE_OPT_CHECKSUM, 156 MLX5DR_DEFINER_FNAME_NVGRE_C_K_S, 157 MLX5DR_DEFINER_FNAME_NVGRE_PROTOCOL, 158 MLX5DR_DEFINER_FNAME_NVGRE_DW1, 159 MLX5DR_DEFINER_FNAME_INTEGRITY_O, 160 MLX5DR_DEFINER_FNAME_INTEGRITY_I, 161 MLX5DR_DEFINER_FNAME_ICMP_DW1, 162 MLX5DR_DEFINER_FNAME_ICMP_DW2, 163 MLX5DR_DEFINER_FNAME_ESP_SPI, 164 MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER, 165 MLX5DR_DEFINER_FNAME_MPLS0_O, 166 MLX5DR_DEFINER_FNAME_MPLS1_O, 167 MLX5DR_DEFINER_FNAME_MPLS2_O, 168 MLX5DR_DEFINER_FNAME_MPLS3_O, 169 MLX5DR_DEFINER_FNAME_MPLS4_O, 170 MLX5DR_DEFINER_FNAME_MPLS0_I, 171 MLX5DR_DEFINER_FNAME_MPLS1_I, 172 MLX5DR_DEFINER_FNAME_MPLS2_I, 173 MLX5DR_DEFINER_FNAME_MPLS3_I, 174 MLX5DR_DEFINER_FNAME_MPLS4_I, 175 MLX5DR_DEFINER_FNAME_OKS2_MPLS0_O, 176 MLX5DR_DEFINER_FNAME_OKS2_MPLS1_O, 177 MLX5DR_DEFINER_FNAME_OKS2_MPLS2_O, 178 MLX5DR_DEFINER_FNAME_OKS2_MPLS3_O, 179 MLX5DR_DEFINER_FNAME_OKS2_MPLS4_O, 180 MLX5DR_DEFINER_FNAME_OKS2_MPLS0_I, 181 MLX5DR_DEFINER_FNAME_OKS2_MPLS1_I, 182 MLX5DR_DEFINER_FNAME_OKS2_MPLS2_I, 183 MLX5DR_DEFINER_FNAME_OKS2_MPLS3_I, 184 MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I, 185 MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_0, 186 MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_1, 187 MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_2, 188 MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_3, 189 MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_4, 190 MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_5, 191 MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_6, 192 MLX5DR_DEFINER_FNAME_GENEVE_OPT_OK_7, 193 MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_0, 194 MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_1, 195 MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_2, 196 MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_3, 197 MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_4, 198 MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_5, 199 MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_6, 200 MLX5DR_DEFINER_FNAME_GENEVE_OPT_DW_7, 201 MLX5DR_DEFINER_FNAME_IB_L4_OPCODE, 202 MLX5DR_DEFINER_FNAME_IB_L4_QPN, 203 MLX5DR_DEFINER_FNAME_IB_L4_A, 204 MLX5DR_DEFINER_FNAME_PTYPE_L2_O, 205 MLX5DR_DEFINER_FNAME_PTYPE_L2_I, 206 MLX5DR_DEFINER_FNAME_PTYPE_L3_O, 207 MLX5DR_DEFINER_FNAME_PTYPE_L3_I, 208 MLX5DR_DEFINER_FNAME_PTYPE_L4_O, 209 MLX5DR_DEFINER_FNAME_PTYPE_L4_I, 210 MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_O, 211 MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_I, 212 MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL, 213 MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O, 214 MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I, 215 MLX5DR_DEFINER_FNAME_RANDOM_NUM, 216 MLX5DR_DEFINER_FNAME_MAX, 217 }; 218 219 enum mlx5dr_definer_type { 220 MLX5DR_DEFINER_TYPE_MATCH, 221 MLX5DR_DEFINER_TYPE_JUMBO, 222 MLX5DR_DEFINER_TYPE_RANGE, 223 }; 224 225 struct mlx5dr_definer_fc { 226 uint8_t item_idx; 227 uint8_t is_range; 228 uint8_t compare_idx; 229 bool compare_set_base; 230 union { 231 uint32_t extra_data; 232 void *dr_ctx; 233 }; 234 uint32_t byte_off; 235 int bit_off; 236 uint32_t bit_mask; 237 enum mlx5dr_definer_fname fname; 238 uint8_t not_overwrite; 239 void (*tag_set)(struct mlx5dr_definer_fc *fc, 240 const void *item_spec, 241 uint8_t *tag); 242 void (*tag_mask_set)(struct mlx5dr_definer_fc *fc, 243 const void *item_spec, 244 uint8_t *tag); 245 }; 246 247 struct mlx5_ifc_definer_hl_eth_l2_bits { 248 u8 dmac_47_16[0x20]; 249 u8 dmac_15_0[0x10]; 250 u8 l3_ethertype[0x10]; 251 u8 reserved_at_40[0x1]; 252 u8 sx_sniffer[0x1]; 253 u8 functional_lb[0x1]; 254 u8 ip_fragmented[0x1]; 255 u8 qp_type[0x2]; 256 u8 encap_type[0x2]; 257 u8 port_number[0x2]; 258 u8 l3_type[0x2]; 259 u8 l4_type_bwc[0x2]; 260 u8 first_vlan_qualifier[0x2]; 261 u8 tci[0x10]; /* contains first_priority[0x3] + first_cfi[0x1] + first_vlan_id[0xc] */ 262 u8 l4_type[0x4]; 263 u8 reserved_at_64[0x2]; 264 u8 ipsec_layer[0x2]; 265 u8 l2_type[0x2]; 266 u8 force_lb[0x1]; 267 u8 l2_ok[0x1]; 268 u8 l3_ok[0x1]; 269 u8 l4_ok[0x1]; 270 u8 second_vlan_qualifier[0x2]; 271 u8 second_priority[0x3]; 272 u8 second_cfi[0x1]; 273 u8 second_vlan_id[0xc]; 274 }; 275 276 struct mlx5_ifc_definer_hl_eth_l2_src_bits { 277 u8 smac_47_16[0x20]; 278 u8 smac_15_0[0x10]; 279 u8 loopback_syndrome[0x8]; 280 u8 l3_type[0x2]; 281 u8 l4_type_bwc[0x2]; 282 u8 first_vlan_qualifier[0x2]; 283 u8 ip_fragmented[0x1]; 284 u8 functional_lb[0x1]; 285 }; 286 287 struct mlx5_ifc_definer_hl_ib_l2_bits { 288 u8 sx_sniffer[0x1]; 289 u8 force_lb[0x1]; 290 u8 functional_lb[0x1]; 291 u8 reserved_at_3[0x3]; 292 u8 port_number[0x2]; 293 u8 sl[0x4]; 294 u8 qp_type[0x2]; 295 u8 lnh[0x2]; 296 u8 dlid[0x10]; 297 u8 vl[0x4]; 298 u8 lrh_packet_length[0xc]; 299 u8 slid[0x10]; 300 }; 301 302 struct mlx5_ifc_definer_hl_eth_l3_bits { 303 u8 ip_version[0x4]; 304 u8 ihl[0x4]; 305 union { 306 u8 tos[0x8]; 307 struct { 308 u8 dscp[0x6]; 309 u8 ecn[0x2]; 310 }; 311 }; 312 u8 time_to_live_hop_limit[0x8]; 313 u8 protocol_next_header[0x8]; 314 u8 identification[0x10]; 315 union { 316 u8 ipv4_frag[0x10]; 317 struct { 318 u8 flags[0x3]; 319 u8 fragment_offset[0xd]; 320 }; 321 }; 322 u8 ipv4_total_length[0x10]; 323 u8 checksum[0x10]; 324 u8 reserved_at_60[0xc]; 325 u8 flow_label[0x14]; 326 u8 packet_length[0x10]; 327 u8 ipv6_payload_length[0x10]; 328 }; 329 330 struct mlx5_ifc_definer_hl_eth_l4_bits { 331 u8 source_port[0x10]; 332 u8 destination_port[0x10]; 333 u8 data_offset[0x4]; 334 u8 l4_ok[0x1]; 335 u8 l3_ok[0x1]; 336 u8 ip_fragmented[0x1]; 337 u8 tcp_ns[0x1]; 338 union { 339 u8 tcp_flags[0x8]; 340 struct { 341 u8 tcp_cwr[0x1]; 342 u8 tcp_ece[0x1]; 343 u8 tcp_urg[0x1]; 344 u8 tcp_ack[0x1]; 345 u8 tcp_psh[0x1]; 346 u8 tcp_rst[0x1]; 347 u8 tcp_syn[0x1]; 348 u8 tcp_fin[0x1]; 349 }; 350 }; 351 u8 first_fragment[0x1]; 352 u8 reserved_at_31[0xf]; 353 }; 354 355 struct mlx5_ifc_definer_hl_src_qp_gvmi_bits { 356 u8 loopback_syndrome[0x8]; 357 u8 l3_type[0x2]; 358 u8 l4_type_bwc[0x2]; 359 u8 first_vlan_qualifier[0x2]; 360 u8 reserved_at_e[0x1]; 361 u8 functional_lb[0x1]; 362 u8 source_gvmi[0x10]; 363 u8 force_lb[0x1]; 364 u8 ip_fragmented[0x1]; 365 u8 source_is_requestor[0x1]; 366 u8 reserved_at_23[0x5]; 367 u8 source_qp[0x18]; 368 }; 369 370 struct mlx5_ifc_definer_hl_ib_l4_bits { 371 u8 opcode[0x8]; 372 u8 qp[0x18]; 373 u8 se[0x1]; 374 u8 migreq[0x1]; 375 u8 ackreq[0x1]; 376 u8 fecn[0x1]; 377 u8 becn[0x1]; 378 u8 bth[0x1]; 379 u8 deth[0x1]; 380 u8 dcceth[0x1]; 381 u8 reserved_at_28[0x2]; 382 u8 pad_count[0x2]; 383 u8 tver[0x4]; 384 u8 p_key[0x10]; 385 u8 reserved_at_40[0x8]; 386 u8 deth_source_qp[0x18]; 387 }; 388 389 enum mlx5dr_integrity_ok1_bits { 390 MLX5DR_DEFINER_OKS1_FIRST_L4_OK = 24, 391 MLX5DR_DEFINER_OKS1_FIRST_L3_OK = 25, 392 MLX5DR_DEFINER_OKS1_SECOND_L4_OK = 26, 393 MLX5DR_DEFINER_OKS1_SECOND_L3_OK = 27, 394 MLX5DR_DEFINER_OKS1_FIRST_L4_CSUM_OK = 28, 395 MLX5DR_DEFINER_OKS1_FIRST_IPV4_CSUM_OK = 29, 396 MLX5DR_DEFINER_OKS1_SECOND_L4_CSUM_OK = 30, 397 MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK = 31, 398 }; 399 400 struct mlx5_ifc_definer_hl_oks1_bits { 401 union { 402 u8 oks1_bits[0x20]; 403 struct { 404 u8 second_ipv4_checksum_ok[0x1]; 405 u8 second_l4_checksum_ok[0x1]; 406 u8 first_ipv4_checksum_ok[0x1]; 407 u8 first_l4_checksum_ok[0x1]; 408 u8 second_l3_ok[0x1]; 409 u8 second_l4_ok[0x1]; 410 u8 first_l3_ok[0x1]; 411 u8 first_l4_ok[0x1]; 412 u8 flex_parser7_steering_ok[0x1]; 413 u8 flex_parser6_steering_ok[0x1]; 414 u8 flex_parser5_steering_ok[0x1]; 415 u8 flex_parser4_steering_ok[0x1]; 416 u8 flex_parser3_steering_ok[0x1]; 417 u8 flex_parser2_steering_ok[0x1]; 418 u8 flex_parser1_steering_ok[0x1]; 419 u8 flex_parser0_steering_ok[0x1]; 420 u8 second_ipv6_extension_header_vld[0x1]; 421 u8 first_ipv6_extension_header_vld[0x1]; 422 u8 l3_tunneling_ok[0x1]; 423 u8 l2_tunneling_ok[0x1]; 424 u8 second_tcp_ok[0x1]; 425 u8 second_udp_ok[0x1]; 426 u8 second_ipv4_ok[0x1]; 427 u8 second_ipv6_ok[0x1]; 428 u8 second_l2_ok[0x1]; 429 u8 vxlan_ok[0x1]; 430 u8 gre_ok[0x1]; 431 u8 first_tcp_ok[0x1]; 432 u8 first_udp_ok[0x1]; 433 u8 first_ipv4_ok[0x1]; 434 u8 first_ipv6_ok[0x1]; 435 u8 first_l2_ok[0x1]; 436 }; 437 }; 438 }; 439 440 struct mlx5_ifc_definer_hl_oks2_bits { 441 u8 reserved_at_0[0xa]; 442 u8 second_mpls_ok[0x1]; 443 u8 second_mpls4_s_bit[0x1]; 444 u8 second_mpls4_qualifier[0x1]; 445 u8 second_mpls3_s_bit[0x1]; 446 u8 second_mpls3_qualifier[0x1]; 447 u8 second_mpls2_s_bit[0x1]; 448 u8 second_mpls2_qualifier[0x1]; 449 u8 second_mpls1_s_bit[0x1]; 450 u8 second_mpls1_qualifier[0x1]; 451 u8 second_mpls0_s_bit[0x1]; 452 u8 second_mpls0_qualifier[0x1]; 453 u8 first_mpls_ok[0x1]; 454 u8 first_mpls4_s_bit[0x1]; 455 u8 first_mpls4_qualifier[0x1]; 456 u8 first_mpls3_s_bit[0x1]; 457 u8 first_mpls3_qualifier[0x1]; 458 u8 first_mpls2_s_bit[0x1]; 459 u8 first_mpls2_qualifier[0x1]; 460 u8 first_mpls1_s_bit[0x1]; 461 u8 first_mpls1_qualifier[0x1]; 462 u8 first_mpls0_s_bit[0x1]; 463 u8 first_mpls0_qualifier[0x1]; 464 }; 465 466 struct mlx5_ifc_definer_hl_voq_bits { 467 u8 reserved_at_0[0x18]; 468 u8 ecn_ok[0x1]; 469 u8 congestion[0x1]; 470 u8 profile[0x2]; 471 u8 internal_prio[0x4]; 472 }; 473 474 struct mlx5_ifc_definer_hl_ipv4_src_dst_bits { 475 u8 source_address[0x20]; 476 u8 destination_address[0x20]; 477 }; 478 479 struct mlx5_ifc_definer_hl_random_number_bits { 480 u8 random_number[0x10]; 481 u8 reserved[0x10]; 482 }; 483 484 struct mlx5_ifc_definer_hl_ipv6_addr_bits { 485 u8 ipv6_address_127_96[0x20]; 486 u8 ipv6_address_95_64[0x20]; 487 u8 ipv6_address_63_32[0x20]; 488 u8 ipv6_address_31_0[0x20]; 489 }; 490 491 struct mlx5_ifc_definer_tcp_icmp_header_bits { 492 union { 493 struct { 494 u8 icmp_dw1[0x20]; 495 u8 icmp_dw2[0x20]; 496 u8 icmp_dw3[0x20]; 497 }; 498 struct { 499 u8 tcp_seq[0x20]; 500 u8 tcp_ack[0x20]; 501 u8 tcp_win_urg[0x20]; 502 }; 503 }; 504 }; 505 506 struct mlx5_ifc_definer_hl_tunnel_header_bits { 507 u8 tunnel_header_0[0x20]; 508 u8 tunnel_header_1[0x20]; 509 u8 tunnel_header_2[0x20]; 510 u8 tunnel_header_3[0x20]; 511 }; 512 513 struct mlx5_ifc_definer_hl_ipsec_bits { 514 u8 spi[0x20]; 515 u8 sequence_number[0x20]; 516 u8 reserved[0x10]; 517 u8 ipsec_syndrome[0x8]; 518 u8 next_header[0x8]; 519 }; 520 521 struct mlx5_ifc_definer_hl_metadata_bits { 522 u8 metadata_to_cqe[0x20]; 523 u8 general_purpose[0x20]; 524 u8 acomulated_hash[0x20]; 525 }; 526 527 struct mlx5_ifc_definer_hl_flex_parser_bits { 528 u8 flex_parser_7[0x20]; 529 u8 flex_parser_6[0x20]; 530 u8 flex_parser_5[0x20]; 531 u8 flex_parser_4[0x20]; 532 u8 flex_parser_3[0x20]; 533 u8 flex_parser_2[0x20]; 534 u8 flex_parser_1[0x20]; 535 u8 flex_parser_0[0x20]; 536 }; 537 538 struct mlx5_ifc_definer_hl_registers_bits { 539 u8 register_c_10[0x20]; 540 u8 register_c_11[0x20]; 541 u8 register_c_8[0x20]; 542 u8 register_c_9[0x20]; 543 u8 register_c_6[0x20]; 544 u8 register_c_7[0x20]; 545 u8 register_c_4[0x20]; 546 u8 register_c_5[0x20]; 547 u8 register_c_2[0x20]; 548 u8 register_c_3[0x20]; 549 u8 register_c_0[0x20]; 550 u8 register_c_1[0x20]; 551 }; 552 553 struct mlx5_ifc_definer_hl_mpls_bits { 554 u8 mpls0_label[0x20]; 555 u8 mpls1_label[0x20]; 556 u8 mpls2_label[0x20]; 557 u8 mpls3_label[0x20]; 558 u8 mpls4_label[0x20]; 559 }; 560 561 struct mlx5_ifc_definer_hl_bits { 562 struct mlx5_ifc_definer_hl_eth_l2_bits eth_l2_outer; 563 struct mlx5_ifc_definer_hl_eth_l2_bits eth_l2_inner; 564 struct mlx5_ifc_definer_hl_eth_l2_src_bits eth_l2_src_outer; 565 struct mlx5_ifc_definer_hl_eth_l2_src_bits eth_l2_src_inner; 566 struct mlx5_ifc_definer_hl_ib_l2_bits ib_l2; 567 struct mlx5_ifc_definer_hl_eth_l3_bits eth_l3_outer; 568 struct mlx5_ifc_definer_hl_eth_l3_bits eth_l3_inner; 569 struct mlx5_ifc_definer_hl_eth_l4_bits eth_l4_outer; 570 struct mlx5_ifc_definer_hl_eth_l4_bits eth_l4_inner; 571 struct mlx5_ifc_definer_hl_src_qp_gvmi_bits source_qp_gvmi; 572 struct mlx5_ifc_definer_hl_ib_l4_bits ib_l4; 573 struct mlx5_ifc_definer_hl_oks1_bits oks1; 574 struct mlx5_ifc_definer_hl_oks2_bits oks2; 575 struct mlx5_ifc_definer_hl_voq_bits voq; 576 u8 reserved_at_480[0x380]; 577 struct mlx5_ifc_definer_hl_ipv4_src_dst_bits ipv4_src_dest_outer; 578 struct mlx5_ifc_definer_hl_ipv4_src_dst_bits ipv4_src_dest_inner; 579 struct mlx5_ifc_definer_hl_ipv6_addr_bits ipv6_dst_outer; 580 struct mlx5_ifc_definer_hl_ipv6_addr_bits ipv6_dst_inner; 581 struct mlx5_ifc_definer_hl_ipv6_addr_bits ipv6_src_outer; 582 struct mlx5_ifc_definer_hl_ipv6_addr_bits ipv6_src_inner; 583 u8 unsupported_dest_ib_l3[0x80]; 584 u8 unsupported_source_ib_l3[0x80]; 585 u8 unsupported_udp_misc_outer[0x20]; 586 u8 unsupported_udp_misc_inner[0x20]; 587 struct mlx5_ifc_definer_tcp_icmp_header_bits tcp_icmp; 588 struct mlx5_ifc_definer_hl_tunnel_header_bits tunnel_header; 589 struct mlx5_ifc_definer_hl_mpls_bits mpls_outer; 590 struct mlx5_ifc_definer_hl_mpls_bits mpls_inner; 591 u8 unsupported_config_headers_outer[0x80]; 592 u8 unsupported_config_headers_inner[0x80]; 593 struct mlx5_ifc_definer_hl_random_number_bits random_number; 594 struct mlx5_ifc_definer_hl_ipsec_bits ipsec; 595 struct mlx5_ifc_definer_hl_metadata_bits metadata; 596 u8 unsupported_utc_timestamp[0x40]; 597 u8 unsupported_free_running_timestamp[0x40]; 598 struct mlx5_ifc_definer_hl_flex_parser_bits flex_parser; 599 struct mlx5_ifc_definer_hl_registers_bits registers; 600 /* Reserved in case header layout on future HW */ 601 u8 unsupported_reserved[0xd40]; 602 }; 603 604 enum mlx5dr_definer_gtp { 605 MLX5DR_DEFINER_GTP_EXT_HDR_BIT = 0x04, 606 }; 607 608 struct mlx5_ifc_header_gtp_bits { 609 u8 version[0x3]; 610 u8 proto_type[0x1]; 611 u8 reserved1[0x1]; 612 u8 ext_hdr_flag[0x1]; 613 u8 seq_num_flag[0x1]; 614 u8 pdu_flag[0x1]; 615 u8 msg_type[0x8]; 616 u8 msg_len[0x8]; 617 u8 teid[0x20]; 618 }; 619 620 struct mlx5_ifc_header_opt_gtp_bits { 621 u8 seq_num[0x10]; 622 u8 pdu_num[0x8]; 623 u8 next_ext_hdr_type[0x8]; 624 }; 625 626 struct mlx5_ifc_header_gtp_psc_bits { 627 u8 len[0x8]; 628 u8 pdu_type[0x4]; 629 u8 flags[0x4]; 630 u8 qfi[0x8]; 631 u8 reserved2[0x8]; 632 }; 633 634 struct mlx5_ifc_header_ipv6_vtc_bits { 635 u8 version[0x4]; 636 union { 637 u8 tos[0x8]; 638 struct { 639 u8 dscp[0x6]; 640 u8 ecn[0x2]; 641 }; 642 }; 643 u8 flow_label[0x14]; 644 }; 645 646 struct mlx5_ifc_header_ipv6_routing_ext_bits { 647 u8 next_hdr[0x8]; 648 u8 hdr_len[0x8]; 649 u8 type[0x8]; 650 u8 segments_left[0x8]; 651 union { 652 u8 flags[0x20]; 653 struct { 654 u8 last_entry[0x8]; 655 u8 flag[0x8]; 656 u8 tag[0x10]; 657 }; 658 }; 659 }; 660 661 struct mlx5_ifc_header_vxlan_bits { 662 u8 flags[0x8]; 663 u8 reserved1[0x18]; 664 u8 vni[0x18]; 665 u8 reserved2[0x8]; 666 }; 667 668 struct mlx5_ifc_header_vxlan_gpe_bits { 669 u8 flags[0x8]; 670 u8 rsvd0[0x10]; 671 u8 protocol[0x8]; 672 u8 vni[0x18]; 673 u8 rsvd1[0x8]; 674 }; 675 676 struct mlx5_ifc_header_gre_bits { 677 union { 678 u8 c_rsvd0_ver[0x10]; 679 struct { 680 u8 gre_c_present[0x1]; 681 u8 reserved_at_1[0x1]; 682 u8 gre_k_present[0x1]; 683 u8 gre_s_present[0x1]; 684 u8 reserved_at_4[0x9]; 685 u8 version[0x3]; 686 }; 687 }; 688 u8 gre_protocol[0x10]; 689 u8 checksum[0x10]; 690 u8 reserved_at_30[0x10]; 691 }; 692 693 struct mlx5_ifc_header_geneve_bits { 694 union { 695 u8 ver_opt_len_o_c_rsvd[0x10]; 696 struct { 697 u8 version[0x2]; 698 u8 opt_len[0x6]; 699 u8 o_flag[0x1]; 700 u8 c_flag[0x1]; 701 u8 reserved_at_a[0x6]; 702 }; 703 }; 704 u8 protocol_type[0x10]; 705 u8 vni[0x18]; 706 u8 reserved_at_38[0x8]; 707 }; 708 709 struct mlx5_ifc_header_geneve_opt_bits { 710 u8 class[0x10]; 711 u8 type[0x8]; 712 u8 reserved[0x3]; 713 u8 len[0x5]; 714 }; 715 716 struct mlx5_ifc_header_icmp_bits { 717 union { 718 u8 icmp_dw1[0x20]; 719 struct { 720 u8 type[0x8]; 721 u8 code[0x8]; 722 u8 cksum[0x10]; 723 }; 724 }; 725 union { 726 u8 icmp_dw2[0x20]; 727 struct { 728 u8 ident[0x10]; 729 u8 seq_nb[0x10]; 730 }; 731 }; 732 }; 733 734 struct mlx5dr_definer { 735 enum mlx5dr_definer_type type; 736 uint8_t dw_selector[DW_SELECTORS]; 737 uint8_t byte_selector[BYTE_SELECTORS]; 738 struct mlx5dr_rule_match_tag mask; 739 struct mlx5dr_devx_obj *obj; 740 }; 741 742 struct mlx5dr_definer_cache { 743 LIST_HEAD(definer_head, mlx5dr_definer_cache_item) head; 744 }; 745 746 struct mlx5dr_definer_cache_item { 747 struct mlx5dr_definer definer; 748 uint32_t refcount; 749 LIST_ENTRY(mlx5dr_definer_cache_item) next; 750 }; 751 752 static inline bool 753 mlx5dr_definer_is_jumbo(struct mlx5dr_definer *definer) 754 { 755 return (definer->type == MLX5DR_DEFINER_TYPE_JUMBO); 756 } 757 758 void mlx5dr_definer_create_tag(const struct rte_flow_item *items, 759 struct mlx5dr_definer_fc *fc, 760 uint32_t fc_sz, 761 uint8_t *tag); 762 763 void mlx5dr_definer_create_tag_range(const struct rte_flow_item *items, 764 struct mlx5dr_definer_fc *fc, 765 uint32_t fc_sz, 766 uint8_t *tag); 767 768 int mlx5dr_definer_get_id(struct mlx5dr_definer *definer); 769 770 int mlx5dr_definer_matcher_init(struct mlx5dr_context *ctx, 771 struct mlx5dr_matcher *matcher); 772 773 void mlx5dr_definer_matcher_uninit(struct mlx5dr_matcher *matcher); 774 775 int mlx5dr_definer_init_cache(struct mlx5dr_definer_cache **cache); 776 777 void mlx5dr_definer_uninit_cache(struct mlx5dr_definer_cache *cache); 778 779 int mlx5dr_definer_compare(struct mlx5dr_definer *definer_a, 780 struct mlx5dr_definer *definer_b); 781 782 #endif 783