1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2023 NVIDIA Corporation & Affiliates 3 */ 4 5 #ifndef MLX5DR_BWC_H_ 6 #define MLX5DR_BWC_H_ 7 8 #define MLX5DR_BWC_MATCHER_INIT_SIZE_LOG 1 9 #define MLX5DR_BWC_MATCHER_SIZE_LOG_STEP 1 10 #define MLX5DR_BWC_MATCHER_REHASH_PERCENT_TH 70 11 #define MLX5DR_BWC_MATCHER_REHASH_BURST_TH 32 12 #define MLX5DR_BWC_MATCHER_ATTACH_AT_NUM 255 13 14 struct mlx5dr_bwc_matcher { 15 struct mlx5dr_matcher *matcher; 16 struct mlx5dr_match_template *mt; 17 struct mlx5dr_action_template *at[MLX5DR_BWC_MATCHER_ATTACH_AT_NUM]; 18 uint8_t num_of_at; 19 uint32_t priority; 20 uint8_t size_log; 21 RTE_ATOMIC(uint32_t)num_of_rules; /* atomically accessed */ 22 LIST_HEAD(rule_head, mlx5dr_bwc_rule) * rules; 23 }; 24 25 struct mlx5dr_bwc_rule { 26 struct mlx5dr_bwc_matcher *bwc_matcher; 27 struct mlx5dr_rule *rule; 28 struct rte_flow_item *flow_items; 29 uint16_t bwc_queue_idx; 30 LIST_ENTRY(mlx5dr_bwc_rule) next; 31 }; 32 33 #endif /* MLX5DR_BWC_H_ */ 34