1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019-2024 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <rte_common.h> 7 8 #include "cfa_resource_types.h" 9 #include "tf_device.h" 10 #include "tf_identifier.h" 11 #include "tf_tbl.h" 12 #include "tf_tcam.h" 13 #include "tf_tcam_shared.h" 14 #include "tf_em.h" 15 #include "tf_if_tbl.h" 16 #include "tfp.h" 17 #include "tf_msg_common.h" 18 #include "tf_msg.h" 19 #include "tf_tbl_sram.h" 20 #include "tf_util.h" 21 #include "tf_resources.h" 22 23 #define TF_DEV_P58_PARIF_MAX 16 24 #define TF_DEV_P58_PF_MASK 0xfUL 25 26 /* For print alignment, make all entries 8 chars in this table */ 27 const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = { 28 [CFA_RESOURCE_TYPE_P58_METER] = "meter ", 29 [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = "sram_bk0", 30 [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = "sram_bk1", 31 [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = "sram_bk2", 32 [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = "sram_bk3", 33 [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = "l2ctx_hi", 34 [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = "l2ctx_lo", 35 [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = "l2ctr_hi", 36 [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = "l2ctr_lo", 37 [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = "prf_func", 38 [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = "prf_tcam", 39 [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = "em_prof ", 40 [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = "wc_prof ", 41 [CFA_RESOURCE_TYPE_P58_EM_REC] = "em_rec ", 42 [CFA_RESOURCE_TYPE_P58_WC_TCAM] = "wc_tcam ", 43 [CFA_RESOURCE_TYPE_P58_METER_PROF] = "mtr_prof", 44 [CFA_RESOURCE_TYPE_P58_MIRROR] = "mirror ", 45 [CFA_RESOURCE_TYPE_P58_EM_FKB] = "em_fkb ", 46 [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ", 47 [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ", 48 [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata", 49 [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc", 50 }; 51 52 struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { 53 [TF_DIR_RX][TF_TBL_TYPE_EM_FKB] = { 54 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, 55 0, 0 56 }, 57 [TF_DIR_RX][TF_TBL_TYPE_WC_FKB] = { 58 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, 59 0, 0 60 }, 61 [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { 62 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, 63 0, 0 64 }, 65 [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { 66 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, 67 0, 0 68 }, 69 [TF_DIR_RX][TF_TBL_TYPE_METER_DROP_CNT] = { 70 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, 71 0, 0 72 }, 73 [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { 74 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, 75 0, 0 76 }, 77 [TF_DIR_RX][TF_TBL_TYPE_METADATA] = { 78 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, 79 0, 0 80 }, 81 /* Policy - ARs in bank 1 */ 82 [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { 83 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, 84 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, 85 .slices = 8, 86 }, 87 [TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { 88 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 89 .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, 90 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, 91 .slices = 16, 92 }, 93 /* Policy - Encaps in bank 2 */ 94 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { 95 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, 96 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 97 .slices = 16, 98 }, 99 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { 100 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 101 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 102 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 103 .slices = 8, 104 }, 105 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = { 106 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 107 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 108 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 109 .slices = 4, 110 }, 111 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { 112 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 113 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 114 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 115 .slices = 2, 116 }, 117 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_128B] = { 118 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 119 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 120 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 121 .slices = 1, 122 }, 123 /* Policy - Modify in bank 2 with Encaps */ 124 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_8B] = { 125 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 126 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 127 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 128 .slices = 16, 129 }, 130 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = { 131 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 132 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 133 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 134 .slices = 8, 135 }, 136 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = { 137 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 138 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 139 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 140 .slices = 4, 141 }, 142 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = { 143 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 144 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 145 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 146 .slices = 2, 147 }, 148 /* Policy - SP in bank 0 */ 149 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { 150 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, 151 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, 152 .slices = 16, 153 }, 154 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { 155 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 156 .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, 157 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, 158 .slices = 8, 159 }, 160 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { 161 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 162 .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, 163 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, 164 .slices = 4, 165 }, 166 /* Policy - Stats in bank 3 */ 167 [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { 168 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, 169 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, 170 .slices = 16, 171 }, 172 [TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = { 173 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB, 174 0, 0 175 }, 176 [TF_DIR_TX][TF_TBL_TYPE_WC_FKB] = { 177 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB, 178 0, 0 179 }, 180 [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { 181 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF, 182 0, 0 183 }, 184 [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { 185 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER, 186 0, 0 187 }, 188 [TF_DIR_TX][TF_TBL_TYPE_METER_DROP_CNT] = { 189 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT, 190 0, 0 191 }, 192 [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { 193 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR, 194 0, 0 195 }, 196 [TF_DIR_TX][TF_TBL_TYPE_METADATA] = { 197 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA, 198 0, 0 199 }, 200 /* Policy - ARs in bank 1 */ 201 [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { 202 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, 203 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, 204 .slices = 8, 205 }, 206 [TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = { 207 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 208 .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD, 209 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, 210 .slices = 16, 211 }, 212 /* Policy - Encaps in bank 2 */ 213 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { 214 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, 215 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 216 .slices = 16, 217 }, 218 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { 219 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 220 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 221 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 222 .slices = 8, 223 }, 224 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = { 225 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 226 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 227 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 228 .slices = 4, 229 }, 230 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { 231 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 232 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 233 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 234 .slices = 2, 235 }, 236 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_128B] = { 237 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 238 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 239 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 240 .slices = 1, 241 }, 242 /* Policy - Modify in bank 2 with Encaps */ 243 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_8B] = { 244 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 245 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 246 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 247 .slices = 16, 248 }, 249 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = { 250 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 251 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 252 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 253 .slices = 8, 254 }, 255 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = { 256 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 257 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 258 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 259 .slices = 4, 260 }, 261 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = { 262 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 263 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B, 264 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 265 .slices = 2, 266 }, 267 /* Policy - SP in bank 0 */ 268 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { 269 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, 270 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, 271 .slices = 16, 272 }, 273 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { 274 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 275 .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, 276 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, 277 .slices = 8, 278 }, 279 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { 280 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD, 281 .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC, 282 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, 283 .slices = 4, 284 }, 285 /* Policy - Stats in bank 3 */ 286 [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { 287 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT, 288 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3, 289 .slices = 16, 290 }, 291 }; 292 293 /** 294 * Device specific function that retrieves the MAX number of HCAPI 295 * types the device supports. 296 * 297 * [in] tfp 298 * Pointer to TF handle 299 * 300 * [out] max_types 301 * Pointer to the MAX number of HCAPI types supported 302 * 303 * Returns 304 * - (0) if successful. 305 * - (-EINVAL) on failure. 306 */ 307 static int 308 tf_dev_p58_get_max_types(struct tf *tfp, 309 uint16_t *max_types) 310 { 311 if (max_types == NULL || tfp == NULL) 312 return -EINVAL; 313 314 *max_types = CFA_RESOURCE_TYPE_P58_LAST + 1; 315 316 return 0; 317 } 318 /** 319 * Device specific function that retrieves a human readable 320 * string to identify a CFA resource type. 321 * 322 * [in] tfp 323 * Pointer to TF handle 324 * 325 * [in] resource_id 326 * HCAPI CFA resource id 327 * 328 * [out] resource_str 329 * Resource string 330 * 331 * Returns 332 * - (0) if successful. 333 * - (-EINVAL) on failure. 334 */ 335 static int 336 tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused, 337 uint16_t resource_id, 338 const char **resource_str) 339 { 340 if (resource_str == NULL) 341 return -EINVAL; 342 343 if (resource_id > CFA_RESOURCE_TYPE_P58_LAST) 344 return -EINVAL; 345 346 *resource_str = tf_resource_str_p58[resource_id]; 347 348 return 0; 349 } 350 351 /** 352 * Device specific function that set the WC TCAM slices the 353 * device supports. 354 * 355 * [in] tfp 356 * Pointer to TF handle 357 * 358 * [in] num_slices_per_row 359 * The WC TCAM row slice configuration 360 * 361 * Returns 362 * - (0) if successful. 363 * - (-EINVAL) on failure. 364 */ 365 static int 366 tf_dev_p58_set_tcam_slice_info(struct tf *tfp, 367 enum tf_wc_num_slice num_slices_per_row) 368 { 369 int rc; 370 struct tf_session *tfs = NULL; 371 372 /* Retrieve the session information */ 373 rc = tf_session_get_session_internal(tfp, &tfs); 374 if (rc) 375 return rc; 376 377 switch (num_slices_per_row) { 378 case TF_WC_TCAM_1_SLICE_PER_ROW: 379 case TF_WC_TCAM_2_SLICE_PER_ROW: 380 case TF_WC_TCAM_4_SLICE_PER_ROW: 381 tfs->wc_num_slices_per_row = num_slices_per_row; 382 break; 383 default: 384 return -EINVAL; 385 } 386 387 return 0; 388 } 389 390 /** 391 * Device specific function that retrieves the TCAM slices the 392 * device supports. 393 * 394 * [in] tfp 395 * Pointer to TF handle 396 * 397 * [in] type 398 * TF TCAM type 399 * 400 * [in] key_sz 401 * The key size 402 * 403 * [out] num_slices_per_row 404 * Pointer to the WC TCAM row slice configuration 405 * 406 * Returns 407 * - (0) if successful. 408 * - (-EINVAL) on failure. 409 */ 410 static int 411 tf_dev_p58_get_tcam_slice_info(struct tf *tfp, 412 enum tf_tcam_tbl_type type, 413 uint16_t key_sz, 414 uint16_t *num_slices_per_row) 415 { 416 int rc; 417 struct tf_session *tfs = NULL; 418 419 /* Retrieve the session information */ 420 rc = tf_session_get_session_internal(tfp, &tfs); 421 if (rc) 422 return rc; 423 424 #define CFA_P58_WC_TCAM_SLICE_SIZE (24) 425 if (type == TF_TCAM_TBL_TYPE_WC_TCAM) { 426 if (key_sz <= 1 * CFA_P58_WC_TCAM_SLICE_SIZE) 427 *num_slices_per_row = TF_WC_TCAM_1_SLICE_PER_ROW; 428 else if (key_sz <= 2 * CFA_P58_WC_TCAM_SLICE_SIZE) 429 *num_slices_per_row = TF_WC_TCAM_2_SLICE_PER_ROW; 430 else if (key_sz <= 4 * CFA_P58_WC_TCAM_SLICE_SIZE) 431 *num_slices_per_row = TF_WC_TCAM_4_SLICE_PER_ROW; 432 else 433 return -ENOTSUP; 434 } else { /* for other type of tcam */ 435 *num_slices_per_row = 1; 436 } 437 438 return 0; 439 } 440 441 static int tf_dev_p58_get_mailbox(void) 442 { 443 return TF_CHIMP_MB; 444 } 445 446 static int tf_dev_p58_word_align(uint16_t size) 447 { 448 return ((((size) + 63) >> 6) * 8); 449 } 450 451 /** 452 * Device specific function that retrieves the increment 453 * required for certain table types in a shared session 454 * 455 * [in] tfp 456 * tf handle 457 * 458 * [in/out] parms 459 * pointer to parms structure 460 * 461 * Returns 462 * - (0) if successful. 463 * - (-EINVAL) on failure. 464 */ 465 static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused, 466 struct tf_get_shared_tbl_increment_parms *parms) 467 { 468 switch (parms->type) { 469 case TF_TBL_TYPE_FULL_ACT_RECORD: 470 case TF_TBL_TYPE_COMPACT_ACT_RECORD: 471 case TF_TBL_TYPE_ACT_ENCAP_8B: 472 case TF_TBL_TYPE_ACT_ENCAP_16B: 473 case TF_TBL_TYPE_ACT_ENCAP_32B: 474 case TF_TBL_TYPE_ACT_ENCAP_64B: 475 case TF_TBL_TYPE_ACT_ENCAP_128B: 476 case TF_TBL_TYPE_ACT_SP_SMAC: 477 case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: 478 case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: 479 case TF_TBL_TYPE_ACT_STATS_64: 480 case TF_TBL_TYPE_ACT_MODIFY_IPV4: 481 case TF_TBL_TYPE_ACT_MODIFY_8B: 482 case TF_TBL_TYPE_ACT_MODIFY_16B: 483 case TF_TBL_TYPE_ACT_MODIFY_32B: 484 case TF_TBL_TYPE_ACT_MODIFY_64B: 485 parms->increment_cnt = 16; 486 break; 487 default: 488 parms->increment_cnt = 1; 489 break; 490 } 491 return 0; 492 } 493 494 /** 495 * Indicates whether the index table type is SRAM managed 496 * 497 * [in] tfp 498 * Pointer to TF handle 499 * 500 * [in] type 501 * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD 502 * 503 * Returns 504 * - (0) if the table is not managed by the SRAM manager 505 * - (1) if the table is managed by the SRAM manager 506 */ 507 static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused, 508 enum tf_tbl_type type) 509 { 510 switch (type) { 511 case TF_TBL_TYPE_FULL_ACT_RECORD: 512 case TF_TBL_TYPE_COMPACT_ACT_RECORD: 513 case TF_TBL_TYPE_ACT_ENCAP_8B: 514 case TF_TBL_TYPE_ACT_ENCAP_16B: 515 case TF_TBL_TYPE_ACT_ENCAP_32B: 516 case TF_TBL_TYPE_ACT_ENCAP_64B: 517 case TF_TBL_TYPE_ACT_ENCAP_128B: 518 case TF_TBL_TYPE_ACT_SP_SMAC: 519 case TF_TBL_TYPE_ACT_SP_SMAC_IPV4: 520 case TF_TBL_TYPE_ACT_SP_SMAC_IPV6: 521 case TF_TBL_TYPE_ACT_STATS_64: 522 case TF_TBL_TYPE_ACT_MODIFY_IPV4: 523 case TF_TBL_TYPE_ACT_MODIFY_8B: 524 case TF_TBL_TYPE_ACT_MODIFY_16B: 525 case TF_TBL_TYPE_ACT_MODIFY_32B: 526 case TF_TBL_TYPE_ACT_MODIFY_64B: 527 return true; 528 default: 529 return false; 530 } 531 } 532 533 #define TF_DEV_P58_BANK_SZ_64B 2048 534 /** 535 * Get SRAM table information. 536 * 537 * Converts an internal RM allocated element offset to 538 * a user address and vice versa. 539 * 540 * [in] tfp 541 * Pointer to TF handle 542 * 543 * [in] type 544 * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD 545 * 546 * [in/out] base 547 * Pointer to the Base address of the associated SRAM bank used for 548 * the type of record allocated. 549 * 550 * [in/out] shift 551 * Pointer to the factor to be used as a multiplier to translate 552 * between the RM units to the user address. SRAM manages 128B entries 553 * Addresses must be shifted to an 8B address. 554 * 555 * Returns 556 * - (0) if successful. 557 * - (-EINVAL) on failure. 558 */ 559 static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused, 560 void *db, 561 enum tf_tbl_type type, 562 uint16_t *base, 563 uint16_t *shift) 564 { 565 uint16_t hcapi_type; 566 struct tf_rm_get_hcapi_parms parms; 567 int rc; 568 569 parms.rm_db = db; 570 parms.subtype = type; 571 parms.hcapi_type = &hcapi_type; 572 573 rc = tf_rm_get_hcapi_type(&parms); 574 if (rc) { 575 *base = 0; 576 *shift = 0; 577 return 0; 578 } 579 580 switch (hcapi_type) { 581 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: 582 *base = 0; 583 *shift = 3; 584 break; 585 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1: 586 *base = TF_DEV_P58_BANK_SZ_64B; 587 *shift = 3; 588 break; 589 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2: 590 *base = TF_DEV_P58_BANK_SZ_64B * 2; 591 *shift = 3; 592 break; 593 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3: 594 *base = TF_DEV_P58_BANK_SZ_64B * 3; 595 *shift = 3; 596 break; 597 default: 598 *base = 0; 599 *shift = 0; 600 break; 601 } 602 return 0; 603 } 604 605 /** 606 * Device specific function that maps the hcapi resource types 607 * to Truflow type. 608 * 609 * [in] hcapi_caps 610 * CFA resource type bitmap 611 * 612 * [out] ident_caps 613 * Pointer to identifier type bitmap 614 * 615 * [out] tcam_caps 616 * Pointer to tcam type bitmap 617 * 618 * [out] tbl_caps 619 * Pointer to table type bitmap 620 * 621 * [out] em_caps 622 * Pointer to em type bitmap 623 * 624 * Returns 625 * - (0) if successful. 626 * - (-EINVAL) on failure. 627 */ 628 static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps, 629 uint32_t *ident_caps, 630 uint32_t *tcam_caps, 631 uint32_t *tbl_caps, 632 uint32_t *em_caps) 633 { 634 uint32_t i; 635 636 *ident_caps = 0; 637 *tcam_caps = 0; 638 *tbl_caps = 0; 639 *em_caps = 0; 640 641 for (i = 0; i <= CFA_RESOURCE_TYPE_P58_LAST; i++) { 642 if (hcapi_caps & 1ULL << i) { 643 switch (tf_hcapi_res_map_p58[i].module_type) { 644 case TF_MODULE_TYPE_IDENTIFIER: 645 *ident_caps |= tf_hcapi_res_map_p58[i].type_caps; 646 break; 647 case TF_MODULE_TYPE_TABLE: 648 *tbl_caps |= tf_hcapi_res_map_p58[i].type_caps; 649 break; 650 case TF_MODULE_TYPE_TCAM: 651 *tcam_caps |= tf_hcapi_res_map_p58[i].type_caps; 652 break; 653 case TF_MODULE_TYPE_EM: 654 *em_caps |= tf_hcapi_res_map_p58[i].type_caps; 655 break; 656 default: 657 return -EINVAL; 658 } 659 } 660 } 661 662 return 0; 663 } 664 665 /** 666 * Device specific function that retrieve the sram resource 667 * 668 * [in] query 669 * Point to resources query result 670 * 671 * [out] sram_bank_caps 672 * Pointer to SRAM bank capabilities 673 * 674 * [out] dynamic_sram_capable 675 * Pointer to dynamic sram capable 676 * 677 * Returns 678 * - (0) if successful. 679 * - (-EINVAL) on failure. 680 */ 681 static int tf_dev_p58_get_sram_resources(void *q, 682 uint32_t *sram_bank_caps, 683 bool *dynamic_sram_capable) 684 { 685 uint32_t i; 686 struct tf_rm_resc_req_entry *query = q; 687 688 for (i = 0; i < CFA_RESOURCE_TYPE_P58_LAST + 1; i++) { 689 switch (query[i].type) { 690 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0: 691 sram_bank_caps[0] = query[i].max; 692 break; 693 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1: 694 sram_bank_caps[1] = query[i].max; 695 break; 696 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2: 697 sram_bank_caps[2] = query[i].max; 698 break; 699 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3: 700 sram_bank_caps[3] = query[i].max; 701 break; 702 default: 703 break; 704 } 705 } 706 707 *dynamic_sram_capable = false; 708 709 return 0; 710 } 711 712 static int sram_bank_hcapi_type[] = { 713 CFA_RESOURCE_TYPE_P58_SRAM_BANK_0, 714 CFA_RESOURCE_TYPE_P58_SRAM_BANK_1, 715 CFA_RESOURCE_TYPE_P58_SRAM_BANK_2, 716 CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 717 }; 718 719 /** 720 * Device specific function that set the sram policy 721 * 722 * [in] dir 723 * Receive or transmit direction 724 * 725 * [in] band_id 726 * SRAM bank id 727 * 728 * Returns 729 * - (0) if successful. 730 * - (-EINVAL) on failure. 731 */ 732 static int tf_dev_p58_set_sram_policy(enum tf_dir dir, 733 enum tf_sram_bank_id *bank_id) 734 { 735 struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; 736 uint8_t type; 737 uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF }; 738 739 for (type = TF_TBL_TYPE_FULL_ACT_RECORD; 740 type <= TF_TBL_TYPE_ACT_MODIFY_64B; type++) { 741 if (bank_id[type] >= TF_SRAM_BANK_ID_MAX) 742 return -EINVAL; 743 744 rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]]; 745 if (parent[bank_id[type]] == 0xFF) { 746 parent[bank_id[type]] = type; 747 rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT; 748 rm_cfg[type].parent_subtype = 0; 749 if (rm_cfg[type].slices == 0) 750 rm_cfg[type].slices = 1; 751 } else { 752 rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD; 753 rm_cfg[type].parent_subtype = parent[bank_id[type]]; 754 } 755 } 756 757 return 0; 758 } 759 760 /** 761 * Device specific function that get the sram policy 762 * 763 * [in] dir 764 * Receive or transmit direction 765 * 766 * [out] band_id 767 * pointer to SRAM bank id 768 * 769 * Returns 770 * - (0) if successful. 771 * - (-EINVAL) on failure. 772 */ 773 static int tf_dev_p58_get_sram_policy(enum tf_dir dir, 774 enum tf_sram_bank_id *bank_id) 775 { 776 struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir]; 777 uint8_t type; 778 779 for (type = TF_TBL_TYPE_FULL_ACT_RECORD; 780 type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++) 781 bank_id[type] = rm_cfg[type].hcapi_type - CFA_RESOURCE_TYPE_P58_SRAM_BANK_0; 782 783 return 0; 784 } 785 786 #ifdef TF_FLOW_SCALE_QUERY 787 /** 788 * Update resource usage to firmware. 789 * 790 * [in] tfp 791 * Pointer to TF handle 792 * 793 * [in] dir 794 * Receive or transmit direction 795 * 796 * [in] flow_resc_type 797 * Types of the resource to update their usage state. 798 * 799 * Returns 800 * - (0) if successful. 801 * - (-EINVAL) on failure. 802 */ 803 static int tf_dev_p58_update_resc_usage(struct tf *tfp, 804 enum tf_dir dir, 805 enum tf_flow_resc_type flow_resc_type) 806 { 807 int rc; 808 809 struct cfa_tf_resc_usage *usage_state = &tf_resc_usage[dir]; 810 811 flow_resc_type |= HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ALL; 812 rc = tf_msg_set_resc_usage(tfp, 813 dir, 814 flow_resc_type, 815 sizeof(cfa_tf_resc_usage_t), 816 (uint8_t *)usage_state); 817 818 return rc; 819 } 820 821 /** 822 * Query resource usage from firmware. 823 * 824 * [in] tfp 825 * Pointer to TF handle 826 * 827 * [in/out] parms 828 * Pointer to parms structure 829 * 830 * Returns 831 * - (0) if successful. 832 * - (-EINVAL) on failure. 833 */ 834 static int tf_dev_p58_query_resc_usage(struct tf *tfp, 835 struct tf_query_resc_usage_parms *parms) 836 { 837 int rc = 0; 838 839 parms->size = sizeof(struct cfa_tf_resc_usage); 840 rc = tf_msg_query_resc_usage(tfp, 841 parms->dir, 842 parms->flow_resc_type, 843 &parms->size, 844 (void *)parms->data); 845 return rc; 846 } 847 848 /** 849 * Update buffer of table usage state 850 * 851 * [in] session_id 852 * Pointer to TF handle 853 * 854 * [in] dir 855 * Receive or transmit direction 856 * 857 * [in] tbl_type 858 * SRAM table type to update its usage state 859 * 860 * [in] resc_opt 861 * Alloca or free resource 862 * 863 * returns: 864 * 0 - Success 865 * -EINVAL - Error 866 */ 867 static int 868 tf_dev_p58_update_tbl_usage_buffer(struct tf *tfp, 869 enum tf_dir dir, 870 enum tf_tbl_type tbl_type, 871 enum tf_resc_opt resc_opt) 872 { 873 int rc; 874 rc = tf_tbl_usage_update(tfp, dir, tbl_type, resc_opt); 875 return rc; 876 } 877 #endif /* TF_FLOW_SCALE_QUERY */ 878 879 /** 880 * Truflow P58 device specific functions 881 */ 882 const struct tf_dev_ops tf_dev_ops_p58_init = { 883 .tf_dev_get_max_types = tf_dev_p58_get_max_types, 884 .tf_dev_get_resource_str = tf_dev_p58_get_resource_str, 885 .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info, 886 .tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info, 887 .tf_dev_alloc_ident = NULL, 888 .tf_dev_free_ident = NULL, 889 .tf_dev_search_ident = NULL, 890 .tf_dev_get_ident_resc_info = NULL, 891 .tf_dev_get_tbl_info = NULL, 892 .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed, 893 .tf_dev_alloc_ext_tbl = NULL, 894 .tf_dev_alloc_tbl = NULL, 895 .tf_dev_alloc_sram_tbl = NULL, 896 .tf_dev_free_ext_tbl = NULL, 897 .tf_dev_free_tbl = NULL, 898 .tf_dev_free_sram_tbl = NULL, 899 .tf_dev_set_tbl = NULL, 900 .tf_dev_set_ext_tbl = NULL, 901 .tf_dev_set_sram_tbl = NULL, 902 .tf_dev_get_tbl = NULL, 903 .tf_dev_get_sram_tbl = NULL, 904 .tf_dev_get_bulk_tbl = NULL, 905 .tf_dev_get_bulk_sram_tbl = NULL, 906 .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment, 907 .tf_dev_get_tbl_resc_info = NULL, 908 .tf_dev_alloc_tcam = NULL, 909 .tf_dev_free_tcam = NULL, 910 .tf_dev_alloc_search_tcam = NULL, 911 .tf_dev_set_tcam = NULL, 912 .tf_dev_get_tcam = NULL, 913 .tf_dev_get_tcam_resc_info = NULL, 914 .tf_dev_insert_int_em_entry = NULL, 915 .tf_dev_delete_int_em_entry = NULL, 916 .tf_dev_insert_ext_em_entry = NULL, 917 .tf_dev_delete_ext_em_entry = NULL, 918 .tf_dev_get_em_resc_info = NULL, 919 .tf_dev_alloc_tbl_scope = NULL, 920 .tf_dev_map_tbl_scope = NULL, 921 .tf_dev_map_parif = NULL, 922 .tf_dev_free_tbl_scope = NULL, 923 .tf_dev_set_if_tbl = NULL, 924 .tf_dev_get_if_tbl = NULL, 925 .tf_dev_set_global_cfg = NULL, 926 .tf_dev_get_global_cfg = NULL, 927 .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, 928 .tf_dev_word_align = NULL, 929 .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, 930 .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, 931 .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, 932 .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, 933 #ifdef TF_FLOW_SCALE_QUERY 934 .tf_dev_update_resc_usage = tf_dev_p58_update_resc_usage, 935 .tf_dev_query_resc_usage = tf_dev_p58_query_resc_usage, 936 .tf_dev_update_tbl_usage_buffer = tf_dev_p58_update_tbl_usage_buffer, 937 #endif /* TF_FLOW_SCALE_QUERY */ 938 }; 939 940 /** 941 * Truflow P58 device specific functions 942 */ 943 const struct tf_dev_ops tf_dev_ops_p58 = { 944 .tf_dev_get_max_types = tf_dev_p58_get_max_types, 945 .tf_dev_get_resource_str = tf_dev_p58_get_resource_str, 946 .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info, 947 .tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info, 948 .tf_dev_alloc_ident = tf_ident_alloc, 949 .tf_dev_free_ident = tf_ident_free, 950 .tf_dev_search_ident = tf_ident_search, 951 .tf_dev_get_ident_resc_info = tf_ident_get_resc_info, 952 .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed, 953 .tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info, 954 .tf_dev_alloc_tbl = tf_tbl_alloc, 955 .tf_dev_alloc_sram_tbl = tf_tbl_sram_alloc, 956 .tf_dev_alloc_ext_tbl = NULL, 957 .tf_dev_free_tbl = tf_tbl_free, 958 .tf_dev_free_ext_tbl = NULL, 959 .tf_dev_free_sram_tbl = tf_tbl_sram_free, 960 .tf_dev_set_tbl = tf_tbl_set, 961 .tf_dev_set_ext_tbl = NULL, 962 .tf_dev_set_sram_tbl = tf_tbl_sram_set, 963 .tf_dev_get_tbl = tf_tbl_get, 964 .tf_dev_get_sram_tbl = tf_tbl_sram_get, 965 .tf_dev_get_bulk_tbl = tf_tbl_bulk_get, 966 .tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get, 967 .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment, 968 .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info, 969 .tf_dev_alloc_tcam = tf_tcam_shared_alloc, 970 .tf_dev_free_tcam = tf_tcam_shared_free, 971 .tf_dev_set_tcam = tf_tcam_shared_set, 972 .tf_dev_get_tcam = tf_tcam_shared_get, 973 .tf_dev_move_tcam = tf_tcam_shared_move_p58, 974 .tf_dev_clear_tcam = tf_tcam_shared_clear, 975 .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info, 976 .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry, 977 .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry, 978 .tf_dev_move_int_em_entry = tf_em_move_int_entry, 979 .tf_dev_insert_ext_em_entry = NULL, 980 .tf_dev_delete_ext_em_entry = NULL, 981 .tf_dev_get_em_resc_info = tf_em_get_resc_info, 982 .tf_dev_alloc_tbl_scope = NULL, 983 .tf_dev_map_tbl_scope = NULL, 984 .tf_dev_map_parif = NULL, 985 .tf_dev_free_tbl_scope = NULL, 986 .tf_dev_set_if_tbl = tf_if_tbl_set, 987 .tf_dev_get_if_tbl = tf_if_tbl_get, 988 .tf_dev_set_global_cfg = tf_global_cfg_set, 989 .tf_dev_get_global_cfg = tf_global_cfg_get, 990 .tf_dev_get_mailbox = tf_dev_p58_get_mailbox, 991 .tf_dev_word_align = tf_dev_p58_word_align, 992 .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash, 993 .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps, 994 .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources, 995 .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy, 996 .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy, 997 #ifdef TF_FLOW_SCALE_QUERY 998 .tf_dev_update_resc_usage = tf_dev_p58_update_resc_usage, 999 .tf_dev_query_resc_usage = tf_dev_p58_query_resc_usage, 1000 .tf_dev_update_tbl_usage_buffer = tf_dev_p58_update_tbl_usage_buffer, 1001 #endif /* TF_FLOW_SCALE_QUERY */ 1002 }; 1003