1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019-2023 Broadcom 3 * All rights reserved. 4 */ 5 6 #ifndef _TF_DEVICE_P4_H_ 7 #define _TF_DEVICE_P4_H_ 8 9 #include "cfa_resource_types.h" 10 #include "tf_core.h" 11 #include "tf_rm.h" 12 #include "tf_if_tbl.h" 13 #include "tf_global_cfg.h" 14 #include "hcapi_cfa_defs.h" 15 16 extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX]; 17 18 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { 19 [TF_IDENT_TYPE_L2_CTXT_HIGH] = { 20 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, 21 0, 0 22 }, 23 [TF_IDENT_TYPE_L2_CTXT_LOW] = { 24 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW, 25 0, 0 26 }, 27 [TF_IDENT_TYPE_PROF_FUNC] = { 28 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC, 29 0, 0 30 }, 31 [TF_IDENT_TYPE_WC_PROF] = { 32 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID, 33 0, 0 34 }, 35 [TF_IDENT_TYPE_EM_PROF] = { 36 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID, 37 0, 0 38 }, 39 }; 40 41 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { 42 [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = { 43 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH, 44 0, 0 45 }, 46 [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = { 47 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW, 48 0, 0 49 }, 50 [TF_TCAM_TBL_TYPE_PROF_TCAM] = { 51 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM, 52 0, 0 53 }, 54 [TF_TCAM_TBL_TYPE_WC_TCAM] = { 55 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM, 56 0, 0 57 }, 58 [TF_TCAM_TBL_TYPE_SP_TCAM] = { 59 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM, 60 0, 0 61 }, 62 }; 63 64 struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { 65 [TF_EM_TBL_TYPE_TBL_SCOPE] = { 66 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE, 67 0, 0 68 }, 69 }; 70 71 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = { 72 [TF_EM_TBL_TYPE_EM_RECORD] = { 73 TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC, 74 0, 0 75 }, 76 }; 77 78 /* Note that hcapi_types from this table are from hcapi_cfa_p4.h 79 * These are not CFA resource types because they are not allocated 80 * CFA resources - they are identifiers for the interface tables 81 * shared between the firmware and the host. It may make sense to 82 * move these types to cfa_resource_types.h. 83 */ 84 struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = { 85 [TF_IF_TBL_TYPE_PROF_SPIF_DFLT_L2_CTXT] = { 86 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT 87 }, 88 [TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = { 89 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR 90 }, 91 [TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = { 92 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR 93 }, 94 [TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR] = { 95 TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR 96 }, 97 }; 98 99 struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { 100 [TF_TUNNEL_ENCAP] = { 101 TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP 102 }, 103 [TF_ACTION_BLOCK] = { 104 TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK 105 }, 106 }; 107 108 const struct tf_hcapi_resource_map tf_hcapi_res_map_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { 109 [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = { 110 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_HIGH 111 }, 112 [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = { 113 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_L2_CTXT_LOW 114 }, 115 [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = { 116 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_PROF_FUNC 117 }, 118 [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = { 119 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_WC_PROF 120 }, 121 [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = { 122 TF_MODULE_TYPE_IDENTIFIER, 1 << TF_IDENT_TYPE_EM_PROF 123 }, 124 [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = { 125 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH 126 }, 127 [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = { 128 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW 129 }, 130 [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = { 131 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_PROF_TCAM 132 }, 133 [CFA_RESOURCE_TYPE_P4_WC_TCAM] = { 134 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_WC_TCAM 135 }, 136 [CFA_RESOURCE_TYPE_P4_SP_TCAM] = { 137 TF_MODULE_TYPE_TCAM, 1 << TF_TCAM_TBL_TYPE_SP_TCAM 138 }, 139 [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = { 140 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_MODIFY_IPV4 141 }, 142 [CFA_RESOURCE_TYPE_P4_METER_PROF] = { 143 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_PROF 144 }, 145 [CFA_RESOURCE_TYPE_P4_METER] = { 146 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_METER_INST 147 }, 148 [CFA_RESOURCE_TYPE_P4_MIRROR] = { 149 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MIRROR_CONFIG 150 }, 151 [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = { 152 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_FULL_ACT_RECORD 153 }, 154 [CFA_RESOURCE_TYPE_P4_MCG] = { 155 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_MCAST_GROUPS 156 }, 157 [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = { 158 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_8B 159 }, 160 [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = { 161 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_16B 162 }, 163 [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = { 164 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_ENCAP_64B 165 }, 166 [CFA_RESOURCE_TYPE_P4_SP_MAC] = { 167 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC 168 }, 169 [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = { 170 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV4 171 }, 172 [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = { 173 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_SP_SMAC_IPV6 174 }, 175 [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = { 176 TF_MODULE_TYPE_TABLE, 1 << TF_TBL_TYPE_ACT_STATS_64 177 }, 178 [CFA_RESOURCE_TYPE_P4_EM_REC] = { 179 TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_EM_RECORD 180 }, 181 [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = { 182 TF_MODULE_TYPE_EM, 1 << TF_EM_TBL_TYPE_TBL_SCOPE 183 }, 184 }; 185 #endif /* _TF_DEVICE_P4_H_ */ 186