1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2024 Intel Corporation 3 */ 4 /* 5 * Copyright (C) 2019 Intel Corporation 6 * 7 * For licensing information, see the file 'LICENSE' in the root folder 8 */ 9 #ifndef _VIRTCHNL2_LAN_DESC_H_ 10 #define _VIRTCHNL2_LAN_DESC_H_ 11 12 /* VIRTCHNL2_TX_DESC_IDS 13 * Transmit descriptor ID flags 14 */ 15 enum virtchnl2_tx_desc_ids { 16 VIRTCHNL2_TXDID_DATA = BIT(0), 17 VIRTCHNL2_TXDID_CTX = BIT(1), 18 VIRTCHNL2_TXDID_REINJECT_CTX = BIT(2), 19 VIRTCHNL2_TXDID_FLEX_DATA = BIT(3), 20 VIRTCHNL2_TXDID_FLEX_CTX = BIT(4), 21 VIRTCHNL2_TXDID_FLEX_TSO_CTX = BIT(5), 22 VIRTCHNL2_TXDID_FLEX_TSYN_L2TAG1 = BIT(6), 23 VIRTCHNL2_TXDID_FLEX_L2TAG1_L2TAG2 = BIT(7), 24 VIRTCHNL2_TXDID_FLEX_TSO_L2TAG2_PARSTAG_CTX = BIT(8), 25 VIRTCHNL2_TXDID_FLEX_HOSTSPLIT_SA_TSO_CTX = BIT(9), 26 VIRTCHNL2_TXDID_FLEX_HOSTSPLIT_SA_CTX = BIT(10), 27 VIRTCHNL2_TXDID_FLEX_L2TAG2_CTX = BIT(11), 28 VIRTCHNL2_TXDID_FLEX_FLOW_SCHED = BIT(12), 29 VIRTCHNL2_TXDID_FLEX_HOSTSPLIT_TSO_CTX = BIT(13), 30 VIRTCHNL2_TXDID_FLEX_HOSTSPLIT_CTX = BIT(14), 31 VIRTCHNL2_TXDID_DESC_DONE = BIT(15), 32 }; 33 34 /** 35 * VIRTCHNL2_RX_DESC_IDS 36 * Receive descriptor IDs (range from 0 to 63) 37 */ 38 enum virtchnl2_rx_desc_ids { 39 VIRTCHNL2_RXDID_0_16B_BASE, 40 VIRTCHNL2_RXDID_1_32B_BASE, 41 /* FLEX_SQ_NIC and FLEX_SPLITQ share desc ids because they can be 42 * differentiated based on queue model; e.g. single queue model can 43 * only use FLEX_SQ_NIC and split queue model can only use FLEX_SPLITQ 44 * for DID 2. 45 */ 46 VIRTCHNL2_RXDID_2_FLEX_SPLITQ = 2, 47 VIRTCHNL2_RXDID_2_FLEX_SQ_NIC = VIRTCHNL2_RXDID_2_FLEX_SPLITQ, 48 VIRTCHNL2_RXDID_3_FLEX_SQ_SW = 3, 49 VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB = 4, 50 VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL = 5, 51 VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2 = 6, 52 VIRTCHNL2_RXDID_7_HW_RSVD = 7, 53 /* 9 through 15 are reserved */ 54 VIRTCHNL2_RXDID_16_COMMS_GENERIC = 16, 55 VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN = 17, 56 VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4 = 18, 57 VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6 = 19, 58 VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW = 20, 59 VIRTCHNL2_RXDID_21_COMMS_AUX_TCP = 21, 60 /* 22 through 63 are reserved */ 61 }; 62 63 /** 64 * VIRTCHNL2_RX_DESC_ID_BITMASKS 65 * Receive descriptor ID bitmasks 66 */ 67 #define VIRTCHNL2_RXDID_M(bit) BIT_ULL(VIRTCHNL2_RXDID_##bit) 68 69 enum virtchnl2_rx_desc_id_bitmasks { 70 VIRTCHNL2_RXDID_0_16B_BASE_M = VIRTCHNL2_RXDID_M(0_16B_BASE), 71 VIRTCHNL2_RXDID_1_32B_BASE_M = VIRTCHNL2_RXDID_M(1_32B_BASE), 72 VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M = VIRTCHNL2_RXDID_M(2_FLEX_SPLITQ), 73 VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M = VIRTCHNL2_RXDID_M(2_FLEX_SQ_NIC), 74 VIRTCHNL2_RXDID_3_FLEX_SQ_SW_M = VIRTCHNL2_RXDID_M(3_FLEX_SQ_SW), 75 VIRTCHNL2_RXDID_4_FLEX_SQ_NIC_VEB_M = VIRTCHNL2_RXDID_M(4_FLEX_SQ_NIC_VEB), 76 VIRTCHNL2_RXDID_5_FLEX_SQ_NIC_ACL_M = VIRTCHNL2_RXDID_M(5_FLEX_SQ_NIC_ACL), 77 VIRTCHNL2_RXDID_6_FLEX_SQ_NIC_2_M = VIRTCHNL2_RXDID_M(6_FLEX_SQ_NIC_2), 78 VIRTCHNL2_RXDID_7_HW_RSVD_M = VIRTCHNL2_RXDID_M(7_HW_RSVD), 79 /* 9 through 15 are reserved */ 80 VIRTCHNL2_RXDID_16_COMMS_GENERIC_M = VIRTCHNL2_RXDID_M(16_COMMS_GENERIC), 81 VIRTCHNL2_RXDID_17_COMMS_AUX_VLAN_M = VIRTCHNL2_RXDID_M(17_COMMS_AUX_VLAN), 82 VIRTCHNL2_RXDID_18_COMMS_AUX_IPV4_M = VIRTCHNL2_RXDID_M(18_COMMS_AUX_IPV4), 83 VIRTCHNL2_RXDID_19_COMMS_AUX_IPV6_M = VIRTCHNL2_RXDID_M(19_COMMS_AUX_IPV6), 84 VIRTCHNL2_RXDID_20_COMMS_AUX_FLOW_M = VIRTCHNL2_RXDID_M(20_COMMS_AUX_FLOW), 85 VIRTCHNL2_RXDID_21_COMMS_AUX_TCP_M = VIRTCHNL2_RXDID_M(21_COMMS_AUX_TCP), 86 /* 22 through 63 are reserved */ 87 }; 88 89 /* For splitq virtchnl2_rx_flex_desc_adv desc members */ 90 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S 0 91 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M GENMASK(3, 0) 92 #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S 6 93 #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M GENMASK(7, 6) 94 #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S 0 95 #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M GENMASK(9, 0) 96 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S 12 97 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M GENMASK(15, 13) 98 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S 0 99 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M GENMASK(13, 0) 100 #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S 14 101 #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M \ 102 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S) 103 #define VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S 15 104 #define VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M \ 105 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S) 106 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S 0 107 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M GENMASK(9, 0) 108 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S 10 109 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M \ 110 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S) 111 #define VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S 11 112 #define VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_M \ 113 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S) 114 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_S 12 115 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M GENMASK(14, 12) 116 #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S 15 117 #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_M \ 118 BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S) 119 120 /** 121 * VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS_ERROR_0_QW1_BITS 122 * For splitq virtchnl2_rx_flex_desc_adv 123 * Note: These are predefined bit offsets 124 */ 125 enum virtchl2_rx_flex_desc_adv_status_error_0_qw1_bits { 126 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_DD_S, 127 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_EOF_S, 128 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_HBO_S, 129 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_L3L4P_S, 130 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_IPE_S, 131 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_L4E_S, 132 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EIPE_S, 133 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XSUM_EUDPE_S, 134 }; 135 136 /** 137 * VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS_ERROR_0_QW0_BITS 138 * For splitq virtchnl2_rx_flex_desc_adv 139 * Note: These are predefined bit offsets 140 */ 141 enum virtchnl2_rx_flex_desc_adv_status_error_0_qw0_bits { 142 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_LPBK_S, 143 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_IPV6EXADD_S, 144 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_RXE_S, 145 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_CRCP_S, 146 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_RSS_VALID_S, 147 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_L2TAG1P_S, 148 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XTRMD0_VALID_S, 149 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_XTRMD1_VALID_S, 150 /* this entry must be last!!! */ 151 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS0_LAST, 152 }; 153 154 /** 155 * VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS_ERROR_1_BITS 156 * For splitq virtchnl2_rx_flex_desc_adv 157 * Note: These are predefined bit offsets 158 */ 159 enum virtchnl2_rx_flex_desc_adv_status_error_1_bits { 160 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_RSVD_S = 0, 161 /* 2 bits */ 162 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_ATRAEFAIL_S = 2, 163 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_L2TAG2P_S = 3, 164 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_XTRMD2_VALID_S = 4, 165 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_XTRMD3_VALID_S = 5, 166 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_XTRMD4_VALID_S = 6, 167 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_XTRMD5_VALID_S = 7, 168 /* this entry must be last!!! */ 169 VIRTCHNL2_RX_FLEX_DESC_ADV_STATUS1_LAST = 8, 170 }; 171 172 /* for singleq (flex) virtchnl2_rx_flex_desc fields 173 * for virtchnl2_rx_flex_desc.ptype_flex_flags0 member 174 */ 175 #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_S 0 176 #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M GENMASK(9, 0) 177 178 /* For virtchnl2_rx_flex_desc.pkt_len member */ 179 #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S 0 180 #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M GENMASK(13, 0) 181 182 /** 183 * VIRTCHNL2_RX_FLEX_DESC_STATUS_ERROR_0_BITS 184 * For singleq (flex) virtchnl2_rx_flex_desc 185 * Note: These are predefined bit offsets 186 */ 187 enum virtchnl2_rx_flex_desc_status_error_0_bits { 188 VIRTCHNL2_RX_FLEX_DESC_STATUS0_DD_S, 189 VIRTCHNL2_RX_FLEX_DESC_STATUS0_EOF_S, 190 VIRTCHNL2_RX_FLEX_DESC_STATUS0_HBO_S, 191 VIRTCHNL2_RX_FLEX_DESC_STATUS0_L3L4P_S, 192 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XSUM_IPE_S, 193 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XSUM_L4E_S, 194 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S, 195 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S, 196 VIRTCHNL2_RX_FLEX_DESC_STATUS0_LPBK_S, 197 VIRTCHNL2_RX_FLEX_DESC_STATUS0_IPV6EXADD_S, 198 VIRTCHNL2_RX_FLEX_DESC_STATUS0_RXE_S, 199 VIRTCHNL2_RX_FLEX_DESC_STATUS0_CRCP_S, 200 VIRTCHNL2_RX_FLEX_DESC_STATUS0_RSS_VALID_S, 201 VIRTCHNL2_RX_FLEX_DESC_STATUS0_L2TAG1P_S, 202 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S, 203 VIRTCHNL2_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S, 204 /* this entry must be last!!! */ 205 VIRTCHNL2_RX_FLEX_DESC_STATUS0_LAST, 206 }; 207 208 /** 209 * VIRTCHNL2_RX_FLEX_DESC_STATUS_ERROR_1_BITS 210 * For singleq (flex) virtchnl2_rx_flex_desc 211 * Note: These are predefined bit offsets 212 */ 213 enum virtchnl2_rx_flex_desc_status_error_1_bits { 214 VIRTCHNL2_RX_FLEX_DESC_STATUS1_CPM_S = 0, 215 /* 4 bits */ 216 VIRTCHNL2_RX_FLEX_DESC_STATUS1_NAT_S = 4, 217 VIRTCHNL2_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5, 218 /* [10:6] reserved */ 219 VIRTCHNL2_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11, 220 VIRTCHNL2_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12, 221 VIRTCHNL2_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13, 222 VIRTCHNL2_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14, 223 VIRTCHNL2_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15, 224 /* this entry must be last!!! */ 225 VIRTCHNL2_RX_FLEX_DESC_STATUS1_LAST = 16, 226 }; 227 228 /* For virtchnl2_rx_flex_desc.ts_low member */ 229 #define VIRTCHNL2_RX_FLEX_TSTAMP_VALID BIT(0) 230 231 /* For singleq (non flex) virtchnl2_singleq_base_rx_desc legacy desc members */ 232 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S 63 233 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_M \ 234 BIT_ULL(VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S) 235 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S 52 236 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_M GENMASK_ULL(62, 52) 237 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S 38 238 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M GENMASK_ULL(51, 38) 239 #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S 30 240 #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M GENMASK_ULL(37, 30) 241 #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S 19 242 #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M GENMASK_ULL(26, 19) 243 #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S 0 244 #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M GENMASK_ULL(18, 0) 245 246 /** 247 * VIRTCHNL2_RX_BASE_DESC_STATUS_BITS 248 * For singleq (base) virtchnl2_rx_base_desc 249 * Note: These are predefined bit offsets 250 */ 251 enum virtchnl2_rx_base_desc_status_bits { 252 VIRTCHNL2_RX_BASE_DESC_STATUS_DD_S = 0, 253 VIRTCHNL2_RX_BASE_DESC_STATUS_EOF_S = 1, 254 VIRTCHNL2_RX_BASE_DESC_STATUS_L2TAG1P_S = 2, 255 VIRTCHNL2_RX_BASE_DESC_STATUS_L3L4P_S = 3, 256 VIRTCHNL2_RX_BASE_DESC_STATUS_CRCP_S = 4, 257 VIRTCHNL2_RX_BASE_DESC_STATUS_RSVD_S = 5, /* 3 bits */ 258 VIRTCHNL2_RX_BASE_DESC_STATUS_EXT_UDP_0_S = 8, 259 VIRTCHNL2_RX_BASE_DESC_STATUS_UMBCAST_S = 9, /* 2 bits */ 260 VIRTCHNL2_RX_BASE_DESC_STATUS_FLM_S = 11, 261 VIRTCHNL2_RX_BASE_DESC_STATUS_FLTSTAT_S = 12, /* 2 bits */ 262 VIRTCHNL2_RX_BASE_DESC_STATUS_LPBK_S = 14, 263 VIRTCHNL2_RX_BASE_DESC_STATUS_IPV6EXADD_S = 15, 264 VIRTCHNL2_RX_BASE_DESC_STATUS_RSVD1_S = 16, /* 2 bits */ 265 VIRTCHNL2_RX_BASE_DESC_STATUS_INT_UDP_0_S = 18, 266 VIRTCHNL2_RX_BASE_DESC_STATUS_LAST = 19, /* this entry must be last!!! */ 267 }; 268 269 /** 270 * VIRTCHNL2_RX_BASE_DESC_EXT_STATUS_BITS 271 * For singleq (base) virtchnl2_rx_base_desc 272 * Note: These are predefined bit offsets 273 */ 274 enum virtcnl2_rx_base_desc_status_bits { 275 VIRTCHNL2_RX_BASE_DESC_EXT_STATUS_L2TAG2P_S, 276 }; 277 278 /** 279 * VIRTCHNL2_RX_BASE_DESC_ERROR_BITS 280 * For singleq (base) virtchnl2_rx_base_desc 281 * Note: These are predefined bit offsets 282 */ 283 enum virtchnl2_rx_base_desc_error_bits { 284 VIRTCHNL2_RX_BASE_DESC_ERROR_RXE_S = 0, 285 VIRTCHNL2_RX_BASE_DESC_ERROR_ATRAEFAIL_S = 1, 286 VIRTCHNL2_RX_BASE_DESC_ERROR_HBO_S = 2, 287 VIRTCHNL2_RX_BASE_DESC_ERROR_L3L4E_S = 3, /* 3 bits */ 288 VIRTCHNL2_RX_BASE_DESC_ERROR_IPE_S = 3, 289 VIRTCHNL2_RX_BASE_DESC_ERROR_L4E_S = 4, 290 VIRTCHNL2_RX_BASE_DESC_ERROR_EIPE_S = 5, 291 VIRTCHNL2_RX_BASE_DESC_ERROR_OVERSIZE_S = 6, 292 VIRTCHNL2_RX_BASE_DESC_ERROR_PPRS_S = 7, 293 }; 294 295 /** 296 * VIRTCHNL2_RX_BASE_DESC_FLTSTAT_VALUES 297 * For singleq (base) virtchnl2_rx_base_desc 298 * Note: These are predefined bit offsets 299 */ 300 enum virtchnl2_rx_base_desc_flstat_values { 301 VIRTCHNL2_RX_BASE_DESC_FLTSTAT_NO_DATA, 302 VIRTCHNL2_RX_BASE_DESC_FLTSTAT_FD_ID, 303 VIRTCHNL2_RX_BASE_DESC_FLTSTAT_RSV, 304 VIRTCHNL2_RX_BASE_DESC_FLTSTAT_RSS_HASH, 305 }; 306 307 /** 308 * struct virtchnl2_splitq_rx_buf_desc - SplitQ RX buffer descriptor format 309 * @qword0: RX buffer struct 310 * @qword0.buf_id: Buffer identifier 311 * @qword0.rsvd0: Reserved 312 * @qword0.rsvd1: Reserved 313 * @pkt_addr: Packet buffer address 314 * @hdr_addr: Header buffer address 315 * @rsvd2: Reserved 316 * 317 * Receive Descriptors 318 * SplitQ buffer 319 * | 16| 0| 320 * ---------------------------------------------------------------- 321 * | RSV | Buffer ID | 322 * ---------------------------------------------------------------- 323 * | Rx packet buffer address | 324 * ---------------------------------------------------------------- 325 * | Rx header buffer address | 326 * ---------------------------------------------------------------- 327 * | RSV | 328 * ---------------------------------------------------------------- 329 * | 0| 330 */ 331 struct virtchnl2_splitq_rx_buf_desc { 332 struct { 333 __le16 buf_id; 334 __le16 rsvd0; 335 __le32 rsvd1; 336 } qword0; 337 __le64 pkt_addr; 338 __le64 hdr_addr; 339 __le64 rsvd2; 340 }; 341 342 /** 343 * struct virtchnl2_singleq_rx_buf_desc - SingleQ RX buffer descriptor format 344 * @pkt_addr: Packet buffer address 345 * @hdr_addr: Header buffer address 346 * @rsvd1: Reserved 347 * @rsvd2: Reserved 348 * 349 * SingleQ buffer 350 * | 0| 351 * ---------------------------------------------------------------- 352 * | Rx packet buffer address | 353 * ---------------------------------------------------------------- 354 * | Rx header buffer address | 355 * ---------------------------------------------------------------- 356 * | RSV | 357 * ---------------------------------------------------------------- 358 * | RSV | 359 * ---------------------------------------------------------------- 360 * | 0| 361 */ 362 struct virtchnl2_singleq_rx_buf_desc { 363 __le64 pkt_addr; 364 __le64 hdr_addr; 365 __le64 rsvd1; 366 __le64 rsvd2; 367 }; 368 369 /** 370 * union virtchnl2_rx_buf_desc - RX buffer descriptor 371 * @read: Singleq RX buffer descriptor format 372 * @split_rd: Splitq RX buffer descriptor format 373 */ 374 union virtchnl2_rx_buf_desc { 375 struct virtchnl2_singleq_rx_buf_desc read; 376 struct virtchnl2_splitq_rx_buf_desc split_rd; 377 }; 378 379 /** 380 * struct virtchnl2_singleq_base_rx_desc - RX descriptor writeback format 381 * @qword0: First quad word struct 382 * @qword0.lo_dword: Lower dual word struct 383 * @qword0.lo_dword.mirroring_status: Mirrored packet status 384 * @qword0.lo_dword.l2tag1: Stripped L2 tag from the received packet 385 * @qword0.hi_dword: High dual word union 386 * @qword0.hi_dword.rss: RSS hash 387 * @qword0.hi_dword.fd_id: Flow director filter id 388 * @qword1: Second quad word struct 389 * @qword1.status_error_ptype_len: Status/error/PTYPE/length 390 * @qword2: Third quad word struct 391 * @qword2.ext_status: Extended status 392 * @qword2.rsvd: Reserved 393 * @qword2.l2tag2_1: Extracted L2 tag 2 from the packet 394 * @qword2.l2tag2_2: Reserved 395 * @qword3: Fourth quad word struct 396 * @qword3.reserved: Reserved 397 * @qword3.fd_id: Flow director filter id 398 * 399 * Profile ID 0x1, SingleQ, base writeback format. 400 */ 401 struct virtchnl2_singleq_base_rx_desc { 402 struct { 403 struct { 404 __le16 mirroring_status; 405 __le16 l2tag1; 406 } lo_dword; 407 union { 408 __le32 rss; 409 __le32 fd_id; 410 } hi_dword; 411 } qword0; 412 struct { 413 __le64 status_error_ptype_len; 414 } qword1; 415 struct { 416 __le16 ext_status; 417 __le16 rsvd; 418 __le16 l2tag2_1; 419 __le16 l2tag2_2; 420 } qword2; 421 struct { 422 __le32 reserved; 423 __le32 fd_id; 424 } qword3; 425 }; 426 427 /** 428 * struct virtchnl2_rx_flex_desc - RX descriptor writeback format 429 * @rxdid: Descriptor builder profile id 430 * @mir_id_umb_cast: umb_cast=[7:6], mirror=[5:0] 431 * @ptype_flex_flags0: ff0=[15:10], ptype=[9:0] 432 * @pkt_len: Packet length, [15:14] are reserved 433 * @hdr_len_sph_flex_flags1: ff1/ext=[15:12], sph=[11], header=[10:0] 434 * @status_error0: Status/Error section 0 435 * @l2tag1: Stripped L2 tag from the received packet 436 * @flex_meta0: Flexible metadata container 0 437 * @flex_meta1: Flexible metadata container 1 438 * @status_error1: Status/Error section 1 439 * @flex_flags2: Flexible flags section 2 440 * @time_stamp_low: Lower word of timestamp value 441 * @l2tag2_1st: First L2TAG2 442 * @l2tag2_2nd: Second L2TAG2 443 * @flex_meta2: Flexible metadata container 2 444 * @flex_meta3: Flexible metadata container 3 445 * @flex_ts: Timestamp and flexible flow id union 446 * @flex_ts.flex.flex_meta4: Flexible metadata container 4 447 * @flex_ts.flex.flex_meta5: Flexible metadata container 5 448 * @flex_ts.ts_high: Timestamp higher word of the timestamp value 449 * 450 * Profile ID 0x1, SingleQ, flex completion writeback format. 451 */ 452 struct virtchnl2_rx_flex_desc { 453 /* Qword 0 */ 454 u8 rxdid; 455 u8 mir_id_umb_cast; 456 __le16 ptype_flex_flags0; 457 __le16 pkt_len; 458 __le16 hdr_len_sph_flex_flags1; 459 /* Qword 1 */ 460 __le16 status_error0; 461 __le16 l2tag1; 462 __le16 flex_meta0; 463 __le16 flex_meta1; 464 465 /* Qword 2 */ 466 __le16 status_error1; 467 u8 flex_flags2; 468 u8 time_stamp_low; 469 __le16 l2tag2_1st; 470 __le16 l2tag2_2nd; 471 472 /* Qword 3 */ 473 __le16 flex_meta2; 474 __le16 flex_meta3; 475 union { 476 struct { 477 __le16 flex_meta4; 478 __le16 flex_meta5; 479 } flex; 480 __le32 ts_high; 481 } flex_ts; 482 }; 483 484 /** 485 * struct virtchnl2_rx_flex_desc_nic - RX descriptor writeback format 486 * @rxdid: Descriptor builder profile id 487 * @mir_id_umb_cast: umb_cast=[7:6], mirror=[5:0] 488 * @ptype_flex_flags0: ff0=[15:10], ptype=[9:0] 489 * @pkt_len: Packet length, [15:14] are reserved 490 * @hdr_len_sph_flex_flags1: ff1/ext=[15:12], sph=[11], header=[10:0] 491 * @status_error0: Status/Error section 0 492 * @l2tag1: Stripped L2 tag from the received packet 493 * @rss_hash: RSS hash 494 * @status_error1: Status/Error section 1 495 * @flexi_flags2: Flexible flags section 2 496 * @ts_low: Lower word of timestamp value 497 * @l2tag2_1st: First L2TAG2 498 * @l2tag2_2nd: Second L2TAG2 499 * @flow_id: Flow id 500 * @flex_ts: Timestamp and flexible flow id union 501 * @flex_ts.flex.rsvd: Reserved 502 * @flex_ts.flex.flow_id_ipv6: IPv6 flow id 503 * @flex_ts.ts_high: Timestamp higher word of the timestamp value 504 * 505 * Profile ID 0x2, SingleQ, flex writeback format. 506 */ 507 struct virtchnl2_rx_flex_desc_nic { 508 /* Qword 0 */ 509 u8 rxdid; 510 u8 mir_id_umb_cast; 511 __le16 ptype_flex_flags0; 512 __le16 pkt_len; 513 __le16 hdr_len_sph_flex_flags1; 514 515 /* Qword 1 */ 516 __le16 status_error0; 517 __le16 l2tag1; 518 __le32 rss_hash; 519 520 /* Qword 2 */ 521 __le16 status_error1; 522 u8 flexi_flags2; 523 u8 ts_low; 524 __le16 l2tag2_1st; 525 __le16 l2tag2_2nd; 526 527 /* Qword 3 */ 528 __le32 flow_id; 529 union { 530 struct { 531 __le16 rsvd; 532 __le16 flow_id_ipv6; 533 } flex; 534 __le32 ts_high; 535 } flex_ts; 536 }; 537 538 /** 539 * struct virtchnl2_rx_flex_desc_sw - RX descriptor writeback format 540 * @rxdid: Descriptor builder profile id 541 * @mir_id_umb_cast: umb_cast=[7:6], mirror=[5:0] 542 * @ptype_flex_flags0: ff0=[15:10], ptype=[9:0] 543 * @pkt_len: Packet length, [15:14] are reserved 544 * @hdr_len_sph_flex_flags1: ff1/ext=[15:12], sph=[11], header=[10:0] 545 * @status_error0: Status/Error section 0 546 * @l2tag1: Stripped L2 tag from the received packet 547 * @src_vsi: Source VSI, [10:15] are reserved 548 * @flex_md1_rsvd: Flexible metadata container 1 549 * @status_error1: Status/Error section 1 550 * @flex_flags2: Flexible flags section 2 551 * @ts_low: Lower word of timestamp value 552 * @l2tag2_1st: First L2TAG2 553 * @l2tag2_2nd: Second L2TAG2 554 * @rsvd: Reserved 555 * @ts_high: Timestamp higher word of the timestamp value 556 * 557 * Rx Flex Descriptor Switch Profile 558 * RxDID Profile ID 0x3, SingleQ 559 * Flex-field 0: Source Vsi 560 */ 561 struct virtchnl2_rx_flex_desc_sw { 562 /* Qword 0 */ 563 u8 rxdid; 564 u8 mir_id_umb_cast; 565 __le16 ptype_flex_flags0; 566 __le16 pkt_len; 567 __le16 hdr_len_sph_flex_flags1; 568 569 /* Qword 1 */ 570 __le16 status_error0; 571 __le16 l2tag1; 572 __le16 src_vsi; 573 __le16 flex_md1_rsvd; 574 /* Qword 2 */ 575 __le16 status_error1; 576 u8 flex_flags2; 577 u8 ts_low; 578 __le16 l2tag2_1st; 579 __le16 l2tag2_2nd; 580 /* Qword 3 */ 581 __le32 rsvd; 582 __le32 ts_high; 583 }; 584 585 #ifndef EXTERNAL_RELEASE 586 /** 587 * struct virtchnl2_rx_flex_desc_nic_veb_dbg - RX descriptor writeback format 588 * @rxdid: Descriptor builder profile id 589 * @mir_id_umb_cast: umb_cast=[7:6], mirror=[5:0] 590 * @ptype_flex_flags0: ff0=[15:10], ptype=[9:0] 591 * @pkt_len: Packet length, [15:14] are reserved 592 * @hdr_len_sph_flex_flags1: ff1/ext=[15:12], sph=[11], header=[10:0] 593 * @status_error0: Status/Error section 0 594 * @l2tag1: Stripped L2 tag from the received packet 595 * @dst_vsi: Destination VSI, [10:15] are reserved 596 * @flex_field_1: Flexible metadata container 1 597 * @status_error1: Status/Error section 1 598 * @flex_flags2: Flexible flags section 2 599 * @ts_low: Lower word of timestamp value 600 * @l2tag2_1st: First L2TAG2 601 * @l2tag2_2nd: Second L2TAG2 602 * @rsvd: Flex words 2-3 are reserved 603 * @ts_high: Timestamp higher word of the timestamp value 604 * 605 * Rx Flex Descriptor NIC VEB Profile 606 * RxDID Profile Id 0x4 607 * Flex-field 0: Destination Vsi 608 */ 609 struct virtchnl2_rx_flex_desc_nic_veb_dbg { 610 /* Qword 0 */ 611 u8 rxdid; 612 u8 mir_id_umb_cast; 613 __le16 ptype_flex_flags0; 614 __le16 pkt_len; 615 __le16 hdr_len_sph_flex_flags1; 616 /* Qword 1 */ 617 __le16 status_error0; 618 __le16 l2tag1; 619 __le16 dst_vsi; 620 __le16 flex_field_1; 621 /* Qword 2 */ 622 __le16 status_error1; 623 u8 flex_flags2; 624 u8 ts_low; 625 __le16 l2tag2_1st; 626 __le16 l2tag2_2nd; 627 628 /* Qword 3 */ 629 __le32 rsvd; 630 __le32 ts_high; 631 }; 632 633 /** 634 * struct virtchnl2_rx_flex_desc_nic_acl_dbg - RX descriptor writeback format 635 * @rxdid: Descriptor builder profile id 636 * @mir_id_umb_cast: umb_cast=[7:6], mirror=[5:0] 637 * @ptype_flex_flags0: ff0=[15:10], ptype=[9:0] 638 * @pkt_len: Packet length, [15:14] are reserved 639 * @hdr_len_sph_flex_flags1: ff1/ext=[15:12], sph=[11], header=[10:0] 640 * @status_error0: Status/Error section 0 641 * @l2tag1: Stripped L2 tag from the received packet 642 * @acl_ctr0: ACL counter 0 643 * @acl_ctr1: ACL counter 1 644 * @status_error1: Status/Error section 1 645 * @flex_flags2: Flexible flags section 2 646 * @ts_low: Lower word of timestamp value 647 * @l2tag2_1st: First L2TAG2 648 * @l2tag2_2nd: Second L2TAG2 649 * @acl_ctr2: ACL counter 2 650 * @rsvd: Flex words 2-3 are reserved 651 * @ts_high: Timestamp higher word of the timestamp value 652 * 653 * Rx Flex Descriptor NIC ACL Profile 654 * RxDID Profile ID 0x5 655 * Flex-field 0: ACL Counter 0 656 * Flex-field 1: ACL Counter 1 657 * Flex-field 2: ACL Counter 2 658 */ 659 struct virtchnl2_rx_flex_desc_nic_acl_dbg { 660 /* Qword 0 */ 661 u8 rxdid; 662 u8 mir_id_umb_cast; 663 __le16 ptype_flex_flags0; 664 __le16 pkt_len; 665 __le16 hdr_len_sph_flex_flags1; 666 /* Qword 1 */ 667 __le16 status_error0; 668 __le16 l2tag1; 669 __le16 acl_ctr0; 670 __le16 acl_ctr1; 671 /* Qword 2 */ 672 __le16 status_error1; 673 u8 flex_flags2; 674 u8 ts_low; 675 __le16 l2tag2_1st; 676 __le16 l2tag2_2nd; 677 /* Qword 3 */ 678 __le16 acl_ctr2; 679 __le16 rsvd; 680 __le32 ts_high; 681 }; 682 #endif /* !EXTERNAL_RELEASE */ 683 684 /** 685 * struct virtchnl2_rx_flex_desc_nic_2 - RX descriptor writeback format 686 * @rxdid: Descriptor builder profile id 687 * @mir_id_umb_cast: umb_cast=[7:6], mirror=[5:0] 688 * @ptype_flex_flags0: ff0=[15:10], ptype=[9:0] 689 * @pkt_len: Packet length, [15:14] are reserved 690 * @hdr_len_sph_flex_flags1: ff1/ext=[15:12], sph=[11], header=[10:0] 691 * @status_error0: Status/Error section 0 692 * @l2tag1: Stripped L2 tag from the received packet 693 * @rss_hash: RSS hash 694 * @status_error1: Status/Error section 1 695 * @flexi_flags2: Flexible flags section 2 696 * @ts_low: Lower word of timestamp value 697 * @l2tag2_1st: First L2TAG2 698 * @l2tag2_2nd: Second L2TAG2 699 * @flow_id: Flow id 700 * @src_vsi: Source VSI 701 * @flex_ts: Timestamp and flexible flow id union 702 * @flex_ts.flex.rsvd: Reserved 703 * @flex_ts.flex.flow_id_ipv6: IPv6 flow id 704 * @flex_ts.ts_high: Timestamp higher word of the timestamp value 705 * 706 * Rx Flex Descriptor NIC Profile 707 * RxDID Profile ID 0x6 708 * Flex-field 0: RSS hash lower 16-bits 709 * Flex-field 1: RSS hash upper 16-bits 710 * Flex-field 2: Flow Id lower 16-bits 711 * Flex-field 3: Source Vsi 712 * Flex-field 4: reserved, Vlan id taken from L2Tag 713 */ 714 struct virtchnl2_rx_flex_desc_nic_2 { 715 /* Qword 0 */ 716 u8 rxdid; 717 u8 mir_id_umb_cast; 718 __le16 ptype_flex_flags0; 719 __le16 pkt_len; 720 __le16 hdr_len_sph_flex_flags1; 721 722 /* Qword 1 */ 723 __le16 status_error0; 724 __le16 l2tag1; 725 __le32 rss_hash; 726 727 /* Qword 2 */ 728 __le16 status_error1; 729 u8 flexi_flags2; 730 u8 ts_low; 731 __le16 l2tag2_1st; 732 __le16 l2tag2_2nd; 733 734 /* Qword 3 */ 735 __le16 flow_id; 736 __le16 src_vsi; 737 union { 738 struct { 739 __le16 rsvd; 740 __le16 flow_id_ipv6; 741 } flex; 742 __le32 ts_high; 743 } flex_ts; 744 }; 745 746 /** 747 * struct virtchnl2_rx_flex_desc_adv - RX descriptor writeback format 748 * @rxdid_ucast: ucast=[7:6], rsvd=[5:4], profile_id=[3:0] 749 * @status_err0_qw0: Status/Error section 0 in quad word 0 750 * @ptype_err_fflags0: ff0=[15:12], udp_len_err=[11], ip_hdr_err=[10], 751 * ptype=[9:0] 752 * @pktlen_gen_bufq_id: bufq_id=[15] only in splitq, gen=[14] only in splitq, 753 * plen=[13:0] 754 * @hdrlen_flags: miss_prepend=[15], trunc_mirr=[14], int_udp_0=[13], 755 * ext_udp0=[12], sph=[11] only in splitq, rsc=[10] 756 * only in splitq, header=[9:0] 757 * @status_err0_qw1: Status/Error section 0 in quad word 1 758 * @status_err1: Status/Error section 1 759 * @fflags1: Flexible flags section 1 760 * @ts_low: Lower word of timestamp value 761 * @fmd0: Flexible metadata container 0 762 * @fmd1: Flexible metadata container 1 763 * @fmd2: Flexible metadata container 2 764 * @fflags2: Flags 765 * @hash3: Upper bits of Rx hash value 766 * @fmd3: Flexible metadata container 3 767 * @fmd4: Flexible metadata container 4 768 * @fmd5: Flexible metadata container 5 769 * @fmd6: Flexible metadata container 6 770 * @fmd7_0: Flexible metadata container 7.0 771 * @fmd7_1: Flexible metadata container 7.1 772 * 773 * RX Flex Descriptor Advanced (Split Queue Model) 774 * RxDID Profile ID 0x2 775 */ 776 struct virtchnl2_rx_flex_desc_adv { 777 /* Qword 0 */ 778 u8 rxdid_ucast; 779 u8 status_err0_qw0; 780 __le16 ptype_err_fflags0; 781 __le16 pktlen_gen_bufq_id; 782 __le16 hdrlen_flags; 783 /* Qword 1 */ 784 u8 status_err0_qw1; 785 u8 status_err1; 786 u8 fflags1; 787 u8 ts_low; 788 __le16 fmd0; 789 __le16 fmd1; 790 /* Qword 2 */ 791 __le16 fmd2; 792 u8 fflags2; 793 u8 hash3; 794 __le16 fmd3; 795 __le16 fmd4; 796 /* Qword 3 */ 797 __le16 fmd5; 798 __le16 fmd6; 799 __le16 fmd7_0; 800 __le16 fmd7_1; 801 }; 802 803 /** 804 * struct virtchnl2_rx_flex_desc_adv_nic_3 - RX descriptor writeback format 805 * @rxdid_ucast: ucast=[7:6], rsvd=[5:4], profile_id=[3:0] 806 * @status_err0_qw0: Status/Error section 0 in quad word 0 807 * @ptype_err_fflags0: ff0=[15:12], udp_len_err=[11], ip_hdr_err=[10], 808 * ptype=[9:0] 809 * @pktlen_gen_bufq_id: bufq_id=[15] only in splitq, gen=[14] only in splitq, 810 * plen=[13:0] 811 * @hdrlen_flags: miss_prepend=[15], trunc_mirr=[14], int_udp_0=[13], 812 * ext_udp0=[12], sph=[11] only in splitq, rsc=[10] 813 * only in splitq, header=[9:0] 814 * @status_err0_qw1: Status/Error section 0 in quad word 1 815 * @status_err1: Status/Error section 1 816 * @fflags1: Flexible flags section 1 817 * @ts_low: Lower word of timestamp value 818 * @buf_id: Buffer identifier. Only in splitq mode. 819 * @misc: Union 820 * @misc.raw_cs: Raw checksum 821 * @misc.l2tag1: Stripped L2 tag from the received packet 822 * @misc.rscseglen: RSC segment length 823 * @hash1: Lower 16 bits of Rx hash value, hash[15:0] 824 * @ff2_mirrid_hash2: Union 825 * @ff2_mirrid_hash2.fflags2: Flexible flags section 2 826 * @ff2_mirrid_hash2.mirrorid: Mirror id 827 * @ff2_mirrid_hash2.hash2: 8 bits of Rx hash value, hash[23:16] 828 * @hash3: Upper 8 bits of Rx hash value, hash[31:24] 829 * @l2tag2: Extracted L2 tag 2 from the packet 830 * @fmd4: Flexible metadata container 4 831 * @l2tag1: Stripped L2 tag from the received packet 832 * @fmd6: Flexible metadata container 6 833 * @ts_high: Timestamp higher word of the timestamp value 834 * 835 * Profile ID 0x2, SplitQ, flex writeback format. 836 * 837 * Flex-field 0: BufferID 838 * Flex-field 1: Raw checksum/L2TAG1/RSC Seg Len (determined by HW) 839 * Flex-field 2: Hash[15:0] 840 * Flex-flags 2: Hash[23:16] 841 * Flex-field 3: L2TAG2 842 * Flex-field 5: L2TAG1 843 * Flex-field 7: Timestamp (upper 32 bits) 844 */ 845 struct virtchnl2_rx_flex_desc_adv_nic_3 { 846 /* Qword 0 */ 847 u8 rxdid_ucast; 848 u8 status_err0_qw0; 849 __le16 ptype_err_fflags0; 850 __le16 pktlen_gen_bufq_id; 851 __le16 hdrlen_flags; 852 /* Qword 1 */ 853 u8 status_err0_qw1; 854 u8 status_err1; 855 u8 fflags1; 856 u8 ts_low; 857 __le16 buf_id; 858 union { 859 __le16 raw_cs; 860 __le16 l2tag1; 861 __le16 rscseglen; 862 } misc; 863 /* Qword 2 */ 864 __le16 hash1; 865 union { 866 u8 fflags2; 867 u8 mirrorid; 868 u8 hash2; 869 } ff2_mirrid_hash2; 870 u8 hash3; 871 __le16 l2tag2; 872 __le16 fmd4; 873 /* Qword 3 */ 874 __le16 l2tag1; 875 __le16 fmd6; 876 __le32 ts_high; 877 }; 878 879 union virtchnl2_rx_desc { 880 struct virtchnl2_singleq_rx_buf_desc read; 881 struct virtchnl2_singleq_base_rx_desc base_wb; 882 struct virtchnl2_rx_flex_desc flex_wb; 883 struct virtchnl2_rx_flex_desc_nic flex_nic_wb; 884 struct virtchnl2_rx_flex_desc_sw flex_sw_wb; 885 struct virtchnl2_rx_flex_desc_nic_2 flex_nic_2_wb; 886 struct virtchnl2_rx_flex_desc_adv flex_adv_wb; 887 struct virtchnl2_rx_flex_desc_adv_nic_3 flex_adv_nic_3_wb; 888 }; 889 890 #endif /* _VIRTCHNL_LAN_DESC_H_ */ 891