1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2023 Intel Corporation 3 */ 4 #ifndef _SIOV_REGS_H_ 5 #define _SIOV_REGS_H_ 6 #define VDEV_MBX_START 0x20000 /* Begin at 128KB */ 7 #define VDEV_GET_RSTAT 0x21000 /* 132KB for RSTAT */ 8 9 /* Begin at offset after 1MB (after 256 4k pages) */ 10 #define VDEV_QRX_TAIL_START 0x100000 11 #define VDEV_QRX_TAIL(_i) (VDEV_QRX_TAIL_START + ((_i) * 0x1000)) /* 2k Rx queues */ 12 13 /* Begin at offset of 9MB for Rx buffer queue tail register pages */ 14 #define VDEV_QRX_BUFQ_TAIL_START 0x900000 15 /* 2k Rx buffer queues */ 16 #define VDEV_QRX_BUFQ_TAIL(_i) (VDEV_QRX_BUFQ_TAIL_START + ((_i) * 0x1000)) 17 18 /* Begin at offset of 17MB for 2k Tx queues */ 19 #define VDEV_QTX_TAIL_START 0x1100000 20 #define VDEV_QTX_TAIL(_i) (VDEV_QTX_TAIL_START + ((_i) * 0x1000)) /* 2k Tx queues */ 21 22 /* Begin at offset of 25MB for 2k Tx completion queues */ 23 #define VDEV_QTX_COMPL_TAIL_START 0x1900000 24 /* 2k Tx completion queues */ 25 #define VDEV_QTX_COMPL_TAIL(_i) (VDEV_QTX_COMPL_TAIL_START + ((_i) * 0x1000)) 26 27 #define VDEV_INT_DYN_CTL01 0x2100000 /* Begin at offset 33MB */ 28 29 /* Begin at offset of 33MB + 4k to accommodate CTL01 register */ 30 #define VDEV_INT_DYN_START (VDEV_INT_DYN_CTL01 + 0x1000) 31 #define VDEV_INT_DYN_CTL(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000)) 32 #define VDEV_INT_ITR_0(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x04) 33 #define VDEV_INT_ITR_1(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x08) 34 #define VDEV_INT_ITR_2(_i) (VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x0C) 35 36 #define SIOV_REG_BAR_SIZE 0x2A00000 37 /* Next offset to begin at 42MB + 4K (0x2A00000 + 0x1000) */ 38 #endif /* _SIOV_REGS_H_ */ 39