1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_CPT_H_ 6 #define _ROC_CPT_H_ 7 8 #include "hw/cpt.h" 9 10 #include "roc_platform.h" 11 12 #define ROC_AE_CPT_BLOCK_TYPE1 0 13 #define ROC_AE_CPT_BLOCK_TYPE2 1 14 15 #define ROC_LOADFVC_MAJOR_OP 0x01UL 16 #define ROC_LOADFVC_MINOR_OP 0x08UL 17 18 /* Default engine groups */ 19 #define ROC_CPT_DFLT_ENG_GRP_SE 0UL 20 #define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL 21 #define ROC_CPT_DFLT_ENG_GRP_AE 2UL 22 23 #define ROC_CPT_MAX_LFS 64 24 #define ROC_CPT_MAX_BLKS 2 25 #define ROC_CN10K_CPT_INST_DW_M1 \ 26 ((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7)) 27 #define ROC_CN10K_TWO_CPT_INST_DW_M1 \ 28 ((uint64_t)(((sizeof(struct cpt_inst_s) * 2 / 16) - 1) & 0x7)) 29 30 /* Vector of sizes in the burst of 16 CPT inst except first in 63:19 of 31 * APT_LMT_ARG_S 32 */ 33 #define ROC_CN10K_CPT_LMT_ARG \ 34 (ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 0) | ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 1) | \ 35 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 2) | ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 3) | \ 36 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 4) | ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 5) | \ 37 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 6) | ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 7) | \ 38 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 8) | ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 9) | \ 39 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 10) | ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 11) | \ 40 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 12) | ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 13) | \ 41 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 14)) 42 43 /* Vector of sizes in the burst of 2 * 16 CPT inst except first in 63:19 of 44 * APT_LMT_ARG_S 45 */ 46 #define ROC_CN10K_DUAL_CPT_LMT_ARG \ 47 (ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 0) | \ 48 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 1) | \ 49 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 2) | \ 50 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 3) | \ 51 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 4) | \ 52 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 5) | \ 53 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 6) | \ 54 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 7) | \ 55 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 8) | \ 56 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 9) | \ 57 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 10) | \ 58 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 11) | \ 59 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 12) | \ 60 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 13) | \ 61 ROC_CN10K_TWO_CPT_INST_DW_M1 << (19 + 3 * 14)) 62 63 /* CPT helper macros */ 64 #define ROC_CPT_AH_HDR_LEN 12 65 #define ROC_CPT_AES_GCM_IV_LEN 8 66 #define ROC_CPT_AES_GCM_MAC_LEN 16 67 #define ROC_CPT_AES_CCM_CTR_LEN 4 68 #define ROC_CPT_AES_CBC_IV_LEN 16 69 #define ROC_CPT_SHA1_HMAC_LEN 12 70 #define ROC_CPT_SHA2_HMAC_LEN 16 71 #define ROC_CPT_DES_IV_LEN 8 72 73 #define ROC_CPT_DES3_KEY_LEN 24 74 #define ROC_CPT_AES128_KEY_LEN 16 75 #define ROC_CPT_AES192_KEY_LEN 24 76 #define ROC_CPT_AES256_KEY_LEN 32 77 #define ROC_CPT_MD5_KEY_LENGTH 16 78 #define ROC_CPT_SHA1_KEY_LENGTH 20 79 #define ROC_CPT_SHA256_KEY_LENGTH 32 80 #define ROC_CPT_SHA384_KEY_LENGTH 48 81 #define ROC_CPT_SHA512_KEY_LENGTH 64 82 #define ROC_CPT_AES_XCBC_KEY_LENGTH 16 83 #define ROC_CPT_AUTH_KEY_LEN_MAX 64 84 85 #define ROC_CPT_DES_BLOCK_LENGTH 8 86 #define ROC_CPT_AES_BLOCK_LENGTH 16 87 88 /* Salt length for AES-CTR/GCM/CCM and AES-GMAC */ 89 #define ROC_CPT_SALT_LEN 4 90 91 #define ROC_CPT_ESP_HDR_LEN 8 92 #define ROC_CPT_ESP_TRL_LEN 2 93 #define ROC_CPT_AH_HDR_LEN 12 94 #define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20 95 #define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40 96 97 #define ROC_CPT_CCM_AAD_DATA 1 98 #define ROC_CPT_CCM_MSG_LEN 4 99 #define ROC_CPT_CCM_ICV_LEN 16 100 #define ROC_CPT_CCM_FLAGS \ 101 ((ROC_CPT_CCM_AAD_DATA << 6) | \ 102 (((ROC_CPT_CCM_ICV_LEN - 2) / 2) << 3) | (ROC_CPT_CCM_MSG_LEN - 1)) 103 #define ROC_CPT_CCM_SALT_LEN 3 104 105 #define ROC_CPT_RES_ALIGN 16 106 107 enum { 108 ROC_CPT_REVISION_ID_83XX = 0, 109 ROC_CPT_REVISION_ID_96XX_B0 = 1, 110 ROC_CPT_REVISION_ID_96XX_C0 = 2, 111 ROC_CPT_REVISION_ID_98XX = 3, 112 ROC_CPT_REVISION_ID_106XX = 4, 113 }; 114 115 struct roc_cpt_lmtline { 116 uint64_t io_addr; 117 uint64_t *fc_addr; 118 uintptr_t lmt_base; 119 uint32_t fc_thresh; 120 }; 121 122 struct roc_cpt_lf { 123 /* Input parameters */ 124 uint16_t lf_id; 125 uint32_t nb_desc; 126 /* End of Input parameters */ 127 struct plt_pci_device *pci_dev; 128 struct dev *dev; 129 struct roc_cpt *roc_cpt; 130 uintptr_t rbase; 131 uintptr_t lmt_base; 132 uint16_t msixoff; 133 uint16_t pf_func; 134 uint64_t *fc_addr; 135 uint64_t io_addr; 136 uint8_t *iq_vaddr; 137 struct roc_nix *inl_outb_nix; 138 uint8_t error_event_pending; 139 } __plt_cache_aligned; 140 141 struct roc_cpt { 142 struct plt_pci_device *pci_dev; 143 struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS]; 144 uint16_t nb_lf; 145 uint16_t nb_lf_avail; 146 uintptr_t lmt_base; 147 /**< CPT device capabilities */ 148 union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES]; 149 uint8_t eng_grp[CPT_MAX_ENG_TYPES]; 150 uint8_t cpt_revision; 151 void *opaque; 152 #define ROC_CPT_MEM_SZ (6 * 1024) 153 uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned; 154 } __plt_cache_aligned; 155 156 struct roc_cpt_rxc_time_cfg { 157 uint32_t step; 158 uint16_t active_limit; 159 uint16_t active_thres; 160 uint16_t zombie_limit; 161 uint16_t zombie_thres; 162 }; 163 164 /* CPT MISC interrupt callback */ 165 typedef void (*roc_cpt_int_misc_cb_t)(struct roc_cpt_lf *lf, void *args); 166 167 struct roc_cpt_inline_ipsec_inb_cfg { 168 uint32_t cpt_credit; 169 uint16_t opcode; 170 uint16_t param1; 171 uint16_t param2; 172 uint16_t bpid; 173 uint32_t credit_th; 174 uint8_t egrp; 175 uint8_t ctx_ilen_valid : 1; 176 uint8_t ctx_ilen : 7; 177 }; 178 179 int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, 180 struct roc_cpt_rxc_time_cfg *cfg); 181 int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt); 182 int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt); 183 int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, 184 enum cpt_eng_type eng_type); 185 int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf, bool rxc_ena, 186 uint16_t rx_inject_qp); 187 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt); 188 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf); 189 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf); 190 void __roc_api roc_cpt_lf_reset(struct roc_cpt_lf *lf); 191 int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, 192 bool inval); 193 int __roc_api roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr); 194 int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot, 195 struct roc_nix *nix); 196 int __roc_api roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt, 197 struct roc_cpt_inline_ipsec_inb_cfg *cfg); 198 int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, 199 struct roc_cpt_inline_ipsec_inb_cfg *cfg); 200 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); 201 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt); 202 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf); 203 void __roc_api roc_cpt_iq_enable(struct roc_cpt_lf *lf); 204 int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline, 205 int lf_id, bool is_dual); 206 207 void __roc_api roc_cpt_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth); 208 int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, 209 uint16_t sa_len); 210 211 void __roc_api roc_cpt_int_misc_cb_register(roc_cpt_int_misc_cb_t cb, void *args); 212 int __roc_api roc_cpt_int_misc_cb_unregister(roc_cpt_int_misc_cb_t cb, void *args); 213 #endif /* _ROC_CPT_H_ */ 214