1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef __RVU_HW_H__ 6 #define __RVU_HW_H__ 7 8 /* Register offsets */ 9 10 #define RVU_AF_MSIXTR_BASE (0x10ull) 11 #define RVU_AF_BLK_RST (0x30ull) 12 #define RVU_AF_PF_BAR4_ADDR (0x40ull) 13 #define RVU_AF_RAS (0x100ull) 14 #define RVU_AF_RAS_W1S (0x108ull) 15 #define RVU_AF_RAS_ENA_W1S (0x110ull) 16 #define RVU_AF_RAS_ENA_W1C (0x118ull) 17 #define RVU_AF_GEN_INT (0x120ull) 18 #define RVU_AF_GEN_INT_W1S (0x128ull) 19 #define RVU_AF_GEN_INT_ENA_W1S (0x130ull) 20 #define RVU_AF_GEN_INT_ENA_W1C (0x138ull) 21 #define RVU_AF_AFPFX_MBOXX(a, b) \ 22 (0x2000ull | (uint64_t)(a) << 4 | (uint64_t)(b) << 3) 23 #define RVU_AF_PFME_STATUS (0x2800ull) 24 #define RVU_AF_PFTRPEND (0x2810ull) 25 #define RVU_AF_PFTRPEND_W1S (0x2820ull) 26 #define RVU_AF_PF_RST (0x2840ull) 27 #define RVU_AF_HWVF_RST (0x2850ull) 28 #define RVU_AF_PFAF_MBOX_INT (0x2880ull) 29 #define RVU_AF_PFAF_MBOX_INT_W1S (0x2888ull) 30 #define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890ull) 31 #define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898ull) 32 #define RVU_AF_PFFLR_INT (0x28a0ull) 33 #define RVU_AF_PFFLR_INT_W1S (0x28a8ull) 34 #define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0ull) 35 #define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8ull) 36 #define RVU_AF_PFME_INT (0x28c0ull) 37 #define RVU_AF_PFME_INT_W1S (0x28c8ull) 38 #define RVU_AF_PFME_INT_ENA_W1S (0x28d0ull) 39 #define RVU_AF_PFME_INT_ENA_W1C (0x28d8ull) 40 #define RVU_PRIV_CONST (0x8000000ull) 41 #define RVU_PRIV_GEN_CFG (0x8000010ull) 42 #define RVU_PRIV_CLK_CFG (0x8000020ull) 43 #define RVU_PRIV_ACTIVE_PC (0x8000030ull) 44 #define RVU_PRIV_PFX_CFG(a) (0x8000100ull | (uint64_t)(a) << 16) 45 #define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110ull | (uint64_t)(a) << 16) 46 #define RVU_PRIV_PFX_ID_CFG(a) (0x8000120ull | (uint64_t)(a) << 16) 47 #define RVU_PRIV_PFX_INT_CFG(a) (0x8000200ull | (uint64_t)(a) << 16) 48 #define RVU_PRIV_PFX_NIXX_CFG(a, b) \ 49 (0x8000300ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) 50 #define RVU_PRIV_PFX_NPA_CFG(a) (0x8000310ull | (uint64_t)(a) << 16) 51 #define RVU_PRIV_PFX_SSO_CFG(a) (0x8000320ull | (uint64_t)(a) << 16) 52 #define RVU_PRIV_PFX_SSOW_CFG(a) (0x8000330ull | (uint64_t)(a) << 16) 53 #define RVU_PRIV_PFX_TIM_CFG(a) (0x8000340ull | (uint64_t)(a) << 16) 54 #define RVU_PRIV_PFX_CPTX_CFG(a, b) \ 55 (0x8000350ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) 56 #define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400ull | (uint64_t)(a) << 3) 57 #define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280ull | (uint64_t)(a) << 16) 58 #define RVU_PRIV_HWVFX_NIXX_CFG(a, b) \ 59 (0x8001300ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) 60 #define RVU_PRIV_HWVFX_NPA_CFG(a) (0x8001310ull | (uint64_t)(a) << 16) 61 #define RVU_PRIV_HWVFX_SSO_CFG(a) (0x8001320ull | (uint64_t)(a) << 16) 62 #define RVU_PRIV_HWVFX_SSOW_CFG(a) (0x8001330ull | (uint64_t)(a) << 16) 63 #define RVU_PRIV_HWVFX_TIM_CFG(a) (0x8001340ull | (uint64_t)(a) << 16) 64 #define RVU_PRIV_HWVFX_CPTX_CFG(a, b) \ 65 (0x8001350ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) 66 67 #define RVU_PF_VFX_PFVF_MBOXX(a, b) \ 68 (0x0ull | (uint64_t)(a) << 12 | (uint64_t)(b) << 3) 69 #define RVU_PF_VF_BAR4_ADDR (0x10ull) 70 71 #define RVU_PF_DISC (0x0ull) /* [CN20K, .) */ 72 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200ull | (uint64_t)(a) << 3) /* [CN9K, CN20K) */ 73 #define RVU_PF_VFME_STATUSX(a) (0x800ull | (uint64_t)(a) << 3) 74 #define RVU_PF_VFTRPENDX(a) (0x820ull | (uint64_t)(a) << 3) 75 #define RVU_PF_VFTRPEND_W1SX(a) (0x840ull | (uint64_t)(a) << 3) 76 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880ull | (uint64_t)(a) << 3) 77 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8a0ull | (uint64_t)(a) << 3) 78 #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8c0ull | (uint64_t)(a) << 3) 79 #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8e0ull | (uint64_t)(a) << 3) 80 #define RVU_PF_VFFLR_INTX(a) (0x900ull | (uint64_t)(a) << 3) 81 #define RVU_PF_VFFLR_INT_W1SX(a) (0x920ull | (uint64_t)(a) << 3) 82 #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940ull | (uint64_t)(a) << 3) 83 #define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960ull | (uint64_t)(a) << 3) 84 #define RVU_PF_VFME_INTX(a) (0x980ull | (uint64_t)(a) << 3) 85 #define RVU_PF_VFME_INT_W1SX(a) (0x9a0ull | (uint64_t)(a) << 3) 86 #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9c0ull | (uint64_t)(a) << 3) 87 #define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9e0ull | (uint64_t)(a) << 3) 88 #define RVU_PF_PFAF_MBOXX(a) (0xc00ull | (uint64_t)(a) << 3) 89 #define RVU_PF_INT (0xc20ull) 90 #define RVU_PF_INT_W1S (0xc28ull) 91 #define RVU_PF_INT_ENA_W1S (0xc30ull) 92 #define RVU_PF_INT_ENA_W1C (0xc38ull) 93 #define RVU_PF_MSIX_VECX_ADDR(a) (0x80000ull | (uint64_t)(a) << 4) 94 #define RVU_PF_MSIX_VECX_CTL(a) (0x80008ull | (uint64_t)(a) << 4) 95 #define RVU_PF_MSIX_PBAX(a) (0xf0000ull | (uint64_t)(a) << 3) 96 #define RVU_VF_DISC (0x0ull) /* [CN20K, .) */ 97 #define RVU_VF_VFPF_MBOXX(a) (0x0ull | (uint64_t)(a) << 3) /* [CN9K, CN20K) */ 98 #define RVU_VF_INT (0x20ull) 99 #define RVU_VF_INT_W1S (0x28ull) 100 #define RVU_VF_INT_ENA_W1S (0x30ull) 101 #define RVU_VF_INT_ENA_W1C (0x38ull) 102 #define RVU_VF_BLOCK_ADDRX_DISC(a) (0x200ull | (uint64_t)(a) << 3) 103 #define RVU_VF_MSIX_VECX_ADDR(a) (0x80000ull | (uint64_t)(a) << 4) 104 #define RVU_VF_MSIX_VECX_CTL(a) (0x80008ull | (uint64_t)(a) << 4) 105 #define RVU_VF_MBOX_REGION (0xc0000ull) /* [CN10K, .) */ 106 #define RVU_VF_MSIX_PBAX(a) (0xf0000ull | (uint64_t)(a) << 3) 107 108 /* CN20k RVU mbox registers */ 109 #define RVU_MBOX_AF_AFPFX_TRIGX(a) (0x9000 | (a) << 3) 110 #define RVU_MBOX_PF_PFAF_TRIGX(a) RVU_PF_PFAF_MBOXX(a) 111 #define RVU_MBOX_PF_VFX_PFVF_TRIGX(a) (0x2000 | (a) << 3) 112 #define RVU_MBOX_VF_VFPF_TRIGX(a) (0x3000 | (a) << 3) 113 114 #define RVU_PF_VF_MBOX_ADDR (0xC40) 115 116 /* cn20k Enum */ 117 #define RVU_PFX_FUNC_PFAF_MBOX (0x80000) 118 119 #define RVU_FUNC_BLKADDR_SHIFT 20 120 #define RVU_FUNC_BLKADDR_MASK 0x1FULL 121 122 /* Enum offsets */ 123 124 #define RVU_BAR_RVU_PF_END_BAR0 (0x84f000000000ull) 125 #define RVU_BAR_RVU_PF_START_BAR0 (0x840000000000ull) 126 #define RVU_BAR_RVU_PFX_FUNCX_BAR2(a, b) \ 127 (0x840200000000ull | ((uint64_t)(a) << 36) | ((uint64_t)(b) << 25)) 128 129 #define RVU_AF_INT_VEC_POISON (0x0ull) 130 #define RVU_AF_INT_VEC_PFFLR (0x1ull) 131 #define RVU_AF_INT_VEC_PFME (0x2ull) 132 #define RVU_AF_INT_VEC_GEN (0x3ull) 133 #define RVU_AF_INT_VEC_MBOX (0x4ull) 134 135 #define RVU_BLOCK_TYPE_RVUM (0x0ull) 136 #define RVU_BLOCK_TYPE_LMT (0x2ull) 137 #define RVU_BLOCK_TYPE_NIX (0x3ull) 138 #define RVU_BLOCK_TYPE_NPA (0x4ull) 139 #define RVU_BLOCK_TYPE_NPC (0x5ull) 140 #define RVU_BLOCK_TYPE_SSO (0x6ull) 141 #define RVU_BLOCK_TYPE_SSOW (0x7ull) 142 #define RVU_BLOCK_TYPE_TIM (0x8ull) 143 #define RVU_BLOCK_TYPE_CPT (0x9ull) 144 #define RVU_BLOCK_TYPE_NDC (0xaull) 145 #define RVU_BLOCK_TYPE_DDF (0xbull) 146 #define RVU_BLOCK_TYPE_ZIP (0xcull) 147 #define RVU_BLOCK_TYPE_RAD (0xdull) 148 #define RVU_BLOCK_TYPE_DFA (0xeull) 149 #define RVU_BLOCK_TYPE_HNA (0xfull) 150 #define RVU_BLOCK_TYPE_REE (0xeull) 151 152 #define RVU_BLOCK_ADDR_RVUM (0x0ull) 153 #define RVU_BLOCK_ADDR_LMT (0x1ull) 154 #define RVU_BLOCK_ADDR_NPA (0x3ull) 155 #define RVU_BLOCK_ADDR_NIX0 (0x4ull) 156 #define RVU_BLOCK_ADDR_NIX1 (0x5ull) 157 #define RVU_BLOCK_ADDR_NPC (0x6ull) 158 #define RVU_BLOCK_ADDR_SSO (0x7ull) 159 #define RVU_BLOCK_ADDR_SSOW (0x8ull) 160 #define RVU_BLOCK_ADDR_TIM (0x9ull) 161 #define RVU_BLOCK_ADDR_CPT0 (0xaull) 162 #define RVU_BLOCK_ADDR_CPT1 (0xbull) 163 #define RVU_BLOCK_ADDR_NDC0 (0xcull) 164 #define RVU_BLOCK_ADDR_NDC1 (0xdull) 165 #define RVU_BLOCK_ADDR_NDC2 (0xeull) 166 #define RVU_BLOCK_ADDR_R_END (0x1full) 167 #define RVU_BLOCK_ADDR_R_START (0x14ull) 168 #define RVU_BLOCK_ADDR_REE0 (0x14ull) 169 #define RVU_BLOCK_ADDR_REE1 (0x15ull) 170 #define RVU_BLOCK_ADDR_MBOX (0x1bULL) 171 172 #define RVU_VF_INT_VEC_MBOX (0x0ull) 173 174 #define RVU_PF_INT_VEC_AFPF_MBOX (0x6ull) 175 #define RVU_PF_INT_VEC_VFFLR0 (0x0ull) 176 #define RVU_PF_INT_VEC_VFFLR1 (0x1ull) 177 #define RVU_PF_INT_VEC_VFME0 (0x2ull) 178 #define RVU_PF_INT_VEC_VFME1 (0x3ull) 179 #define RVU_PF_INT_VEC_VFPF_MBOX0 (0x4ull) 180 #define RVU_PF_INT_VEC_VFPF_MBOX1 (0x5ull) 181 182 #define RVU_MBOX_PF_INT_VEC_VFPF_MBOX0 (0x4ull) 183 #define RVU_MBOX_PF_INT_VEC_VFPF_MBOX1 (0x5ull) 184 #define RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0 (0x6ull) 185 #define RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1 (0x7ull) 186 #define RVU_MBOX_PF_INT_VEC_AFPF_MBOX (0x8ull) 187 188 #define RVU_MBOX_PF_VFPF_INTX(a) (0x1000 | (a) << 3) 189 #define RVU_MBOX_PF_VFPF_INT_W1SX(a) (0x1020 | (a) << 3) 190 #define RVU_MBOX_PF_VFPF_INT_ENA_W1SX(a) (0x1040 | (a) << 3) 191 #define RVU_MBOX_PF_VFPF_INT_ENA_W1CX(a) (0x1060 | (a) << 3) 192 193 #define RVU_MBOX_PF_VFPF1_INTX(a) (0x1080 | (a) << 3) 194 #define RVU_MBOX_PF_VFPF1_INT_W1SX(a) (0x10a0 | (a) << 3) 195 #define RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(a) (0x10c0 | (a) << 3) 196 #define RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(a) (0x10e0 | (a) << 3) 197 198 #define AF_BAR2_ALIASX_SIZE (0x100000ull) 199 200 #define TIM_AF_BAR2_SEL (0x9000000ull) 201 #define SSO_AF_BAR2_SEL (0x9000000ull) 202 #define NIX_AF_BAR2_SEL (0x9000000ull) 203 #define SSOW_AF_BAR2_SEL (0x9000000ull) 204 #define NPA_AF_BAR2_SEL (0x9000000ull) 205 #define CPT_AF_BAR2_SEL (0x9000000ull) 206 #define RVU_AF_BAR2_SEL (0x9000000ull) 207 #define REE_AF_BAR2_SEL (0x9000000ull) 208 209 #define AF_BAR2_ALIASX(a, b) \ 210 (0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b)) 211 #define TIM_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) 212 #define SSO_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) 213 #define NIX_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(0, b) 214 #define SSOW_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) 215 #define NPA_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(0, b) 216 #define CPT_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) 217 #define RVU_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) 218 #define REE_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) 219 220 /* Structures definitions */ 221 222 /* RVU admin function register address structure */ 223 struct rvu_af_addr_s { 224 uint64_t addr : 28; 225 uint64_t block : 5; 226 uint64_t rsvd_63_33 : 31; 227 }; 228 229 /* RVU function-unique address structure */ 230 struct rvu_func_addr_s { 231 uint32_t addr : 12; 232 uint32_t lf_slot : 8; 233 uint32_t block : 5; 234 uint32_t rsvd_31_25 : 7; 235 }; 236 237 /* RVU msi-x vector structure */ 238 struct rvu_msix_vec_s { 239 uint64_t addr : 64; /* W0 */ 240 uint64_t data : 32; 241 uint64_t mask : 1; 242 uint64_t pend : 1; 243 uint64_t rsvd_127_98 : 30; 244 }; 245 246 /* RVU pf function identification structure */ 247 struct rvu_pf_func_s { 248 uint16_t func : 10; 249 uint16_t pf : 6; 250 }; 251 252 #define RVU_CN9K_LMT_SLOT_MAX 256ULL 253 #define RVU_CN9K_LMT_SLOT_MASK (RVU_CN9K_LMT_SLOT_MAX - 1) 254 255 #define RVU_LMT_SZ 128ULL 256 257 /* 2048 LMT lines in BAR4 [CN10k, .) */ 258 #define RVU_LMT_LINE_MAX 2048 259 #define RVU_LMT_LINE_BURST_MAX (uint16_t)32 /* [CN10K, .) */ 260 261 #endif /* __RVU_HW_H__ */ 262