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Searched refs:reg_offset (Results 1 – 25 of 134) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/amd/amdgpu/
H A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in arct_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in arct_reg_base_init()
43 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in arct_reg_base_init()
[all …]
H A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in aldebaran_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init()
41 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in aldebaran_reg_base_init()
42 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in aldebaran_reg_base_init()
43 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in aldebaran_reg_base_init()
[all …]
H A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
42 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
[all …]
H A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
43 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
[all …]
H A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
[all …]
H A Djpeg_v1_0.c42 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) in jpeg_v1_0_decode_ring_patch_wreg()
46 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_patch_wreg()
47 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_patch_wreg()
49 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
51 ring->ring[(*ptr)++] = reg_offset; in jpeg_v1_0_decode_ring_patch_wreg()
61 uint32_t reg, reg_offset, val, mask, i; in jpeg_v1_0_decode_ring_set_patch_ring()
65 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
67 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, va in jpeg_v1_0_decode_ring_set_patch_ring()
38 jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring * ring,uint32_t * ptr,uint32_t reg_offset,uint32_t val) jpeg_v1_0_decode_ring_patch_wreg() argument
57 uint32_t reg, reg_offset, val, mask, i; jpeg_v1_0_decode_ring_set_patch_ring() local
351 uint32_t reg_offset = (reg << 2); jpeg_v1_0_decode_ring_emit_reg_wait() local
395 uint32_t reg_offset = (reg << 2); jpeg_v1_0_decode_ring_emit_wreg() local
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H A Dsoc15_common.h36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
51 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
53 adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
59 …__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, …
61 adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
67 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
75 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
79 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)) + \
83 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
[all …]
H A Dmmsch_v1_0.h61 uint32_t reg_offset : 28; member
66 uint32_t reg_offset : 20; member
99 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt() argument
102 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
109 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt() argument
112 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
121 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll() argument
124 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
H A Dsdma_v4_4.c40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0]; in sdma_v4_4_get_reg_offset()
167 uint32_t reg_offset, in sdma_v4_4_get_ras_error_count() argument
177 if (sdma_v4_4_ras_fields[i].reg_offset != reg_offset) in sdma_v4_4_get_ras_error_count()
202 uint32_t reg_offset = 0; in sdma_v4_4_query_ras_error_count_by_instance() local
204 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER); in sdma_v4_4_query_ras_error_count_by_instance()
205 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
211 reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2); in sdma_v4_4_query_ras_error_count_by_instance()
212 reg_value = RREG32(reg_offset); in sdma_v4_4_query_ras_error_count_by_instance()
239 uint32_t reg_offset; in sdma_v4_4_reset_ras_error_count() local
244 reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER); in sdma_v4_4_reset_ras_error_count()
[all …]
H A Dmmsch_v2_0.h245 uint32_t reg_offset : 28; member
250 uint32_t reg_offset : 20; member
283 uint32_t reg_offset, in mmsch_v2_0_insert_direct_wt() argument
286 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_wt()
293 uint32_t reg_offset, in mmsch_v2_0_insert_direct_rd_mod_wt() argument
296 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_rd_mod_wt()
305 uint32_t reg_offset, in mmsch_v2_0_insert_direct_poll() argument
308 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_poll()
H A Dsoc15.h56 uint32_t reg_offset; member
63 uint32_t reg_offset; member
73 uint32_t reg_offset; member
82 uint32_t reg_offset; member
91 …define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.…
H A Dmmsch_v3_0.h56 uint32_t reg_offset : 28; member
61 uint32_t reg_offset : 20; member
95 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
106 direct_wt.cmd_header.reg_offset = reg; \
116 direct_poll.cmd_header.reg_offset = reg; \
H A Dmmsch_v4_0.h70 uint32_t reg_offset : 28; member
75 uint32_t reg_offset : 20; member
109 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
120 direct_wt.cmd_header.reg_offset = reg; \
130 direct_poll.cmd_header.reg_offset = reg; \
H A Djpeg_v4_0_3.c506 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); in jpeg_v4_0_3_start()
518 reg_offset, 0); in jpeg_v4_0_3_start()
521 reg_offset, in jpeg_v4_0_3_start()
526 reg_offset, lower_32_bits(ring->gpu_addr)); in jpeg_v4_0_3_start()
530 reg_offset, upper_32_bits(ring->gpu_addr)); in jpeg_v4_0_3_start()
533 reg_offset, 0); in jpeg_v4_0_3_start()
536 reg_offset, 0); in jpeg_v4_0_3_start()
539 reg_offset, 0x00000002L); in jpeg_v4_0_3_start()
542 reg_offset, ring->ring_size / 4); in jpeg_v4_0_3_start()
545 reg_offset); in jpeg_v4_0_3_start()
505 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); jpeg_v4_0_3_start() local
817 uint32_t reg_offset = (reg << 2); jpeg_v4_0_3_dec_ring_emit_reg_wait() local
858 uint32_t reg_offset = (reg << 2); jpeg_v4_0_3_dec_ring_emit_wreg() local
894 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); jpeg_v4_0_3_is_idle() local
916 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); jpeg_v4_0_3_wait_for_idle() local
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H A Dsoc21.c272 u32 sh_num, u32 reg_offset) in soc21_read_indexed_register() argument
280 val = RREG32(reg_offset); in soc21_read_indexed_register()
290 u32 sh_num, u32 reg_offset) in soc21_get_register_value() argument
293 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
295 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) in soc21_get_register_value()
297 return RREG32(reg_offset); in soc21_get_register_value()
302 u32 sh_num, u32 reg_offset, u32 *value) in soc21_read_register() argument
310 if (!adev->reg_offset[en->hwip][en->inst]) in soc21_read_register()
312 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc21_read_register()
313 + en->reg_offset)) in soc21_read_register()
[all …]
H A Dgfx_v8_0.c2079 u32 reg_offset; in gfx_v8_0_tiling_mode_table_init() local
2084 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2085 modearray[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2087 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2088 mod2array[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2252 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2253 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && in gfx_v8_0_tiling_mode_table_init()
2254 reg_offset != 23) in gfx_v8_0_tiling_mode_table_init()
2255 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2257 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
[all …]
H A Djpeg_v2_0.c591 uint32_t reg_offset = (reg << 2); in jpeg_v2_0_dec_ring_emit_reg_wait() local
603 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v2_0_dec_ring_emit_reg_wait()
606 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_reg_wait()
608 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_reg_wait()
632 uint32_t reg_offset = (reg << 2); in jpeg_v2_0_dec_ring_emit_wreg() local
636 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v2_0_dec_ring_emit_wreg()
639 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
641 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_wreg()
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H A Dnv.c359 u32 sh_num, u32 reg_offset) in nv_read_indexed_register() argument
367 val = RREG32(reg_offset); in nv_read_indexed_register()
377 u32 sh_num, u32 reg_offset) in nv_get_register_value() argument
380 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
382 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) in nv_get_register_value()
384 return RREG32(reg_offset); in nv_get_register_value()
389 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register() argument
397 if (!adev->reg_offset[en->hwip][en->inst]) in nv_read_register()
399 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in nv_read_register()
400 + en->reg_offset)) in nv_read_register()
[all …]
H A Dsoc15.c381 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register() argument
389 val = RREG32(reg_offset); in soc15_read_indexed_register()
399 u32 sh_num, u32 reg_offset) in soc15_get_register_value() argument
402 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
404 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) in soc15_get_register_value()
406 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) in soc15_get_register_value()
408 return RREG32(reg_offset); in soc15_get_register_value()
413 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register() argument
421 if (!adev->reg_offset[en->hwip][en->inst]) in soc15_read_register()
423 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
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/openbsd-src/sys/dev/pci/drm/radeon/
H A Dcik_sdma.c251 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
260 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
262 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
266 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); in cik_sdma_gfx_stop()
305 uint32_t reg_offset, value; in cik_sdma_ctx_switch_enable() local
310 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
312 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
313 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
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H A Dni_dma.c191 u32 reg_offset, wb_offset; in cayman_dma_resume() local
197 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
201 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
205 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
206 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
214 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
217 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
218 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
221 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
223 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
[all …]
/openbsd-src/gnu/usr.bin/binutils/gdb/
H A Damd64-nat.c58 int *reg_offset = amd64_native_gregset64_reg_offset; in amd64_native_gregset_reg_offset() local
65 reg_offset = amd64_native_gregset32_reg_offset; in amd64_native_gregset_reg_offset()
73 return reg_offset[regnum]; in amd64_native_gregset_reg_offset()
/openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dcommon_baco.c92 reg = entry[i].reg_offset; in baco_program_registers()
112 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg] in soc15_baco_program_registers()
113 + entry[i].reg_offset; in soc15_baco_program_registers()
H A Dcommon_baco.h38 uint32_t reg_offset; member
50 uint32_t reg_offset; member
/openbsd-src/gnu/gcc/gcc/
H A Dpostreload.c1171 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; variable
1248 rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno], in reload_cse_move2add()
1262 if (INTVAL (src) == reg_offset [regno]) in reload_cse_move2add()
1280 && ((reg_offset[regno] in reload_cse_move2add()
1302 reg_offset[regno] = INTVAL (src); in reload_cse_move2add()
1334 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; in reload_cse_move2add()
1335 HOST_WIDE_INT regno_offset = reg_offset[regno]; in reload_cse_move2add()
1364 reg_offset[regno] = in reload_cse_move2add()
1488 offset = reg_offset[REGNO (XEXP (src, 1))]; in move2add_note_store()
1497 offset = reg_offset[REGNO (base_reg)]; in move2add_note_store()
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