1fb4d8502Sjsg /*
2fb4d8502Sjsg * Copyright 2014 Advanced Micro Devices, Inc.
3fb4d8502Sjsg *
4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg *
11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg * all copies or substantial portions of the Software.
13fb4d8502Sjsg *
14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg *
22fb4d8502Sjsg */
23c349dbc7Sjsg
24c349dbc7Sjsg #include <linux/delay.h>
25fb4d8502Sjsg #include <linux/kernel.h>
26fb4d8502Sjsg #include <linux/firmware.h>
27c349dbc7Sjsg #include <linux/module.h>
28c349dbc7Sjsg #include <linux/pci.h>
29c349dbc7Sjsg
30fb4d8502Sjsg #include "amdgpu.h"
31fb4d8502Sjsg #include "amdgpu_gfx.h"
325ca02815Sjsg #include "amdgpu_ring.h"
33fb4d8502Sjsg #include "vi.h"
34fb4d8502Sjsg #include "vi_structs.h"
35fb4d8502Sjsg #include "vid.h"
36fb4d8502Sjsg #include "amdgpu_ucode.h"
37fb4d8502Sjsg #include "amdgpu_atombios.h"
38fb4d8502Sjsg #include "atombios_i2c.h"
39fb4d8502Sjsg #include "clearstate_vi.h"
40fb4d8502Sjsg
41fb4d8502Sjsg #include "gmc/gmc_8_2_d.h"
42fb4d8502Sjsg #include "gmc/gmc_8_2_sh_mask.h"
43fb4d8502Sjsg
44fb4d8502Sjsg #include "oss/oss_3_0_d.h"
45fb4d8502Sjsg #include "oss/oss_3_0_sh_mask.h"
46fb4d8502Sjsg
47fb4d8502Sjsg #include "bif/bif_5_0_d.h"
48fb4d8502Sjsg #include "bif/bif_5_0_sh_mask.h"
49fb4d8502Sjsg #include "gca/gfx_8_0_d.h"
50fb4d8502Sjsg #include "gca/gfx_8_0_enum.h"
51fb4d8502Sjsg #include "gca/gfx_8_0_sh_mask.h"
52fb4d8502Sjsg
53fb4d8502Sjsg #include "dce/dce_10_0_d.h"
54fb4d8502Sjsg #include "dce/dce_10_0_sh_mask.h"
55fb4d8502Sjsg
56fb4d8502Sjsg #include "smu/smu_7_1_3_d.h"
57fb4d8502Sjsg
58fb4d8502Sjsg #include "ivsrcid/ivsrcid_vislands30.h"
59fb4d8502Sjsg
60fb4d8502Sjsg #define GFX8_NUM_GFX_RINGS 1
61c349dbc7Sjsg #define GFX8_MEC_HPD_SIZE 4096
62fb4d8502Sjsg
63fb4d8502Sjsg #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64fb4d8502Sjsg #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65fb4d8502Sjsg #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66fb4d8502Sjsg #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
67fb4d8502Sjsg
68fb4d8502Sjsg #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
69fb4d8502Sjsg #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
70fb4d8502Sjsg #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
71fb4d8502Sjsg #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
72fb4d8502Sjsg #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
73fb4d8502Sjsg #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
74fb4d8502Sjsg #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
75fb4d8502Sjsg #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
76fb4d8502Sjsg #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
77fb4d8502Sjsg
78fb4d8502Sjsg #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
79fb4d8502Sjsg #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
80fb4d8502Sjsg #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
81fb4d8502Sjsg #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
82fb4d8502Sjsg #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
83fb4d8502Sjsg #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
84fb4d8502Sjsg
85fb4d8502Sjsg /* BPM SERDES CMD */
86fb4d8502Sjsg #define SET_BPM_SERDES_CMD 1
87fb4d8502Sjsg #define CLE_BPM_SERDES_CMD 0
88fb4d8502Sjsg
89fb4d8502Sjsg /* BPM Register Address*/
90fb4d8502Sjsg enum {
91fb4d8502Sjsg BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
92fb4d8502Sjsg BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
93fb4d8502Sjsg BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
94fb4d8502Sjsg BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
95fb4d8502Sjsg BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
96fb4d8502Sjsg BPM_REG_FGCG_MAX
97fb4d8502Sjsg };
98fb4d8502Sjsg
99fb4d8502Sjsg #define RLC_FormatDirectRegListLength 14
100fb4d8502Sjsg
101fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
102fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
103fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
104fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
105fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
106fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
107fb4d8502Sjsg
108fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
109fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
110fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/stoney_me.bin");
111fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
112fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
113fb4d8502Sjsg
114fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
115fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
116fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/tonga_me.bin");
117fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
118fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
119fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
120fb4d8502Sjsg
121fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
122fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
123fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/topaz_me.bin");
124fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
125fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
126fb4d8502Sjsg
127fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
128fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
129fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/fiji_me.bin");
130fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
131fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
132fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
133fb4d8502Sjsg
134fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
135fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
136fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
137fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
138fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
139fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
140fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
141fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
142fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
143fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
144fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
145fb4d8502Sjsg
146fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
147fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
148fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
149fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
150fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
151fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
152fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
153fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
154fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
155fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
156fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
157fb4d8502Sjsg
158fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
159fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
160fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
161fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
162fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
163fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
164fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
165fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
166fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
167fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
168fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
169fb4d8502Sjsg
170fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
171fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
172fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/vegam_me.bin");
173fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
174fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
175fb4d8502Sjsg MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
176fb4d8502Sjsg
177fb4d8502Sjsg static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
178fb4d8502Sjsg {
179fb4d8502Sjsg {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
180fb4d8502Sjsg {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
181fb4d8502Sjsg {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
182fb4d8502Sjsg {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
183fb4d8502Sjsg {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
184fb4d8502Sjsg {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
185fb4d8502Sjsg {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
186fb4d8502Sjsg {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
187fb4d8502Sjsg {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
188fb4d8502Sjsg {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
189fb4d8502Sjsg {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
190fb4d8502Sjsg {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
191fb4d8502Sjsg {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
192fb4d8502Sjsg {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
193fb4d8502Sjsg {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
194fb4d8502Sjsg {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
195fb4d8502Sjsg };
196fb4d8502Sjsg
197fb4d8502Sjsg static const u32 golden_settings_tonga_a11[] =
198fb4d8502Sjsg {
199fb4d8502Sjsg mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
200fb4d8502Sjsg mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
201fb4d8502Sjsg mmDB_DEBUG2, 0xf00fffff, 0x00000400,
202fb4d8502Sjsg mmGB_GPU_ID, 0x0000000f, 0x00000000,
203fb4d8502Sjsg mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
204fb4d8502Sjsg mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
205fb4d8502Sjsg mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
206fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
207fb4d8502Sjsg mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
208fb4d8502Sjsg mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
209fb4d8502Sjsg mmTCC_CTRL, 0x00100000, 0xf31fff7f,
210fb4d8502Sjsg mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
211fb4d8502Sjsg mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
212fb4d8502Sjsg mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
213fb4d8502Sjsg mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
214fb4d8502Sjsg mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
215fb4d8502Sjsg };
216fb4d8502Sjsg
217fb4d8502Sjsg static const u32 tonga_golden_common_all[] =
218fb4d8502Sjsg {
219fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
221fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
222fb4d8502Sjsg mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
223fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
224fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
225fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
226fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
227fb4d8502Sjsg };
228fb4d8502Sjsg
229fb4d8502Sjsg static const u32 tonga_mgcg_cgcg_init[] =
230fb4d8502Sjsg {
231fb4d8502Sjsg mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
232fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
233fb4d8502Sjsg mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
234fb4d8502Sjsg mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
235fb4d8502Sjsg mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
236fb4d8502Sjsg mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
237fb4d8502Sjsg mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
238fb4d8502Sjsg mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
239fb4d8502Sjsg mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
240fb4d8502Sjsg mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
241fb4d8502Sjsg mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
242fb4d8502Sjsg mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
243fb4d8502Sjsg mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
244fb4d8502Sjsg mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
245fb4d8502Sjsg mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
246fb4d8502Sjsg mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
247fb4d8502Sjsg mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
248fb4d8502Sjsg mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
249fb4d8502Sjsg mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
250fb4d8502Sjsg mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
251fb4d8502Sjsg mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
252fb4d8502Sjsg mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
253fb4d8502Sjsg mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
254fb4d8502Sjsg mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
255fb4d8502Sjsg mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
256fb4d8502Sjsg mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
257fb4d8502Sjsg mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
258fb4d8502Sjsg mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259fb4d8502Sjsg mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
260fb4d8502Sjsg mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
261fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
262fb4d8502Sjsg mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263fb4d8502Sjsg mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264fb4d8502Sjsg mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
265fb4d8502Sjsg mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266fb4d8502Sjsg mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267fb4d8502Sjsg mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268fb4d8502Sjsg mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269fb4d8502Sjsg mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
270fb4d8502Sjsg mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271fb4d8502Sjsg mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272fb4d8502Sjsg mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273fb4d8502Sjsg mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274fb4d8502Sjsg mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
275fb4d8502Sjsg mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276fb4d8502Sjsg mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277fb4d8502Sjsg mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278fb4d8502Sjsg mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279fb4d8502Sjsg mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
280fb4d8502Sjsg mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281fb4d8502Sjsg mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282fb4d8502Sjsg mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283fb4d8502Sjsg mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284fb4d8502Sjsg mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
285fb4d8502Sjsg mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286fb4d8502Sjsg mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287fb4d8502Sjsg mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288fb4d8502Sjsg mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289fb4d8502Sjsg mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
290fb4d8502Sjsg mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291fb4d8502Sjsg mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292fb4d8502Sjsg mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293fb4d8502Sjsg mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294fb4d8502Sjsg mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
295fb4d8502Sjsg mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296fb4d8502Sjsg mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297fb4d8502Sjsg mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
298fb4d8502Sjsg mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
299fb4d8502Sjsg mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
300fb4d8502Sjsg mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
301fb4d8502Sjsg mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
302fb4d8502Sjsg mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
303fb4d8502Sjsg mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
304fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
305fb4d8502Sjsg mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
306fb4d8502Sjsg };
307fb4d8502Sjsg
308fb4d8502Sjsg static const u32 golden_settings_vegam_a11[] =
309fb4d8502Sjsg {
310fb4d8502Sjsg mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
311fb4d8502Sjsg mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
312fb4d8502Sjsg mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
313fb4d8502Sjsg mmDB_DEBUG2, 0xf00fffff, 0x00000400,
314fb4d8502Sjsg mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
315fb4d8502Sjsg mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
317fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
318fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
319fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
320fb4d8502Sjsg mmSQ_CONFIG, 0x07f80000, 0x01180000,
321fb4d8502Sjsg mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
322fb4d8502Sjsg mmTCC_CTRL, 0x00100000, 0xf31fff7f,
323fb4d8502Sjsg mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
324fb4d8502Sjsg mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
325fb4d8502Sjsg mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
326fb4d8502Sjsg mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
327fb4d8502Sjsg };
328fb4d8502Sjsg
329fb4d8502Sjsg static const u32 vegam_golden_common_all[] =
330fb4d8502Sjsg {
331fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332fb4d8502Sjsg mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
333fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
334fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
335fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
336fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
337fb4d8502Sjsg };
338fb4d8502Sjsg
339fb4d8502Sjsg static const u32 golden_settings_polaris11_a11[] =
340fb4d8502Sjsg {
341fb4d8502Sjsg mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
342fb4d8502Sjsg mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
343fb4d8502Sjsg mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
344fb4d8502Sjsg mmDB_DEBUG2, 0xf00fffff, 0x00000400,
345fb4d8502Sjsg mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
346fb4d8502Sjsg mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
347fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
348fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
349fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
351fb4d8502Sjsg mmSQ_CONFIG, 0x07f80000, 0x01180000,
352fb4d8502Sjsg mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
353fb4d8502Sjsg mmTCC_CTRL, 0x00100000, 0xf31fff7f,
354fb4d8502Sjsg mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
355fb4d8502Sjsg mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
356fb4d8502Sjsg mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
357fb4d8502Sjsg mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
358fb4d8502Sjsg };
359fb4d8502Sjsg
360fb4d8502Sjsg static const u32 polaris11_golden_common_all[] =
361fb4d8502Sjsg {
362fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
363fb4d8502Sjsg mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
364fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
368fb4d8502Sjsg };
369fb4d8502Sjsg
370fb4d8502Sjsg static const u32 golden_settings_polaris10_a11[] =
371fb4d8502Sjsg {
372fb4d8502Sjsg mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
373fb4d8502Sjsg mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
374fb4d8502Sjsg mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
375fb4d8502Sjsg mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376fb4d8502Sjsg mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377fb4d8502Sjsg mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378fb4d8502Sjsg mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
380fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
381fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
382fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
383fb4d8502Sjsg mmSQ_CONFIG, 0x07f80000, 0x07180000,
384fb4d8502Sjsg mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
385fb4d8502Sjsg mmTCC_CTRL, 0x00100000, 0xf31fff7f,
386fb4d8502Sjsg mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
387fb4d8502Sjsg mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
388fb4d8502Sjsg mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
389fb4d8502Sjsg };
390fb4d8502Sjsg
391fb4d8502Sjsg static const u32 polaris10_golden_common_all[] =
392fb4d8502Sjsg {
393fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
394fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
395fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
396fb4d8502Sjsg mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
397fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
398fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
399fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
400fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
401fb4d8502Sjsg };
402fb4d8502Sjsg
403fb4d8502Sjsg static const u32 fiji_golden_common_all[] =
404fb4d8502Sjsg {
405fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
406fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
407fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
408fb4d8502Sjsg mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
409fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
410fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
411fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
412fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
413fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
414fb4d8502Sjsg mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
415fb4d8502Sjsg };
416fb4d8502Sjsg
417fb4d8502Sjsg static const u32 golden_settings_fiji_a10[] =
418fb4d8502Sjsg {
419fb4d8502Sjsg mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
420fb4d8502Sjsg mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421fb4d8502Sjsg mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
422fb4d8502Sjsg mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
423fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
424fb4d8502Sjsg mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425fb4d8502Sjsg mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
426fb4d8502Sjsg mmTCC_CTRL, 0x00100000, 0xf31fff7f,
427fb4d8502Sjsg mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
428fb4d8502Sjsg mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
429fb4d8502Sjsg mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
430fb4d8502Sjsg };
431fb4d8502Sjsg
432fb4d8502Sjsg static const u32 fiji_mgcg_cgcg_init[] =
433fb4d8502Sjsg {
434fb4d8502Sjsg mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
435fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
436fb4d8502Sjsg mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
437fb4d8502Sjsg mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
438fb4d8502Sjsg mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
439fb4d8502Sjsg mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
440fb4d8502Sjsg mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
441fb4d8502Sjsg mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
442fb4d8502Sjsg mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
443fb4d8502Sjsg mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
444fb4d8502Sjsg mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
445fb4d8502Sjsg mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
446fb4d8502Sjsg mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
447fb4d8502Sjsg mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
448fb4d8502Sjsg mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
449fb4d8502Sjsg mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
450fb4d8502Sjsg mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
451fb4d8502Sjsg mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
452fb4d8502Sjsg mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
453fb4d8502Sjsg mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
454fb4d8502Sjsg mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
455fb4d8502Sjsg mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
456fb4d8502Sjsg mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
457fb4d8502Sjsg mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
458fb4d8502Sjsg mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
459fb4d8502Sjsg mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
460fb4d8502Sjsg mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
461fb4d8502Sjsg mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462fb4d8502Sjsg mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463fb4d8502Sjsg mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
464fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
465fb4d8502Sjsg mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
466fb4d8502Sjsg mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
467fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
468fb4d8502Sjsg mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
469fb4d8502Sjsg };
470fb4d8502Sjsg
471fb4d8502Sjsg static const u32 golden_settings_iceland_a11[] =
472fb4d8502Sjsg {
473fb4d8502Sjsg mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
474fb4d8502Sjsg mmDB_DEBUG2, 0xf00fffff, 0x00000400,
475fb4d8502Sjsg mmDB_DEBUG3, 0xc0000000, 0xc0000000,
476fb4d8502Sjsg mmGB_GPU_ID, 0x0000000f, 0x00000000,
477fb4d8502Sjsg mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
478fb4d8502Sjsg mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
479fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
480fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
481fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
482fb4d8502Sjsg mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
483fb4d8502Sjsg mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
484fb4d8502Sjsg mmTCC_CTRL, 0x00100000, 0xf31fff7f,
485fb4d8502Sjsg mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
486fb4d8502Sjsg mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
487fb4d8502Sjsg mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
488fb4d8502Sjsg mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
489fb4d8502Sjsg };
490fb4d8502Sjsg
491fb4d8502Sjsg static const u32 iceland_golden_common_all[] =
492fb4d8502Sjsg {
493fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
494fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
495fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
496fb4d8502Sjsg mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
497fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
498fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
499fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
500fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
501fb4d8502Sjsg };
502fb4d8502Sjsg
503fb4d8502Sjsg static const u32 iceland_mgcg_cgcg_init[] =
504fb4d8502Sjsg {
505fb4d8502Sjsg mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
506fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
507fb4d8502Sjsg mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
508fb4d8502Sjsg mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
509fb4d8502Sjsg mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
510fb4d8502Sjsg mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
511fb4d8502Sjsg mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
512fb4d8502Sjsg mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
513fb4d8502Sjsg mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
514fb4d8502Sjsg mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
515fb4d8502Sjsg mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
516fb4d8502Sjsg mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
517fb4d8502Sjsg mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
518fb4d8502Sjsg mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
519fb4d8502Sjsg mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
520fb4d8502Sjsg mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
521fb4d8502Sjsg mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
522fb4d8502Sjsg mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
523fb4d8502Sjsg mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
524fb4d8502Sjsg mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
525fb4d8502Sjsg mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
526fb4d8502Sjsg mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
527fb4d8502Sjsg mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
528fb4d8502Sjsg mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
529fb4d8502Sjsg mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
530fb4d8502Sjsg mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
531fb4d8502Sjsg mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
532fb4d8502Sjsg mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533fb4d8502Sjsg mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
534fb4d8502Sjsg mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
535fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536fb4d8502Sjsg mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537fb4d8502Sjsg mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538fb4d8502Sjsg mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
539fb4d8502Sjsg mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540fb4d8502Sjsg mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541fb4d8502Sjsg mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542fb4d8502Sjsg mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543fb4d8502Sjsg mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
544fb4d8502Sjsg mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545fb4d8502Sjsg mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546fb4d8502Sjsg mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547fb4d8502Sjsg mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548fb4d8502Sjsg mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
549fb4d8502Sjsg mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550fb4d8502Sjsg mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551fb4d8502Sjsg mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552fb4d8502Sjsg mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553fb4d8502Sjsg mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
554fb4d8502Sjsg mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555fb4d8502Sjsg mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556fb4d8502Sjsg mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557fb4d8502Sjsg mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558fb4d8502Sjsg mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
559fb4d8502Sjsg mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560fb4d8502Sjsg mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561fb4d8502Sjsg mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
562fb4d8502Sjsg mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
563fb4d8502Sjsg mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
564fb4d8502Sjsg mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
565fb4d8502Sjsg mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
566fb4d8502Sjsg mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
567fb4d8502Sjsg mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
568fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
569fb4d8502Sjsg };
570fb4d8502Sjsg
571fb4d8502Sjsg static const u32 cz_golden_settings_a11[] =
572fb4d8502Sjsg {
573fb4d8502Sjsg mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
574fb4d8502Sjsg mmDB_DEBUG2, 0xf00fffff, 0x00000400,
575fb4d8502Sjsg mmGB_GPU_ID, 0x0000000f, 0x00000000,
576fb4d8502Sjsg mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
577fb4d8502Sjsg mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
578fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
579fb4d8502Sjsg mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
580fb4d8502Sjsg mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
581fb4d8502Sjsg mmTCC_CTRL, 0x00100000, 0xf31fff7f,
582fb4d8502Sjsg mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
583fb4d8502Sjsg mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
584fb4d8502Sjsg mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
585fb4d8502Sjsg };
586fb4d8502Sjsg
587fb4d8502Sjsg static const u32 cz_golden_common_all[] =
588fb4d8502Sjsg {
589fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
590fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
591fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
592fb4d8502Sjsg mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
593fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
594fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
595fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
596fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
597fb4d8502Sjsg };
598fb4d8502Sjsg
599fb4d8502Sjsg static const u32 cz_mgcg_cgcg_init[] =
600fb4d8502Sjsg {
601fb4d8502Sjsg mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
602fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
603fb4d8502Sjsg mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
604fb4d8502Sjsg mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
605fb4d8502Sjsg mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
606fb4d8502Sjsg mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
607fb4d8502Sjsg mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
608fb4d8502Sjsg mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
609fb4d8502Sjsg mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
610fb4d8502Sjsg mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
611fb4d8502Sjsg mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
612fb4d8502Sjsg mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
613fb4d8502Sjsg mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
614fb4d8502Sjsg mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
615fb4d8502Sjsg mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
616fb4d8502Sjsg mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
617fb4d8502Sjsg mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
618fb4d8502Sjsg mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
619fb4d8502Sjsg mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
620fb4d8502Sjsg mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
621fb4d8502Sjsg mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
622fb4d8502Sjsg mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
623fb4d8502Sjsg mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
624fb4d8502Sjsg mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
625fb4d8502Sjsg mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
626fb4d8502Sjsg mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
627fb4d8502Sjsg mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
628fb4d8502Sjsg mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629fb4d8502Sjsg mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
630fb4d8502Sjsg mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
631fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
632fb4d8502Sjsg mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633fb4d8502Sjsg mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634fb4d8502Sjsg mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
635fb4d8502Sjsg mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636fb4d8502Sjsg mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637fb4d8502Sjsg mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638fb4d8502Sjsg mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639fb4d8502Sjsg mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
640fb4d8502Sjsg mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641fb4d8502Sjsg mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642fb4d8502Sjsg mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643fb4d8502Sjsg mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644fb4d8502Sjsg mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
645fb4d8502Sjsg mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646fb4d8502Sjsg mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647fb4d8502Sjsg mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648fb4d8502Sjsg mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649fb4d8502Sjsg mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
650fb4d8502Sjsg mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651fb4d8502Sjsg mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652fb4d8502Sjsg mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653fb4d8502Sjsg mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654fb4d8502Sjsg mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
655fb4d8502Sjsg mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656fb4d8502Sjsg mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657fb4d8502Sjsg mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658fb4d8502Sjsg mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659fb4d8502Sjsg mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
660fb4d8502Sjsg mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661fb4d8502Sjsg mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662fb4d8502Sjsg mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663fb4d8502Sjsg mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664fb4d8502Sjsg mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
665fb4d8502Sjsg mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666fb4d8502Sjsg mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667fb4d8502Sjsg mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
668fb4d8502Sjsg mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
669fb4d8502Sjsg mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
670fb4d8502Sjsg mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
671fb4d8502Sjsg mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
672fb4d8502Sjsg mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
673fb4d8502Sjsg mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
674fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
675fb4d8502Sjsg mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
676fb4d8502Sjsg };
677fb4d8502Sjsg
678fb4d8502Sjsg static const u32 stoney_golden_settings_a11[] =
679fb4d8502Sjsg {
680fb4d8502Sjsg mmDB_DEBUG2, 0xf00fffff, 0x00000400,
681fb4d8502Sjsg mmGB_GPU_ID, 0x0000000f, 0x00000000,
682fb4d8502Sjsg mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
683fb4d8502Sjsg mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
684fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
685fb4d8502Sjsg mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
686fb4d8502Sjsg mmTCC_CTRL, 0x00100000, 0xf31fff7f,
687fb4d8502Sjsg mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
688fb4d8502Sjsg mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
689fb4d8502Sjsg mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
690fb4d8502Sjsg };
691fb4d8502Sjsg
692fb4d8502Sjsg static const u32 stoney_golden_common_all[] =
693fb4d8502Sjsg {
694fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
695fb4d8502Sjsg mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
696fb4d8502Sjsg mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
697fb4d8502Sjsg mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
698fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
699fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
700fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
701fb4d8502Sjsg mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
702fb4d8502Sjsg };
703fb4d8502Sjsg
704fb4d8502Sjsg static const u32 stoney_mgcg_cgcg_init[] =
705fb4d8502Sjsg {
706fb4d8502Sjsg mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
707fb4d8502Sjsg mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
708fb4d8502Sjsg mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709fb4d8502Sjsg mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
710fb4d8502Sjsg mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
711fb4d8502Sjsg };
712fb4d8502Sjsg
713fb4d8502Sjsg
714fb4d8502Sjsg static const char * const sq_edc_source_names[] = {
715fb4d8502Sjsg "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
716fb4d8502Sjsg "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
717fb4d8502Sjsg "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
718fb4d8502Sjsg "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
719fb4d8502Sjsg "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
720fb4d8502Sjsg "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
721fb4d8502Sjsg "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
722fb4d8502Sjsg };
723fb4d8502Sjsg
724fb4d8502Sjsg static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
725fb4d8502Sjsg static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
726fb4d8502Sjsg static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
727fb4d8502Sjsg static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
728fb4d8502Sjsg static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
729fb4d8502Sjsg static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
730fb4d8502Sjsg static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
731fb4d8502Sjsg static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
732fb4d8502Sjsg
7335ca02815Sjsg #define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x0000007fL
7345ca02815Sjsg #define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x00000000L
7355ca02815Sjsg
gfx_v8_0_init_golden_registers(struct amdgpu_device * adev)736fb4d8502Sjsg static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
737fb4d8502Sjsg {
7385ca02815Sjsg uint32_t data;
7395ca02815Sjsg
740fb4d8502Sjsg switch (adev->asic_type) {
741fb4d8502Sjsg case CHIP_TOPAZ:
742fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
743fb4d8502Sjsg iceland_mgcg_cgcg_init,
744fb4d8502Sjsg ARRAY_SIZE(iceland_mgcg_cgcg_init));
745fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
746fb4d8502Sjsg golden_settings_iceland_a11,
747fb4d8502Sjsg ARRAY_SIZE(golden_settings_iceland_a11));
748fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
749fb4d8502Sjsg iceland_golden_common_all,
750fb4d8502Sjsg ARRAY_SIZE(iceland_golden_common_all));
751fb4d8502Sjsg break;
752fb4d8502Sjsg case CHIP_FIJI:
753fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
754fb4d8502Sjsg fiji_mgcg_cgcg_init,
755fb4d8502Sjsg ARRAY_SIZE(fiji_mgcg_cgcg_init));
756fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
757fb4d8502Sjsg golden_settings_fiji_a10,
758fb4d8502Sjsg ARRAY_SIZE(golden_settings_fiji_a10));
759fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
760fb4d8502Sjsg fiji_golden_common_all,
761fb4d8502Sjsg ARRAY_SIZE(fiji_golden_common_all));
762fb4d8502Sjsg break;
763fb4d8502Sjsg
764fb4d8502Sjsg case CHIP_TONGA:
765fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
766fb4d8502Sjsg tonga_mgcg_cgcg_init,
767fb4d8502Sjsg ARRAY_SIZE(tonga_mgcg_cgcg_init));
768fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
769fb4d8502Sjsg golden_settings_tonga_a11,
770fb4d8502Sjsg ARRAY_SIZE(golden_settings_tonga_a11));
771fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
772fb4d8502Sjsg tonga_golden_common_all,
773fb4d8502Sjsg ARRAY_SIZE(tonga_golden_common_all));
774fb4d8502Sjsg break;
775fb4d8502Sjsg case CHIP_VEGAM:
776fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
777fb4d8502Sjsg golden_settings_vegam_a11,
778fb4d8502Sjsg ARRAY_SIZE(golden_settings_vegam_a11));
779fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
780fb4d8502Sjsg vegam_golden_common_all,
781fb4d8502Sjsg ARRAY_SIZE(vegam_golden_common_all));
782fb4d8502Sjsg break;
783fb4d8502Sjsg case CHIP_POLARIS11:
784fb4d8502Sjsg case CHIP_POLARIS12:
785fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
786fb4d8502Sjsg golden_settings_polaris11_a11,
787fb4d8502Sjsg ARRAY_SIZE(golden_settings_polaris11_a11));
788fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
789fb4d8502Sjsg polaris11_golden_common_all,
790fb4d8502Sjsg ARRAY_SIZE(polaris11_golden_common_all));
791fb4d8502Sjsg break;
792fb4d8502Sjsg case CHIP_POLARIS10:
793fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
794fb4d8502Sjsg golden_settings_polaris10_a11,
795fb4d8502Sjsg ARRAY_SIZE(golden_settings_polaris10_a11));
796fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
797fb4d8502Sjsg polaris10_golden_common_all,
798fb4d8502Sjsg ARRAY_SIZE(polaris10_golden_common_all));
7995ca02815Sjsg data = RREG32_SMC(ixCG_ACLK_CNTL);
8005ca02815Sjsg data &= ~CG_ACLK_CNTL__ACLK_DIVIDER_MASK;
8015ca02815Sjsg data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;
8025ca02815Sjsg WREG32_SMC(ixCG_ACLK_CNTL, data);
8035ca02815Sjsg if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&
804fb4d8502Sjsg ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
805fb4d8502Sjsg (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
8065ca02815Sjsg (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {
807fb4d8502Sjsg amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
808fb4d8502Sjsg amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
809fb4d8502Sjsg }
810fb4d8502Sjsg break;
811fb4d8502Sjsg case CHIP_CARRIZO:
812fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
813fb4d8502Sjsg cz_mgcg_cgcg_init,
814fb4d8502Sjsg ARRAY_SIZE(cz_mgcg_cgcg_init));
815fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
816fb4d8502Sjsg cz_golden_settings_a11,
817fb4d8502Sjsg ARRAY_SIZE(cz_golden_settings_a11));
818fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
819fb4d8502Sjsg cz_golden_common_all,
820fb4d8502Sjsg ARRAY_SIZE(cz_golden_common_all));
821fb4d8502Sjsg break;
822fb4d8502Sjsg case CHIP_STONEY:
823fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
824fb4d8502Sjsg stoney_mgcg_cgcg_init,
825fb4d8502Sjsg ARRAY_SIZE(stoney_mgcg_cgcg_init));
826fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
827fb4d8502Sjsg stoney_golden_settings_a11,
828fb4d8502Sjsg ARRAY_SIZE(stoney_golden_settings_a11));
829fb4d8502Sjsg amdgpu_device_program_register_sequence(adev,
830fb4d8502Sjsg stoney_golden_common_all,
831fb4d8502Sjsg ARRAY_SIZE(stoney_golden_common_all));
832fb4d8502Sjsg break;
833fb4d8502Sjsg default:
834fb4d8502Sjsg break;
835fb4d8502Sjsg }
836fb4d8502Sjsg }
837fb4d8502Sjsg
gfx_v8_0_ring_test_ring(struct amdgpu_ring * ring)838fb4d8502Sjsg static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
839fb4d8502Sjsg {
840fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
841fb4d8502Sjsg uint32_t tmp = 0;
842fb4d8502Sjsg unsigned i;
843fb4d8502Sjsg int r;
844fb4d8502Sjsg
8451bb76ff1Sjsg WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
8461bb76ff1Sjsg r = amdgpu_ring_alloc(ring, 3);
847c349dbc7Sjsg if (r)
848fb4d8502Sjsg return r;
849c349dbc7Sjsg
850fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
8511bb76ff1Sjsg amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
852fb4d8502Sjsg amdgpu_ring_write(ring, 0xDEADBEEF);
853fb4d8502Sjsg amdgpu_ring_commit(ring);
854fb4d8502Sjsg
855fb4d8502Sjsg for (i = 0; i < adev->usec_timeout; i++) {
8561bb76ff1Sjsg tmp = RREG32(mmSCRATCH_REG0);
857fb4d8502Sjsg if (tmp == 0xDEADBEEF)
858fb4d8502Sjsg break;
859c349dbc7Sjsg udelay(1);
860fb4d8502Sjsg }
861c349dbc7Sjsg
862c349dbc7Sjsg if (i >= adev->usec_timeout)
863c349dbc7Sjsg r = -ETIMEDOUT;
864c349dbc7Sjsg
865fb4d8502Sjsg return r;
866fb4d8502Sjsg }
867fb4d8502Sjsg
gfx_v8_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)868fb4d8502Sjsg static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
869fb4d8502Sjsg {
870fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
871fb4d8502Sjsg struct amdgpu_ib ib;
872fb4d8502Sjsg struct dma_fence *f = NULL;
873fb4d8502Sjsg
874fb4d8502Sjsg unsigned int index;
875fb4d8502Sjsg uint64_t gpu_addr;
876fb4d8502Sjsg uint32_t tmp;
877fb4d8502Sjsg long r;
878fb4d8502Sjsg
879fb4d8502Sjsg r = amdgpu_device_wb_get(adev, &index);
880c349dbc7Sjsg if (r)
881fb4d8502Sjsg return r;
882fb4d8502Sjsg
883fb4d8502Sjsg gpu_addr = adev->wb.gpu_addr + (index * 4);
884fb4d8502Sjsg adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
885fb4d8502Sjsg memset(&ib, 0, sizeof(ib));
8867cb3d583Sjsg
8877cb3d583Sjsg r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
888c349dbc7Sjsg if (r)
889fb4d8502Sjsg goto err1;
890c349dbc7Sjsg
891fb4d8502Sjsg ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
892fb4d8502Sjsg ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
893fb4d8502Sjsg ib.ptr[2] = lower_32_bits(gpu_addr);
894fb4d8502Sjsg ib.ptr[3] = upper_32_bits(gpu_addr);
895fb4d8502Sjsg ib.ptr[4] = 0xDEADBEEF;
896fb4d8502Sjsg ib.length_dw = 5;
897fb4d8502Sjsg
898fb4d8502Sjsg r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
899fb4d8502Sjsg if (r)
900fb4d8502Sjsg goto err2;
901fb4d8502Sjsg
902fb4d8502Sjsg r = dma_fence_wait_timeout(f, false, timeout);
903fb4d8502Sjsg if (r == 0) {
904fb4d8502Sjsg r = -ETIMEDOUT;
905fb4d8502Sjsg goto err2;
906fb4d8502Sjsg } else if (r < 0) {
907fb4d8502Sjsg goto err2;
908fb4d8502Sjsg }
909fb4d8502Sjsg
910fb4d8502Sjsg tmp = adev->wb.wb[index];
911c349dbc7Sjsg if (tmp == 0xDEADBEEF)
912fb4d8502Sjsg r = 0;
913c349dbc7Sjsg else
914fb4d8502Sjsg r = -EINVAL;
915fb4d8502Sjsg
916fb4d8502Sjsg err2:
917fb4d8502Sjsg amdgpu_ib_free(adev, &ib, NULL);
918fb4d8502Sjsg dma_fence_put(f);
919fb4d8502Sjsg err1:
920fb4d8502Sjsg amdgpu_device_wb_free(adev, index);
921fb4d8502Sjsg return r;
922fb4d8502Sjsg }
923fb4d8502Sjsg
924fb4d8502Sjsg
gfx_v8_0_free_microcode(struct amdgpu_device * adev)925fb4d8502Sjsg static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
926fb4d8502Sjsg {
927*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.pfp_fw);
928*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.me_fw);
929*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.ce_fw);
930*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.rlc_fw);
931*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.mec_fw);
932fb4d8502Sjsg if ((adev->asic_type != CHIP_STONEY) &&
933fb4d8502Sjsg (adev->asic_type != CHIP_TOPAZ))
934*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.mec2_fw);
935fb4d8502Sjsg
936fb4d8502Sjsg kfree(adev->gfx.rlc.register_list_format);
937fb4d8502Sjsg }
938fb4d8502Sjsg
gfx_v8_0_init_microcode(struct amdgpu_device * adev)939fb4d8502Sjsg static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
940fb4d8502Sjsg {
941fb4d8502Sjsg const char *chip_name;
942fb4d8502Sjsg char fw_name[30];
943fb4d8502Sjsg int err;
944fb4d8502Sjsg struct amdgpu_firmware_info *info = NULL;
945fb4d8502Sjsg const struct common_firmware_header *header = NULL;
946fb4d8502Sjsg const struct gfx_firmware_header_v1_0 *cp_hdr;
947fb4d8502Sjsg const struct rlc_firmware_header_v2_0 *rlc_hdr;
948fb4d8502Sjsg unsigned int *tmp = NULL, i;
949fb4d8502Sjsg
950fb4d8502Sjsg DRM_DEBUG("\n");
951fb4d8502Sjsg
952fb4d8502Sjsg switch (adev->asic_type) {
953fb4d8502Sjsg case CHIP_TOPAZ:
954fb4d8502Sjsg chip_name = "topaz";
955fb4d8502Sjsg break;
956fb4d8502Sjsg case CHIP_TONGA:
957fb4d8502Sjsg chip_name = "tonga";
958fb4d8502Sjsg break;
959fb4d8502Sjsg case CHIP_CARRIZO:
960fb4d8502Sjsg chip_name = "carrizo";
961fb4d8502Sjsg break;
962fb4d8502Sjsg case CHIP_FIJI:
963fb4d8502Sjsg chip_name = "fiji";
964fb4d8502Sjsg break;
965fb4d8502Sjsg case CHIP_STONEY:
966fb4d8502Sjsg chip_name = "stoney";
967fb4d8502Sjsg break;
968fb4d8502Sjsg case CHIP_POLARIS10:
969fb4d8502Sjsg chip_name = "polaris10";
970fb4d8502Sjsg break;
971fb4d8502Sjsg case CHIP_POLARIS11:
972fb4d8502Sjsg chip_name = "polaris11";
973fb4d8502Sjsg break;
974fb4d8502Sjsg case CHIP_POLARIS12:
975fb4d8502Sjsg chip_name = "polaris12";
976fb4d8502Sjsg break;
977fb4d8502Sjsg case CHIP_VEGAM:
978fb4d8502Sjsg chip_name = "vegam";
979fb4d8502Sjsg break;
980fb4d8502Sjsg default:
981fb4d8502Sjsg BUG();
982fb4d8502Sjsg }
983fb4d8502Sjsg
984fb4d8502Sjsg if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
985fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
986*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
987*f005ef32Sjsg if (err == -ENODEV) {
988fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
989*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
990fb4d8502Sjsg }
991fb4d8502Sjsg } else {
992fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
993*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
994fb4d8502Sjsg }
995fb4d8502Sjsg if (err)
996fb4d8502Sjsg goto out;
997fb4d8502Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
998fb4d8502Sjsg adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
999fb4d8502Sjsg adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1000fb4d8502Sjsg
1001fb4d8502Sjsg if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1002fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1003*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
1004*f005ef32Sjsg if (err == -ENODEV) {
1005fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1006*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
1007fb4d8502Sjsg }
1008fb4d8502Sjsg } else {
1009fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1010*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
1011fb4d8502Sjsg }
1012fb4d8502Sjsg if (err)
1013fb4d8502Sjsg goto out;
1014fb4d8502Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1015fb4d8502Sjsg adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1016fb4d8502Sjsg
1017fb4d8502Sjsg adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1018fb4d8502Sjsg
1019fb4d8502Sjsg if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1020fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1021*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
1022*f005ef32Sjsg if (err == -ENODEV) {
1023fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1024*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
1025fb4d8502Sjsg }
1026fb4d8502Sjsg } else {
1027fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1028*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
1029fb4d8502Sjsg }
1030fb4d8502Sjsg if (err)
1031fb4d8502Sjsg goto out;
1032fb4d8502Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1033fb4d8502Sjsg adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1034fb4d8502Sjsg adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1035fb4d8502Sjsg
1036fb4d8502Sjsg /*
1037fb4d8502Sjsg * Support for MCBP/Virtualization in combination with chained IBs is
1038fb4d8502Sjsg * formal released on feature version #46
1039fb4d8502Sjsg */
1040fb4d8502Sjsg if (adev->gfx.ce_feature_version >= 46 &&
1041fb4d8502Sjsg adev->gfx.pfp_feature_version >= 46) {
1042fb4d8502Sjsg adev->virt.chained_ib_support = true;
1043fb4d8502Sjsg DRM_INFO("Chained IB support enabled!\n");
1044fb4d8502Sjsg } else
1045fb4d8502Sjsg adev->virt.chained_ib_support = false;
1046fb4d8502Sjsg
1047fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1048*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
1049fb4d8502Sjsg if (err)
1050fb4d8502Sjsg goto out;
1051fb4d8502Sjsg rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1052fb4d8502Sjsg adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1053fb4d8502Sjsg adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1054fb4d8502Sjsg
1055fb4d8502Sjsg adev->gfx.rlc.save_and_restore_offset =
1056fb4d8502Sjsg le32_to_cpu(rlc_hdr->save_and_restore_offset);
1057fb4d8502Sjsg adev->gfx.rlc.clear_state_descriptor_offset =
1058fb4d8502Sjsg le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1059fb4d8502Sjsg adev->gfx.rlc.avail_scratch_ram_locations =
1060fb4d8502Sjsg le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1061fb4d8502Sjsg adev->gfx.rlc.reg_restore_list_size =
1062fb4d8502Sjsg le32_to_cpu(rlc_hdr->reg_restore_list_size);
1063fb4d8502Sjsg adev->gfx.rlc.reg_list_format_start =
1064fb4d8502Sjsg le32_to_cpu(rlc_hdr->reg_list_format_start);
1065fb4d8502Sjsg adev->gfx.rlc.reg_list_format_separate_start =
1066fb4d8502Sjsg le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1067fb4d8502Sjsg adev->gfx.rlc.starting_offsets_start =
1068fb4d8502Sjsg le32_to_cpu(rlc_hdr->starting_offsets_start);
1069fb4d8502Sjsg adev->gfx.rlc.reg_list_format_size_bytes =
1070fb4d8502Sjsg le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1071fb4d8502Sjsg adev->gfx.rlc.reg_list_size_bytes =
1072fb4d8502Sjsg le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1073fb4d8502Sjsg
1074fb4d8502Sjsg adev->gfx.rlc.register_list_format =
1075fb4d8502Sjsg kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1076fb4d8502Sjsg adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1077fb4d8502Sjsg
1078fb4d8502Sjsg if (!adev->gfx.rlc.register_list_format) {
1079fb4d8502Sjsg err = -ENOMEM;
1080fb4d8502Sjsg goto out;
1081fb4d8502Sjsg }
1082fb4d8502Sjsg
1083fb4d8502Sjsg tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1084fb4d8502Sjsg le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1085c349dbc7Sjsg for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1086fb4d8502Sjsg adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1087fb4d8502Sjsg
1088fb4d8502Sjsg adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1089fb4d8502Sjsg
1090fb4d8502Sjsg tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1091fb4d8502Sjsg le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1092c349dbc7Sjsg for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1093fb4d8502Sjsg adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1094fb4d8502Sjsg
1095fb4d8502Sjsg if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1096fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1097*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
1098*f005ef32Sjsg if (err == -ENODEV) {
1099fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1100*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
1101fb4d8502Sjsg }
1102fb4d8502Sjsg } else {
1103fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1104*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
1105fb4d8502Sjsg }
1106fb4d8502Sjsg if (err)
1107fb4d8502Sjsg goto out;
1108fb4d8502Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1109fb4d8502Sjsg adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1110fb4d8502Sjsg adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1111fb4d8502Sjsg
1112fb4d8502Sjsg if ((adev->asic_type != CHIP_STONEY) &&
1113fb4d8502Sjsg (adev->asic_type != CHIP_TOPAZ)) {
1114fb4d8502Sjsg if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1115fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1116*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
1117*f005ef32Sjsg if (err == -ENODEV) {
1118fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1119*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
1120fb4d8502Sjsg }
1121fb4d8502Sjsg } else {
1122fb4d8502Sjsg snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1123*f005ef32Sjsg err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
1124fb4d8502Sjsg }
1125fb4d8502Sjsg if (!err) {
1126fb4d8502Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1127fb4d8502Sjsg adev->gfx.mec2_fw->data;
1128fb4d8502Sjsg adev->gfx.mec2_fw_version =
1129fb4d8502Sjsg le32_to_cpu(cp_hdr->header.ucode_version);
1130fb4d8502Sjsg adev->gfx.mec2_feature_version =
1131fb4d8502Sjsg le32_to_cpu(cp_hdr->ucode_feature_version);
1132fb4d8502Sjsg } else {
1133fb4d8502Sjsg err = 0;
1134fb4d8502Sjsg adev->gfx.mec2_fw = NULL;
1135fb4d8502Sjsg }
1136fb4d8502Sjsg }
1137fb4d8502Sjsg
1138fb4d8502Sjsg info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1139fb4d8502Sjsg info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1140fb4d8502Sjsg info->fw = adev->gfx.pfp_fw;
1141fb4d8502Sjsg header = (const struct common_firmware_header *)info->fw->data;
1142fb4d8502Sjsg adev->firmware.fw_size +=
1143*f005ef32Sjsg ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1144fb4d8502Sjsg
1145fb4d8502Sjsg info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1146fb4d8502Sjsg info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1147fb4d8502Sjsg info->fw = adev->gfx.me_fw;
1148fb4d8502Sjsg header = (const struct common_firmware_header *)info->fw->data;
1149fb4d8502Sjsg adev->firmware.fw_size +=
1150*f005ef32Sjsg ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1151fb4d8502Sjsg
1152fb4d8502Sjsg info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1153fb4d8502Sjsg info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1154fb4d8502Sjsg info->fw = adev->gfx.ce_fw;
1155fb4d8502Sjsg header = (const struct common_firmware_header *)info->fw->data;
1156fb4d8502Sjsg adev->firmware.fw_size +=
1157*f005ef32Sjsg ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1158fb4d8502Sjsg
1159fb4d8502Sjsg info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1160fb4d8502Sjsg info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1161fb4d8502Sjsg info->fw = adev->gfx.rlc_fw;
1162fb4d8502Sjsg header = (const struct common_firmware_header *)info->fw->data;
1163fb4d8502Sjsg adev->firmware.fw_size +=
1164*f005ef32Sjsg ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1165fb4d8502Sjsg
1166fb4d8502Sjsg info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1167fb4d8502Sjsg info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1168fb4d8502Sjsg info->fw = adev->gfx.mec_fw;
1169fb4d8502Sjsg header = (const struct common_firmware_header *)info->fw->data;
1170fb4d8502Sjsg adev->firmware.fw_size +=
1171*f005ef32Sjsg ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1172fb4d8502Sjsg
1173fb4d8502Sjsg /* we need account JT in */
1174fb4d8502Sjsg cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1175fb4d8502Sjsg adev->firmware.fw_size +=
1176*f005ef32Sjsg ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1177fb4d8502Sjsg
1178fb4d8502Sjsg if (amdgpu_sriov_vf(adev)) {
1179fb4d8502Sjsg info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1180fb4d8502Sjsg info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1181fb4d8502Sjsg info->fw = adev->gfx.mec_fw;
1182fb4d8502Sjsg adev->firmware.fw_size +=
1183*f005ef32Sjsg ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1184fb4d8502Sjsg }
1185fb4d8502Sjsg
1186fb4d8502Sjsg if (adev->gfx.mec2_fw) {
1187fb4d8502Sjsg info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1188fb4d8502Sjsg info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1189fb4d8502Sjsg info->fw = adev->gfx.mec2_fw;
1190fb4d8502Sjsg header = (const struct common_firmware_header *)info->fw->data;
1191fb4d8502Sjsg adev->firmware.fw_size +=
1192*f005ef32Sjsg ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1193fb4d8502Sjsg }
1194fb4d8502Sjsg
1195fb4d8502Sjsg out:
1196fb4d8502Sjsg if (err) {
1197fb4d8502Sjsg dev_err(adev->dev,
1198fb4d8502Sjsg "gfx8: Failed to load firmware \"%s\"\n",
1199fb4d8502Sjsg fw_name);
1200*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.pfp_fw);
1201*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.me_fw);
1202*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.ce_fw);
1203*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.rlc_fw);
1204*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.mec_fw);
1205*f005ef32Sjsg amdgpu_ucode_release(&adev->gfx.mec2_fw);
1206fb4d8502Sjsg }
1207fb4d8502Sjsg return err;
1208fb4d8502Sjsg }
1209fb4d8502Sjsg
gfx_v8_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)1210fb4d8502Sjsg static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1211fb4d8502Sjsg volatile u32 *buffer)
1212fb4d8502Sjsg {
1213fb4d8502Sjsg u32 count = 0, i;
1214fb4d8502Sjsg const struct cs_section_def *sect = NULL;
1215fb4d8502Sjsg const struct cs_extent_def *ext = NULL;
1216fb4d8502Sjsg
1217fb4d8502Sjsg if (adev->gfx.rlc.cs_data == NULL)
1218fb4d8502Sjsg return;
1219fb4d8502Sjsg if (buffer == NULL)
1220fb4d8502Sjsg return;
1221fb4d8502Sjsg
1222fb4d8502Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1223fb4d8502Sjsg buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1224fb4d8502Sjsg
1225fb4d8502Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1226fb4d8502Sjsg buffer[count++] = cpu_to_le32(0x80000000);
1227fb4d8502Sjsg buffer[count++] = cpu_to_le32(0x80000000);
1228fb4d8502Sjsg
1229fb4d8502Sjsg for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1230fb4d8502Sjsg for (ext = sect->section; ext->extent != NULL; ++ext) {
1231fb4d8502Sjsg if (sect->id == SECT_CONTEXT) {
1232fb4d8502Sjsg buffer[count++] =
1233fb4d8502Sjsg cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1234fb4d8502Sjsg buffer[count++] = cpu_to_le32(ext->reg_index -
1235fb4d8502Sjsg PACKET3_SET_CONTEXT_REG_START);
1236fb4d8502Sjsg for (i = 0; i < ext->reg_count; i++)
1237fb4d8502Sjsg buffer[count++] = cpu_to_le32(ext->extent[i]);
1238fb4d8502Sjsg } else {
1239fb4d8502Sjsg return;
1240fb4d8502Sjsg }
1241fb4d8502Sjsg }
1242fb4d8502Sjsg }
1243fb4d8502Sjsg
1244fb4d8502Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1245fb4d8502Sjsg buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1246fb4d8502Sjsg PACKET3_SET_CONTEXT_REG_START);
1247fb4d8502Sjsg buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1248fb4d8502Sjsg buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1249fb4d8502Sjsg
1250fb4d8502Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1251fb4d8502Sjsg buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1252fb4d8502Sjsg
1253fb4d8502Sjsg buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1254fb4d8502Sjsg buffer[count++] = cpu_to_le32(0);
1255fb4d8502Sjsg }
1256fb4d8502Sjsg
gfx_v8_0_cp_jump_table_num(struct amdgpu_device * adev)1257c349dbc7Sjsg static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1258fb4d8502Sjsg {
1259fb4d8502Sjsg if (adev->asic_type == CHIP_CARRIZO)
1260c349dbc7Sjsg return 5;
1261c349dbc7Sjsg else
1262c349dbc7Sjsg return 4;
1263fb4d8502Sjsg }
1264fb4d8502Sjsg
gfx_v8_0_rlc_init(struct amdgpu_device * adev)1265fb4d8502Sjsg static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1266fb4d8502Sjsg {
1267fb4d8502Sjsg const struct cs_section_def *cs_data;
1268fb4d8502Sjsg int r;
1269fb4d8502Sjsg
1270fb4d8502Sjsg adev->gfx.rlc.cs_data = vi_cs_data;
1271fb4d8502Sjsg
1272fb4d8502Sjsg cs_data = adev->gfx.rlc.cs_data;
1273fb4d8502Sjsg
1274fb4d8502Sjsg if (cs_data) {
1275c349dbc7Sjsg /* init clear state block */
1276c349dbc7Sjsg r = amdgpu_gfx_rlc_init_csb(adev);
1277c349dbc7Sjsg if (r)
1278fb4d8502Sjsg return r;
1279fb4d8502Sjsg }
1280fb4d8502Sjsg
1281fb4d8502Sjsg if ((adev->asic_type == CHIP_CARRIZO) ||
1282fb4d8502Sjsg (adev->asic_type == CHIP_STONEY)) {
1283*f005ef32Sjsg adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1284c349dbc7Sjsg r = amdgpu_gfx_rlc_init_cpt(adev);
1285c349dbc7Sjsg if (r)
1286fb4d8502Sjsg return r;
1287fb4d8502Sjsg }
1288fb4d8502Sjsg
1289c349dbc7Sjsg /* init spm vmid with 0xf */
1290c349dbc7Sjsg if (adev->gfx.rlc.funcs->update_spm_vmid)
1291c349dbc7Sjsg adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1292fb4d8502Sjsg
1293fb4d8502Sjsg return 0;
1294fb4d8502Sjsg }
1295fb4d8502Sjsg
gfx_v8_0_mec_fini(struct amdgpu_device * adev)1296fb4d8502Sjsg static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1297fb4d8502Sjsg {
1298fb4d8502Sjsg amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1299fb4d8502Sjsg }
1300fb4d8502Sjsg
gfx_v8_0_mec_init(struct amdgpu_device * adev)1301fb4d8502Sjsg static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1302fb4d8502Sjsg {
1303fb4d8502Sjsg int r;
1304fb4d8502Sjsg u32 *hpd;
1305fb4d8502Sjsg size_t mec_hpd_size;
1306fb4d8502Sjsg
1307*f005ef32Sjsg bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1308fb4d8502Sjsg
1309fb4d8502Sjsg /* take ownership of the relevant compute queues */
1310fb4d8502Sjsg amdgpu_gfx_compute_queue_acquire(adev);
1311fb4d8502Sjsg
1312fb4d8502Sjsg mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1313ad8b1aafSjsg if (mec_hpd_size) {
1314fb4d8502Sjsg r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1315*f005ef32Sjsg AMDGPU_GEM_DOMAIN_VRAM |
1316*f005ef32Sjsg AMDGPU_GEM_DOMAIN_GTT,
1317fb4d8502Sjsg &adev->gfx.mec.hpd_eop_obj,
1318fb4d8502Sjsg &adev->gfx.mec.hpd_eop_gpu_addr,
1319fb4d8502Sjsg (void **)&hpd);
1320fb4d8502Sjsg if (r) {
1321fb4d8502Sjsg dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1322fb4d8502Sjsg return r;
1323fb4d8502Sjsg }
1324fb4d8502Sjsg
1325fb4d8502Sjsg memset(hpd, 0, mec_hpd_size);
1326fb4d8502Sjsg
1327fb4d8502Sjsg amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1328fb4d8502Sjsg amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1329ad8b1aafSjsg }
1330fb4d8502Sjsg
1331fb4d8502Sjsg return 0;
1332fb4d8502Sjsg }
1333fb4d8502Sjsg
1334fb4d8502Sjsg static const u32 vgpr_init_compute_shader[] =
1335fb4d8502Sjsg {
1336fb4d8502Sjsg 0x7e000209, 0x7e020208,
1337fb4d8502Sjsg 0x7e040207, 0x7e060206,
1338fb4d8502Sjsg 0x7e080205, 0x7e0a0204,
1339fb4d8502Sjsg 0x7e0c0203, 0x7e0e0202,
1340fb4d8502Sjsg 0x7e100201, 0x7e120200,
1341fb4d8502Sjsg 0x7e140209, 0x7e160208,
1342fb4d8502Sjsg 0x7e180207, 0x7e1a0206,
1343fb4d8502Sjsg 0x7e1c0205, 0x7e1e0204,
1344fb4d8502Sjsg 0x7e200203, 0x7e220202,
1345fb4d8502Sjsg 0x7e240201, 0x7e260200,
1346fb4d8502Sjsg 0x7e280209, 0x7e2a0208,
1347fb4d8502Sjsg 0x7e2c0207, 0x7e2e0206,
1348fb4d8502Sjsg 0x7e300205, 0x7e320204,
1349fb4d8502Sjsg 0x7e340203, 0x7e360202,
1350fb4d8502Sjsg 0x7e380201, 0x7e3a0200,
1351fb4d8502Sjsg 0x7e3c0209, 0x7e3e0208,
1352fb4d8502Sjsg 0x7e400207, 0x7e420206,
1353fb4d8502Sjsg 0x7e440205, 0x7e460204,
1354fb4d8502Sjsg 0x7e480203, 0x7e4a0202,
1355fb4d8502Sjsg 0x7e4c0201, 0x7e4e0200,
1356fb4d8502Sjsg 0x7e500209, 0x7e520208,
1357fb4d8502Sjsg 0x7e540207, 0x7e560206,
1358fb4d8502Sjsg 0x7e580205, 0x7e5a0204,
1359fb4d8502Sjsg 0x7e5c0203, 0x7e5e0202,
1360fb4d8502Sjsg 0x7e600201, 0x7e620200,
1361fb4d8502Sjsg 0x7e640209, 0x7e660208,
1362fb4d8502Sjsg 0x7e680207, 0x7e6a0206,
1363fb4d8502Sjsg 0x7e6c0205, 0x7e6e0204,
1364fb4d8502Sjsg 0x7e700203, 0x7e720202,
1365fb4d8502Sjsg 0x7e740201, 0x7e760200,
1366fb4d8502Sjsg 0x7e780209, 0x7e7a0208,
1367fb4d8502Sjsg 0x7e7c0207, 0x7e7e0206,
1368fb4d8502Sjsg 0xbf8a0000, 0xbf810000,
1369fb4d8502Sjsg };
1370fb4d8502Sjsg
1371fb4d8502Sjsg static const u32 sgpr_init_compute_shader[] =
1372fb4d8502Sjsg {
1373fb4d8502Sjsg 0xbe8a0100, 0xbe8c0102,
1374fb4d8502Sjsg 0xbe8e0104, 0xbe900106,
1375fb4d8502Sjsg 0xbe920108, 0xbe940100,
1376fb4d8502Sjsg 0xbe960102, 0xbe980104,
1377fb4d8502Sjsg 0xbe9a0106, 0xbe9c0108,
1378fb4d8502Sjsg 0xbe9e0100, 0xbea00102,
1379fb4d8502Sjsg 0xbea20104, 0xbea40106,
1380fb4d8502Sjsg 0xbea60108, 0xbea80100,
1381fb4d8502Sjsg 0xbeaa0102, 0xbeac0104,
1382fb4d8502Sjsg 0xbeae0106, 0xbeb00108,
1383fb4d8502Sjsg 0xbeb20100, 0xbeb40102,
1384fb4d8502Sjsg 0xbeb60104, 0xbeb80106,
1385fb4d8502Sjsg 0xbeba0108, 0xbebc0100,
1386fb4d8502Sjsg 0xbebe0102, 0xbec00104,
1387fb4d8502Sjsg 0xbec20106, 0xbec40108,
1388fb4d8502Sjsg 0xbec60100, 0xbec80102,
1389fb4d8502Sjsg 0xbee60004, 0xbee70005,
1390fb4d8502Sjsg 0xbeea0006, 0xbeeb0007,
1391fb4d8502Sjsg 0xbee80008, 0xbee90009,
1392fb4d8502Sjsg 0xbefc0000, 0xbf8a0000,
1393fb4d8502Sjsg 0xbf810000, 0x00000000,
1394fb4d8502Sjsg };
1395fb4d8502Sjsg
1396fb4d8502Sjsg static const u32 vgpr_init_regs[] =
1397fb4d8502Sjsg {
1398fb4d8502Sjsg mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1399fb4d8502Sjsg mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1400fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_X, 256*4,
1401fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_Y, 1,
1402fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_Z, 1,
1403fb4d8502Sjsg mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1404fb4d8502Sjsg mmCOMPUTE_PGM_RSRC2, 20,
1405fb4d8502Sjsg mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1406fb4d8502Sjsg mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1407fb4d8502Sjsg mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1408fb4d8502Sjsg mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1409fb4d8502Sjsg mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1410fb4d8502Sjsg mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1411fb4d8502Sjsg mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1412fb4d8502Sjsg mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1413fb4d8502Sjsg mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1414fb4d8502Sjsg mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1415fb4d8502Sjsg };
1416fb4d8502Sjsg
1417fb4d8502Sjsg static const u32 sgpr1_init_regs[] =
1418fb4d8502Sjsg {
1419fb4d8502Sjsg mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1420fb4d8502Sjsg mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1421fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_X, 256*5,
1422fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_Y, 1,
1423fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_Z, 1,
1424fb4d8502Sjsg mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1425fb4d8502Sjsg mmCOMPUTE_PGM_RSRC2, 20,
1426fb4d8502Sjsg mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1427fb4d8502Sjsg mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1428fb4d8502Sjsg mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1429fb4d8502Sjsg mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1430fb4d8502Sjsg mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1431fb4d8502Sjsg mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1432fb4d8502Sjsg mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1433fb4d8502Sjsg mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1434fb4d8502Sjsg mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1435fb4d8502Sjsg mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1436fb4d8502Sjsg };
1437fb4d8502Sjsg
1438fb4d8502Sjsg static const u32 sgpr2_init_regs[] =
1439fb4d8502Sjsg {
1440fb4d8502Sjsg mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1441fb4d8502Sjsg mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1442fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_X, 256*5,
1443fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_Y, 1,
1444fb4d8502Sjsg mmCOMPUTE_NUM_THREAD_Z, 1,
1445fb4d8502Sjsg mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1446fb4d8502Sjsg mmCOMPUTE_PGM_RSRC2, 20,
1447fb4d8502Sjsg mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1448fb4d8502Sjsg mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1449fb4d8502Sjsg mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1450fb4d8502Sjsg mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1451fb4d8502Sjsg mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1452fb4d8502Sjsg mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1453fb4d8502Sjsg mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1454fb4d8502Sjsg mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1455fb4d8502Sjsg mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1456fb4d8502Sjsg mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1457fb4d8502Sjsg };
1458fb4d8502Sjsg
1459fb4d8502Sjsg static const u32 sec_ded_counter_registers[] =
1460fb4d8502Sjsg {
1461fb4d8502Sjsg mmCPC_EDC_ATC_CNT,
1462fb4d8502Sjsg mmCPC_EDC_SCRATCH_CNT,
1463fb4d8502Sjsg mmCPC_EDC_UCODE_CNT,
1464fb4d8502Sjsg mmCPF_EDC_ATC_CNT,
1465fb4d8502Sjsg mmCPF_EDC_ROQ_CNT,
1466fb4d8502Sjsg mmCPF_EDC_TAG_CNT,
1467fb4d8502Sjsg mmCPG_EDC_ATC_CNT,
1468fb4d8502Sjsg mmCPG_EDC_DMA_CNT,
1469fb4d8502Sjsg mmCPG_EDC_TAG_CNT,
1470fb4d8502Sjsg mmDC_EDC_CSINVOC_CNT,
1471fb4d8502Sjsg mmDC_EDC_RESTORE_CNT,
1472fb4d8502Sjsg mmDC_EDC_STATE_CNT,
1473fb4d8502Sjsg mmGDS_EDC_CNT,
1474fb4d8502Sjsg mmGDS_EDC_GRBM_CNT,
1475fb4d8502Sjsg mmGDS_EDC_OA_DED,
1476fb4d8502Sjsg mmSPI_EDC_CNT,
1477fb4d8502Sjsg mmSQC_ATC_EDC_GATCL1_CNT,
1478fb4d8502Sjsg mmSQC_EDC_CNT,
1479fb4d8502Sjsg mmSQ_EDC_DED_CNT,
1480fb4d8502Sjsg mmSQ_EDC_INFO,
1481fb4d8502Sjsg mmSQ_EDC_SEC_CNT,
1482fb4d8502Sjsg mmTCC_EDC_CNT,
1483fb4d8502Sjsg mmTCP_ATC_EDC_GATCL1_CNT,
1484fb4d8502Sjsg mmTCP_EDC_CNT,
1485fb4d8502Sjsg mmTD_EDC_CNT
1486fb4d8502Sjsg };
1487fb4d8502Sjsg
gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device * adev)1488fb4d8502Sjsg static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1489fb4d8502Sjsg {
1490fb4d8502Sjsg struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1491fb4d8502Sjsg struct amdgpu_ib ib;
1492fb4d8502Sjsg struct dma_fence *f = NULL;
1493fb4d8502Sjsg int r, i;
1494fb4d8502Sjsg u32 tmp;
1495fb4d8502Sjsg unsigned total_size, vgpr_offset, sgpr_offset;
1496fb4d8502Sjsg u64 gpu_addr;
1497fb4d8502Sjsg
1498fb4d8502Sjsg /* only supported on CZ */
1499fb4d8502Sjsg if (adev->asic_type != CHIP_CARRIZO)
1500fb4d8502Sjsg return 0;
1501fb4d8502Sjsg
1502fb4d8502Sjsg /* bail if the compute ring is not ready */
1503c349dbc7Sjsg if (!ring->sched.ready)
1504fb4d8502Sjsg return 0;
1505fb4d8502Sjsg
1506fb4d8502Sjsg tmp = RREG32(mmGB_EDC_MODE);
1507fb4d8502Sjsg WREG32(mmGB_EDC_MODE, 0);
1508fb4d8502Sjsg
1509fb4d8502Sjsg total_size =
1510fb4d8502Sjsg (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1511fb4d8502Sjsg total_size +=
1512fb4d8502Sjsg (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1513fb4d8502Sjsg total_size +=
1514fb4d8502Sjsg (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1515*f005ef32Sjsg total_size = ALIGN(total_size, 256);
1516fb4d8502Sjsg vgpr_offset = total_size;
1517*f005ef32Sjsg total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1518fb4d8502Sjsg sgpr_offset = total_size;
1519fb4d8502Sjsg total_size += sizeof(sgpr_init_compute_shader);
1520fb4d8502Sjsg
1521fb4d8502Sjsg /* allocate an indirect buffer to put the commands in */
1522fb4d8502Sjsg memset(&ib, 0, sizeof(ib));
1523ad8b1aafSjsg r = amdgpu_ib_get(adev, NULL, total_size,
1524ad8b1aafSjsg AMDGPU_IB_POOL_DIRECT, &ib);
1525fb4d8502Sjsg if (r) {
1526fb4d8502Sjsg DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1527fb4d8502Sjsg return r;
1528fb4d8502Sjsg }
1529fb4d8502Sjsg
1530fb4d8502Sjsg /* load the compute shaders */
1531fb4d8502Sjsg for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1532fb4d8502Sjsg ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1533fb4d8502Sjsg
1534fb4d8502Sjsg for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1535fb4d8502Sjsg ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1536fb4d8502Sjsg
1537fb4d8502Sjsg /* init the ib length to 0 */
1538fb4d8502Sjsg ib.length_dw = 0;
1539fb4d8502Sjsg
1540fb4d8502Sjsg /* VGPR */
1541fb4d8502Sjsg /* write the register state for the compute dispatch */
1542fb4d8502Sjsg for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1543fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1544fb4d8502Sjsg ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1545fb4d8502Sjsg ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1546fb4d8502Sjsg }
1547fb4d8502Sjsg /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1548fb4d8502Sjsg gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1549fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1550fb4d8502Sjsg ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1551fb4d8502Sjsg ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1552fb4d8502Sjsg ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1553fb4d8502Sjsg
1554fb4d8502Sjsg /* write dispatch packet */
1555fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1556fb4d8502Sjsg ib.ptr[ib.length_dw++] = 8; /* x */
1557fb4d8502Sjsg ib.ptr[ib.length_dw++] = 1; /* y */
1558fb4d8502Sjsg ib.ptr[ib.length_dw++] = 1; /* z */
1559fb4d8502Sjsg ib.ptr[ib.length_dw++] =
1560fb4d8502Sjsg REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1561fb4d8502Sjsg
1562fb4d8502Sjsg /* write CS partial flush packet */
1563fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1564fb4d8502Sjsg ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1565fb4d8502Sjsg
1566fb4d8502Sjsg /* SGPR1 */
1567fb4d8502Sjsg /* write the register state for the compute dispatch */
1568fb4d8502Sjsg for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1569fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1570fb4d8502Sjsg ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1571fb4d8502Sjsg ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1572fb4d8502Sjsg }
1573fb4d8502Sjsg /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1574fb4d8502Sjsg gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1575fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1576fb4d8502Sjsg ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1577fb4d8502Sjsg ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1578fb4d8502Sjsg ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1579fb4d8502Sjsg
1580fb4d8502Sjsg /* write dispatch packet */
1581fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1582fb4d8502Sjsg ib.ptr[ib.length_dw++] = 8; /* x */
1583fb4d8502Sjsg ib.ptr[ib.length_dw++] = 1; /* y */
1584fb4d8502Sjsg ib.ptr[ib.length_dw++] = 1; /* z */
1585fb4d8502Sjsg ib.ptr[ib.length_dw++] =
1586fb4d8502Sjsg REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1587fb4d8502Sjsg
1588fb4d8502Sjsg /* write CS partial flush packet */
1589fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1590fb4d8502Sjsg ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1591fb4d8502Sjsg
1592fb4d8502Sjsg /* SGPR2 */
1593fb4d8502Sjsg /* write the register state for the compute dispatch */
1594fb4d8502Sjsg for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1595fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1596fb4d8502Sjsg ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1597fb4d8502Sjsg ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1598fb4d8502Sjsg }
1599fb4d8502Sjsg /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1600fb4d8502Sjsg gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1601fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1602fb4d8502Sjsg ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1603fb4d8502Sjsg ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1604fb4d8502Sjsg ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1605fb4d8502Sjsg
1606fb4d8502Sjsg /* write dispatch packet */
1607fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1608fb4d8502Sjsg ib.ptr[ib.length_dw++] = 8; /* x */
1609fb4d8502Sjsg ib.ptr[ib.length_dw++] = 1; /* y */
1610fb4d8502Sjsg ib.ptr[ib.length_dw++] = 1; /* z */
1611fb4d8502Sjsg ib.ptr[ib.length_dw++] =
1612fb4d8502Sjsg REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1613fb4d8502Sjsg
1614fb4d8502Sjsg /* write CS partial flush packet */
1615fb4d8502Sjsg ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1616fb4d8502Sjsg ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1617fb4d8502Sjsg
1618fb4d8502Sjsg /* shedule the ib on the ring */
1619fb4d8502Sjsg r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1620fb4d8502Sjsg if (r) {
1621fb4d8502Sjsg DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1622fb4d8502Sjsg goto fail;
1623fb4d8502Sjsg }
1624fb4d8502Sjsg
1625fb4d8502Sjsg /* wait for the GPU to finish processing the IB */
1626fb4d8502Sjsg r = dma_fence_wait(f, false);
1627fb4d8502Sjsg if (r) {
1628fb4d8502Sjsg DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1629fb4d8502Sjsg goto fail;
1630fb4d8502Sjsg }
1631fb4d8502Sjsg
1632fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1633fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1634fb4d8502Sjsg WREG32(mmGB_EDC_MODE, tmp);
1635fb4d8502Sjsg
1636fb4d8502Sjsg tmp = RREG32(mmCC_GC_EDC_CONFIG);
1637fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1638fb4d8502Sjsg WREG32(mmCC_GC_EDC_CONFIG, tmp);
1639fb4d8502Sjsg
1640fb4d8502Sjsg
1641fb4d8502Sjsg /* read back registers to clear the counters */
1642fb4d8502Sjsg for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1643fb4d8502Sjsg RREG32(sec_ded_counter_registers[i]);
1644fb4d8502Sjsg
1645fb4d8502Sjsg fail:
1646fb4d8502Sjsg amdgpu_ib_free(adev, &ib, NULL);
1647fb4d8502Sjsg dma_fence_put(f);
1648fb4d8502Sjsg
1649fb4d8502Sjsg return r;
1650fb4d8502Sjsg }
1651fb4d8502Sjsg
gfx_v8_0_gpu_early_init(struct amdgpu_device * adev)1652fb4d8502Sjsg static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1653fb4d8502Sjsg {
1654fb4d8502Sjsg u32 gb_addr_config;
1655c349dbc7Sjsg u32 mc_arb_ramcfg;
1656fb4d8502Sjsg u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1657fb4d8502Sjsg u32 tmp;
1658fb4d8502Sjsg int ret;
1659fb4d8502Sjsg
1660fb4d8502Sjsg switch (adev->asic_type) {
1661fb4d8502Sjsg case CHIP_TOPAZ:
1662fb4d8502Sjsg adev->gfx.config.max_shader_engines = 1;
1663fb4d8502Sjsg adev->gfx.config.max_tile_pipes = 2;
1664fb4d8502Sjsg adev->gfx.config.max_cu_per_sh = 6;
1665fb4d8502Sjsg adev->gfx.config.max_sh_per_se = 1;
1666fb4d8502Sjsg adev->gfx.config.max_backends_per_se = 2;
1667fb4d8502Sjsg adev->gfx.config.max_texture_channel_caches = 2;
1668fb4d8502Sjsg adev->gfx.config.max_gprs = 256;
1669fb4d8502Sjsg adev->gfx.config.max_gs_threads = 32;
1670fb4d8502Sjsg adev->gfx.config.max_hw_contexts = 8;
1671fb4d8502Sjsg
1672fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1673fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1674fb4d8502Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1675fb4d8502Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1676fb4d8502Sjsg gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1677fb4d8502Sjsg break;
1678fb4d8502Sjsg case CHIP_FIJI:
1679fb4d8502Sjsg adev->gfx.config.max_shader_engines = 4;
1680fb4d8502Sjsg adev->gfx.config.max_tile_pipes = 16;
1681fb4d8502Sjsg adev->gfx.config.max_cu_per_sh = 16;
1682fb4d8502Sjsg adev->gfx.config.max_sh_per_se = 1;
1683fb4d8502Sjsg adev->gfx.config.max_backends_per_se = 4;
1684fb4d8502Sjsg adev->gfx.config.max_texture_channel_caches = 16;
1685fb4d8502Sjsg adev->gfx.config.max_gprs = 256;
1686fb4d8502Sjsg adev->gfx.config.max_gs_threads = 32;
1687fb4d8502Sjsg adev->gfx.config.max_hw_contexts = 8;
1688fb4d8502Sjsg
1689fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1690fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1691fb4d8502Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1692fb4d8502Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1693fb4d8502Sjsg gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1694fb4d8502Sjsg break;
1695fb4d8502Sjsg case CHIP_POLARIS11:
1696fb4d8502Sjsg case CHIP_POLARIS12:
1697fb4d8502Sjsg ret = amdgpu_atombios_get_gfx_info(adev);
1698fb4d8502Sjsg if (ret)
1699fb4d8502Sjsg return ret;
1700fb4d8502Sjsg adev->gfx.config.max_gprs = 256;
1701fb4d8502Sjsg adev->gfx.config.max_gs_threads = 32;
1702fb4d8502Sjsg adev->gfx.config.max_hw_contexts = 8;
1703fb4d8502Sjsg
1704fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1705fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1706fb4d8502Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1707fb4d8502Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1708fb4d8502Sjsg gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1709fb4d8502Sjsg break;
1710fb4d8502Sjsg case CHIP_POLARIS10:
1711fb4d8502Sjsg case CHIP_VEGAM:
1712fb4d8502Sjsg ret = amdgpu_atombios_get_gfx_info(adev);
1713fb4d8502Sjsg if (ret)
1714fb4d8502Sjsg return ret;
1715fb4d8502Sjsg adev->gfx.config.max_gprs = 256;
1716fb4d8502Sjsg adev->gfx.config.max_gs_threads = 32;
1717fb4d8502Sjsg adev->gfx.config.max_hw_contexts = 8;
1718fb4d8502Sjsg
1719fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1720fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1721fb4d8502Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1722fb4d8502Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1723fb4d8502Sjsg gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1724fb4d8502Sjsg break;
1725fb4d8502Sjsg case CHIP_TONGA:
1726fb4d8502Sjsg adev->gfx.config.max_shader_engines = 4;
1727fb4d8502Sjsg adev->gfx.config.max_tile_pipes = 8;
1728fb4d8502Sjsg adev->gfx.config.max_cu_per_sh = 8;
1729fb4d8502Sjsg adev->gfx.config.max_sh_per_se = 1;
1730fb4d8502Sjsg adev->gfx.config.max_backends_per_se = 2;
1731fb4d8502Sjsg adev->gfx.config.max_texture_channel_caches = 8;
1732fb4d8502Sjsg adev->gfx.config.max_gprs = 256;
1733fb4d8502Sjsg adev->gfx.config.max_gs_threads = 32;
1734fb4d8502Sjsg adev->gfx.config.max_hw_contexts = 8;
1735fb4d8502Sjsg
1736fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1737fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1738fb4d8502Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1739fb4d8502Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1740fb4d8502Sjsg gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1741fb4d8502Sjsg break;
1742fb4d8502Sjsg case CHIP_CARRIZO:
1743fb4d8502Sjsg adev->gfx.config.max_shader_engines = 1;
1744fb4d8502Sjsg adev->gfx.config.max_tile_pipes = 2;
1745fb4d8502Sjsg adev->gfx.config.max_sh_per_se = 1;
1746fb4d8502Sjsg adev->gfx.config.max_backends_per_se = 2;
1747fb4d8502Sjsg adev->gfx.config.max_cu_per_sh = 8;
1748fb4d8502Sjsg adev->gfx.config.max_texture_channel_caches = 2;
1749fb4d8502Sjsg adev->gfx.config.max_gprs = 256;
1750fb4d8502Sjsg adev->gfx.config.max_gs_threads = 32;
1751fb4d8502Sjsg adev->gfx.config.max_hw_contexts = 8;
1752fb4d8502Sjsg
1753fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1754fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1755fb4d8502Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1756fb4d8502Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1757fb4d8502Sjsg gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1758fb4d8502Sjsg break;
1759fb4d8502Sjsg case CHIP_STONEY:
1760fb4d8502Sjsg adev->gfx.config.max_shader_engines = 1;
1761fb4d8502Sjsg adev->gfx.config.max_tile_pipes = 2;
1762fb4d8502Sjsg adev->gfx.config.max_sh_per_se = 1;
1763fb4d8502Sjsg adev->gfx.config.max_backends_per_se = 1;
1764fb4d8502Sjsg adev->gfx.config.max_cu_per_sh = 3;
1765fb4d8502Sjsg adev->gfx.config.max_texture_channel_caches = 2;
1766fb4d8502Sjsg adev->gfx.config.max_gprs = 256;
1767fb4d8502Sjsg adev->gfx.config.max_gs_threads = 16;
1768fb4d8502Sjsg adev->gfx.config.max_hw_contexts = 8;
1769fb4d8502Sjsg
1770fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1771fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1772fb4d8502Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1773fb4d8502Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1774fb4d8502Sjsg gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1775fb4d8502Sjsg break;
1776fb4d8502Sjsg default:
1777fb4d8502Sjsg adev->gfx.config.max_shader_engines = 2;
1778fb4d8502Sjsg adev->gfx.config.max_tile_pipes = 4;
1779fb4d8502Sjsg adev->gfx.config.max_cu_per_sh = 2;
1780fb4d8502Sjsg adev->gfx.config.max_sh_per_se = 1;
1781fb4d8502Sjsg adev->gfx.config.max_backends_per_se = 2;
1782fb4d8502Sjsg adev->gfx.config.max_texture_channel_caches = 4;
1783fb4d8502Sjsg adev->gfx.config.max_gprs = 256;
1784fb4d8502Sjsg adev->gfx.config.max_gs_threads = 32;
1785fb4d8502Sjsg adev->gfx.config.max_hw_contexts = 8;
1786fb4d8502Sjsg
1787fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1788fb4d8502Sjsg adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1789fb4d8502Sjsg adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1790fb4d8502Sjsg adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1791fb4d8502Sjsg gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1792fb4d8502Sjsg break;
1793fb4d8502Sjsg }
1794fb4d8502Sjsg
1795fb4d8502Sjsg adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1796fb4d8502Sjsg mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1797fb4d8502Sjsg
1798c349dbc7Sjsg adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
1799c349dbc7Sjsg MC_ARB_RAMCFG, NOOFBANK);
1800c349dbc7Sjsg adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
1801c349dbc7Sjsg MC_ARB_RAMCFG, NOOFRANKS);
1802c349dbc7Sjsg
1803fb4d8502Sjsg adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1804fb4d8502Sjsg adev->gfx.config.mem_max_burst_length_bytes = 256;
1805fb4d8502Sjsg if (adev->flags & AMD_IS_APU) {
1806fb4d8502Sjsg /* Get memory bank mapping mode. */
1807fb4d8502Sjsg tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1808fb4d8502Sjsg dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1809fb4d8502Sjsg dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1810fb4d8502Sjsg
1811fb4d8502Sjsg tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1812fb4d8502Sjsg dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1813fb4d8502Sjsg dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1814fb4d8502Sjsg
1815fb4d8502Sjsg /* Validate settings in case only one DIMM installed. */
1816fb4d8502Sjsg if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1817fb4d8502Sjsg dimm00_addr_map = 0;
1818fb4d8502Sjsg if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1819fb4d8502Sjsg dimm01_addr_map = 0;
1820fb4d8502Sjsg if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1821fb4d8502Sjsg dimm10_addr_map = 0;
1822fb4d8502Sjsg if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1823fb4d8502Sjsg dimm11_addr_map = 0;
1824fb4d8502Sjsg
1825fb4d8502Sjsg /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1826fb4d8502Sjsg /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1827fb4d8502Sjsg if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1828fb4d8502Sjsg adev->gfx.config.mem_row_size_in_kb = 2;
1829fb4d8502Sjsg else
1830fb4d8502Sjsg adev->gfx.config.mem_row_size_in_kb = 1;
1831fb4d8502Sjsg } else {
1832fb4d8502Sjsg tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1833fb4d8502Sjsg adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1834fb4d8502Sjsg if (adev->gfx.config.mem_row_size_in_kb > 4)
1835fb4d8502Sjsg adev->gfx.config.mem_row_size_in_kb = 4;
1836fb4d8502Sjsg }
1837fb4d8502Sjsg
1838fb4d8502Sjsg adev->gfx.config.shader_engine_tile_size = 32;
1839fb4d8502Sjsg adev->gfx.config.num_gpus = 1;
1840fb4d8502Sjsg adev->gfx.config.multi_gpu_tile_size = 64;
1841fb4d8502Sjsg
1842fb4d8502Sjsg /* fix up row size */
1843fb4d8502Sjsg switch (adev->gfx.config.mem_row_size_in_kb) {
1844fb4d8502Sjsg case 1:
1845fb4d8502Sjsg default:
1846fb4d8502Sjsg gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1847fb4d8502Sjsg break;
1848fb4d8502Sjsg case 2:
1849fb4d8502Sjsg gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1850fb4d8502Sjsg break;
1851fb4d8502Sjsg case 4:
1852fb4d8502Sjsg gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1853fb4d8502Sjsg break;
1854fb4d8502Sjsg }
1855fb4d8502Sjsg adev->gfx.config.gb_addr_config = gb_addr_config;
1856fb4d8502Sjsg
1857fb4d8502Sjsg return 0;
1858fb4d8502Sjsg }
1859fb4d8502Sjsg
gfx_v8_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)1860fb4d8502Sjsg static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1861fb4d8502Sjsg int mec, int pipe, int queue)
1862fb4d8502Sjsg {
1863fb4d8502Sjsg int r;
1864fb4d8502Sjsg unsigned irq_type;
1865fb4d8502Sjsg struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1866ad8b1aafSjsg unsigned int hw_prio;
1867fb4d8502Sjsg
1868fb4d8502Sjsg ring = &adev->gfx.compute_ring[ring_id];
1869fb4d8502Sjsg
1870fb4d8502Sjsg /* mec0 is me1 */
1871fb4d8502Sjsg ring->me = mec + 1;
1872fb4d8502Sjsg ring->pipe = pipe;
1873fb4d8502Sjsg ring->queue = queue;
1874fb4d8502Sjsg
1875fb4d8502Sjsg ring->ring_obj = NULL;
1876fb4d8502Sjsg ring->use_doorbell = true;
1877c349dbc7Sjsg ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1878fb4d8502Sjsg ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1879fb4d8502Sjsg + (ring_id * GFX8_MEC_HPD_SIZE);
1880fb4d8502Sjsg snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1881fb4d8502Sjsg
1882fb4d8502Sjsg irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1883fb4d8502Sjsg + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1884fb4d8502Sjsg + ring->pipe;
1885fb4d8502Sjsg
18865ca02815Sjsg hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
18871bb76ff1Sjsg AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
1888fb4d8502Sjsg /* type-2 packets are deprecated on MEC, use type-3 instead */
18895ca02815Sjsg r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
18905ca02815Sjsg hw_prio, NULL);
1891fb4d8502Sjsg if (r)
1892fb4d8502Sjsg return r;
1893fb4d8502Sjsg
1894fb4d8502Sjsg
1895fb4d8502Sjsg return 0;
1896fb4d8502Sjsg }
1897fb4d8502Sjsg
1898fb4d8502Sjsg static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1899fb4d8502Sjsg
gfx_v8_0_sw_init(void * handle)1900fb4d8502Sjsg static int gfx_v8_0_sw_init(void *handle)
1901fb4d8502Sjsg {
1902fb4d8502Sjsg int i, j, k, r, ring_id;
1903fb4d8502Sjsg struct amdgpu_ring *ring;
1904fb4d8502Sjsg struct amdgpu_kiq *kiq;
1905fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1906fb4d8502Sjsg
1907fb4d8502Sjsg switch (adev->asic_type) {
1908fb4d8502Sjsg case CHIP_TONGA:
1909fb4d8502Sjsg case CHIP_CARRIZO:
1910fb4d8502Sjsg case CHIP_FIJI:
1911fb4d8502Sjsg case CHIP_POLARIS10:
1912fb4d8502Sjsg case CHIP_POLARIS11:
1913fb4d8502Sjsg case CHIP_POLARIS12:
1914fb4d8502Sjsg case CHIP_VEGAM:
1915fb4d8502Sjsg adev->gfx.mec.num_mec = 2;
1916fb4d8502Sjsg break;
1917fb4d8502Sjsg case CHIP_TOPAZ:
1918fb4d8502Sjsg case CHIP_STONEY:
1919fb4d8502Sjsg default:
1920fb4d8502Sjsg adev->gfx.mec.num_mec = 1;
1921fb4d8502Sjsg break;
1922fb4d8502Sjsg }
1923fb4d8502Sjsg
1924fb4d8502Sjsg adev->gfx.mec.num_pipe_per_mec = 4;
1925fb4d8502Sjsg adev->gfx.mec.num_queue_per_pipe = 8;
1926fb4d8502Sjsg
1927fb4d8502Sjsg /* EOP Event */
1928c349dbc7Sjsg r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1929fb4d8502Sjsg if (r)
1930fb4d8502Sjsg return r;
1931fb4d8502Sjsg
1932fb4d8502Sjsg /* Privileged reg */
1933c349dbc7Sjsg r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1934fb4d8502Sjsg &adev->gfx.priv_reg_irq);
1935fb4d8502Sjsg if (r)
1936fb4d8502Sjsg return r;
1937fb4d8502Sjsg
1938fb4d8502Sjsg /* Privileged inst */
1939c349dbc7Sjsg r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1940fb4d8502Sjsg &adev->gfx.priv_inst_irq);
1941fb4d8502Sjsg if (r)
1942fb4d8502Sjsg return r;
1943fb4d8502Sjsg
1944fb4d8502Sjsg /* Add CP EDC/ECC irq */
1945c349dbc7Sjsg r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1946fb4d8502Sjsg &adev->gfx.cp_ecc_error_irq);
1947fb4d8502Sjsg if (r)
1948fb4d8502Sjsg return r;
1949fb4d8502Sjsg
1950fb4d8502Sjsg /* SQ interrupts. */
1951c349dbc7Sjsg r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
1952fb4d8502Sjsg &adev->gfx.sq_irq);
1953fb4d8502Sjsg if (r) {
1954fb4d8502Sjsg DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
1955fb4d8502Sjsg return r;
1956fb4d8502Sjsg }
1957fb4d8502Sjsg
1958fb4d8502Sjsg INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
1959fb4d8502Sjsg
1960fb4d8502Sjsg adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1961fb4d8502Sjsg
1962fb4d8502Sjsg r = gfx_v8_0_init_microcode(adev);
1963fb4d8502Sjsg if (r) {
1964fb4d8502Sjsg DRM_ERROR("Failed to load gfx firmware!\n");
1965fb4d8502Sjsg return r;
1966fb4d8502Sjsg }
1967fb4d8502Sjsg
1968c349dbc7Sjsg r = adev->gfx.rlc.funcs->init(adev);
1969fb4d8502Sjsg if (r) {
1970fb4d8502Sjsg DRM_ERROR("Failed to init rlc BOs!\n");
1971fb4d8502Sjsg return r;
1972fb4d8502Sjsg }
1973fb4d8502Sjsg
1974fb4d8502Sjsg r = gfx_v8_0_mec_init(adev);
1975fb4d8502Sjsg if (r) {
1976fb4d8502Sjsg DRM_ERROR("Failed to init MEC BOs!\n");
1977fb4d8502Sjsg return r;
1978fb4d8502Sjsg }
1979fb4d8502Sjsg
1980fb4d8502Sjsg /* set up the gfx ring */
1981fb4d8502Sjsg for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1982fb4d8502Sjsg ring = &adev->gfx.gfx_ring[i];
1983fb4d8502Sjsg ring->ring_obj = NULL;
1984fb4d8502Sjsg snprintf(ring->name, sizeof(ring->name), "gfx");
1985fb4d8502Sjsg /* no gfx doorbells on iceland */
1986fb4d8502Sjsg if (adev->asic_type != CHIP_TOPAZ) {
1987fb4d8502Sjsg ring->use_doorbell = true;
1988c349dbc7Sjsg ring->doorbell_index = adev->doorbell_index.gfx_ring0;
1989fb4d8502Sjsg }
1990fb4d8502Sjsg
1991fb4d8502Sjsg r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
1992ad8b1aafSjsg AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
19935ca02815Sjsg AMDGPU_RING_PRIO_DEFAULT, NULL);
1994fb4d8502Sjsg if (r)
1995fb4d8502Sjsg return r;
1996fb4d8502Sjsg }
1997fb4d8502Sjsg
1998fb4d8502Sjsg
1999fb4d8502Sjsg /* set up the compute queues - allocate horizontally across pipes */
2000fb4d8502Sjsg ring_id = 0;
2001fb4d8502Sjsg for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2002fb4d8502Sjsg for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2003fb4d8502Sjsg for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2004*f005ef32Sjsg if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
2005*f005ef32Sjsg k, j))
2006fb4d8502Sjsg continue;
2007fb4d8502Sjsg
2008fb4d8502Sjsg r = gfx_v8_0_compute_ring_init(adev,
2009fb4d8502Sjsg ring_id,
2010fb4d8502Sjsg i, k, j);
2011fb4d8502Sjsg if (r)
2012fb4d8502Sjsg return r;
2013fb4d8502Sjsg
2014fb4d8502Sjsg ring_id++;
2015fb4d8502Sjsg }
2016fb4d8502Sjsg }
2017fb4d8502Sjsg }
2018fb4d8502Sjsg
2019*f005ef32Sjsg r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE, 0);
2020fb4d8502Sjsg if (r) {
2021fb4d8502Sjsg DRM_ERROR("Failed to init KIQ BOs!\n");
2022fb4d8502Sjsg return r;
2023fb4d8502Sjsg }
2024fb4d8502Sjsg
2025*f005ef32Sjsg kiq = &adev->gfx.kiq[0];
2026*f005ef32Sjsg r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
2027fb4d8502Sjsg if (r)
2028fb4d8502Sjsg return r;
2029fb4d8502Sjsg
2030fb4d8502Sjsg /* create MQD for all compute queues as well as KIQ for SRIOV case */
2031*f005ef32Sjsg r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation), 0);
2032fb4d8502Sjsg if (r)
2033fb4d8502Sjsg return r;
2034fb4d8502Sjsg
2035fb4d8502Sjsg adev->gfx.ce_ram_size = 0x8000;
2036fb4d8502Sjsg
2037fb4d8502Sjsg r = gfx_v8_0_gpu_early_init(adev);
2038fb4d8502Sjsg if (r)
2039fb4d8502Sjsg return r;
2040fb4d8502Sjsg
2041fb4d8502Sjsg return 0;
2042fb4d8502Sjsg }
2043fb4d8502Sjsg
gfx_v8_0_sw_fini(void * handle)2044fb4d8502Sjsg static int gfx_v8_0_sw_fini(void *handle)
2045fb4d8502Sjsg {
2046fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2047c349dbc7Sjsg int i;
2048fb4d8502Sjsg
2049fb4d8502Sjsg for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2050fb4d8502Sjsg amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2051fb4d8502Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++)
2052fb4d8502Sjsg amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2053fb4d8502Sjsg
2054*f005ef32Sjsg amdgpu_gfx_mqd_sw_fini(adev, 0);
2055*f005ef32Sjsg amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
2056*f005ef32Sjsg amdgpu_gfx_kiq_fini(adev, 0);
2057fb4d8502Sjsg
2058fb4d8502Sjsg gfx_v8_0_mec_fini(adev);
2059c349dbc7Sjsg amdgpu_gfx_rlc_fini(adev);
2060fb4d8502Sjsg amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2061fb4d8502Sjsg &adev->gfx.rlc.clear_state_gpu_addr,
2062fb4d8502Sjsg (void **)&adev->gfx.rlc.cs_ptr);
2063fb4d8502Sjsg if ((adev->asic_type == CHIP_CARRIZO) ||
2064fb4d8502Sjsg (adev->asic_type == CHIP_STONEY)) {
2065fb4d8502Sjsg amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2066fb4d8502Sjsg &adev->gfx.rlc.cp_table_gpu_addr,
2067fb4d8502Sjsg (void **)&adev->gfx.rlc.cp_table_ptr);
2068fb4d8502Sjsg }
2069fb4d8502Sjsg gfx_v8_0_free_microcode(adev);
2070fb4d8502Sjsg
2071fb4d8502Sjsg return 0;
2072fb4d8502Sjsg }
2073fb4d8502Sjsg
gfx_v8_0_tiling_mode_table_init(struct amdgpu_device * adev)2074fb4d8502Sjsg static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2075fb4d8502Sjsg {
2076fb4d8502Sjsg uint32_t *modearray, *mod2array;
2077fb4d8502Sjsg const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2078fb4d8502Sjsg const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2079fb4d8502Sjsg u32 reg_offset;
2080fb4d8502Sjsg
2081fb4d8502Sjsg modearray = adev->gfx.config.tile_mode_array;
2082fb4d8502Sjsg mod2array = adev->gfx.config.macrotile_mode_array;
2083fb4d8502Sjsg
2084fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2085fb4d8502Sjsg modearray[reg_offset] = 0;
2086fb4d8502Sjsg
2087fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2088fb4d8502Sjsg mod2array[reg_offset] = 0;
2089fb4d8502Sjsg
2090fb4d8502Sjsg switch (adev->asic_type) {
2091fb4d8502Sjsg case CHIP_TOPAZ:
2092fb4d8502Sjsg modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2093fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2094fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2095fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2096fb4d8502Sjsg modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2097fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2098fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2099fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2100fb4d8502Sjsg modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2101fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2102fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2103fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2104fb4d8502Sjsg modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2105fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2106fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2107fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2108fb4d8502Sjsg modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2109fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2110fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2111fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2112fb4d8502Sjsg modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2113fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2114fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2115fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2116fb4d8502Sjsg modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2117fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2118fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2119fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2120fb4d8502Sjsg modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2121fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2));
2122fb4d8502Sjsg modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2123fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2124fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2125fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2126fb4d8502Sjsg modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2127fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2128fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2129fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2130fb4d8502Sjsg modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2131fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2132fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2133fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2134fb4d8502Sjsg modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2135fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2136fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2137fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2138fb4d8502Sjsg modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2139fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2140fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2141fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2142fb4d8502Sjsg modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2143fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2144fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2145fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2146fb4d8502Sjsg modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2147fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2148fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2149fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2150fb4d8502Sjsg modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2151fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2152fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2153fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2154fb4d8502Sjsg modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2155fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2156fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2157fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2158fb4d8502Sjsg modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2159fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2160fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2161fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2162fb4d8502Sjsg modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2163fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2164fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2165fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2166fb4d8502Sjsg modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2167fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2168fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2169fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2170fb4d8502Sjsg modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2171fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2172fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2173fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2174fb4d8502Sjsg modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2175fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2176fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2177fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2178fb4d8502Sjsg modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2179fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2180fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2181fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2182fb4d8502Sjsg modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2183fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2184fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2185fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2186fb4d8502Sjsg modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2187fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2188fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2189fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2190fb4d8502Sjsg modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2191fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
2192fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2193fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2194fb4d8502Sjsg
2195fb4d8502Sjsg mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2196fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2197fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2198fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2199fb4d8502Sjsg mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2200fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2201fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2202fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2203fb4d8502Sjsg mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2204fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2205fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2206fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2207fb4d8502Sjsg mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2208fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2209fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2210fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2211fb4d8502Sjsg mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2212fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2213fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2214fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2215fb4d8502Sjsg mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2216fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2217fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2218fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2219fb4d8502Sjsg mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2220fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2221fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2222fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2223fb4d8502Sjsg mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2224fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2225fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2226fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2227fb4d8502Sjsg mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2228fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2229fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2230fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2231fb4d8502Sjsg mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2232fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2233fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2234fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2235fb4d8502Sjsg mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2236fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2237fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2238fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2239fb4d8502Sjsg mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2240fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2241fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2242fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2243fb4d8502Sjsg mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2244fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2245fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2246fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2247fb4d8502Sjsg mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2248fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2249fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2250fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2251fb4d8502Sjsg
2252fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2253fb4d8502Sjsg if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2254fb4d8502Sjsg reg_offset != 23)
2255fb4d8502Sjsg WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2256fb4d8502Sjsg
2257fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2258fb4d8502Sjsg if (reg_offset != 7)
2259fb4d8502Sjsg WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2260fb4d8502Sjsg
2261fb4d8502Sjsg break;
2262fb4d8502Sjsg case CHIP_FIJI:
2263fb4d8502Sjsg case CHIP_VEGAM:
2264fb4d8502Sjsg modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2265fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2266fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2267fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2268fb4d8502Sjsg modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2269fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2270fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2271fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2272fb4d8502Sjsg modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2273fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2274fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2275fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2276fb4d8502Sjsg modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2277fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2278fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2279fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2280fb4d8502Sjsg modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2281fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2282fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2283fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2284fb4d8502Sjsg modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2285fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2286fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2287fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2288fb4d8502Sjsg modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2289fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2290fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2291fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2292fb4d8502Sjsg modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2293fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2294fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2295fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2296fb4d8502Sjsg modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2297fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2298fb4d8502Sjsg modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2299fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2300fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2301fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2302fb4d8502Sjsg modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2303fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2304fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2305fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2306fb4d8502Sjsg modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2307fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2308fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2309fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2310fb4d8502Sjsg modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2311fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2312fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2313fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2314fb4d8502Sjsg modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2315fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2316fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2317fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2318fb4d8502Sjsg modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2319fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2320fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2321fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2322fb4d8502Sjsg modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2323fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2324fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2325fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2326fb4d8502Sjsg modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2327fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2328fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2329fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2330fb4d8502Sjsg modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2331fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2332fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2333fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2334fb4d8502Sjsg modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2335fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2336fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2337fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2338fb4d8502Sjsg modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2339fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2340fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2341fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2342fb4d8502Sjsg modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2343fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2344fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2345fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2346fb4d8502Sjsg modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2347fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2348fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2349fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2350fb4d8502Sjsg modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2351fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2352fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2353fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2354fb4d8502Sjsg modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2355fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2356fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2357fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2358fb4d8502Sjsg modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2359fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2360fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2361fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2362fb4d8502Sjsg modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2363fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2364fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2365fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2366fb4d8502Sjsg modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2367fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2368fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2369fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2370fb4d8502Sjsg modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2371fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2372fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2373fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2374fb4d8502Sjsg modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2375fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2376fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2377fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2378fb4d8502Sjsg modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2379fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2380fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2381fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2382fb4d8502Sjsg modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2383fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2384fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2385fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2386fb4d8502Sjsg
2387fb4d8502Sjsg mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2388fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2389fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2390fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2391fb4d8502Sjsg mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2392fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2393fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2394fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2395fb4d8502Sjsg mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2396fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2397fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2398fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2399fb4d8502Sjsg mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2400fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2401fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2402fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2403fb4d8502Sjsg mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2404fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2405fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2406fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2407fb4d8502Sjsg mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2408fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2409fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2410fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2411fb4d8502Sjsg mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2412fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2413fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2414fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2415fb4d8502Sjsg mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2416fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2417fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2418fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2419fb4d8502Sjsg mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2420fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2421fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2422fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2423fb4d8502Sjsg mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2424fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2425fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2426fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2427fb4d8502Sjsg mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2428fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2429fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2430fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2431fb4d8502Sjsg mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2432fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2433fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2434fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2435fb4d8502Sjsg mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2436fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2437fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2438fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2439fb4d8502Sjsg mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2440fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2441fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2442fb4d8502Sjsg NUM_BANKS(ADDR_SURF_4_BANK));
2443fb4d8502Sjsg
2444fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2445fb4d8502Sjsg WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2446fb4d8502Sjsg
2447fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2448fb4d8502Sjsg if (reg_offset != 7)
2449fb4d8502Sjsg WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2450fb4d8502Sjsg
2451fb4d8502Sjsg break;
2452fb4d8502Sjsg case CHIP_TONGA:
2453fb4d8502Sjsg modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2454fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2455fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2456fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2457fb4d8502Sjsg modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2458fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2459fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2460fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2461fb4d8502Sjsg modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2462fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2463fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2464fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2465fb4d8502Sjsg modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2466fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2467fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2468fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2469fb4d8502Sjsg modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2470fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2471fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2472fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2473fb4d8502Sjsg modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2474fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2475fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2476fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2477fb4d8502Sjsg modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2478fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2479fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2480fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2481fb4d8502Sjsg modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2482fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2483fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2484fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2485fb4d8502Sjsg modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2486fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2487fb4d8502Sjsg modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2488fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2489fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2490fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2491fb4d8502Sjsg modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2492fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2493fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2494fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2495fb4d8502Sjsg modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2496fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2497fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2498fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2499fb4d8502Sjsg modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2500fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2501fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2502fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2503fb4d8502Sjsg modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2504fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2505fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2506fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2507fb4d8502Sjsg modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2508fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2509fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2510fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2511fb4d8502Sjsg modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2512fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2513fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2514fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2515fb4d8502Sjsg modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2516fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2517fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2518fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2519fb4d8502Sjsg modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2520fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2521fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2522fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2523fb4d8502Sjsg modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2524fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2525fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2526fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2527fb4d8502Sjsg modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2528fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2529fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2530fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2531fb4d8502Sjsg modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2532fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2533fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2534fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2535fb4d8502Sjsg modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2536fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2537fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2538fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2539fb4d8502Sjsg modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2540fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2541fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2542fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2543fb4d8502Sjsg modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2544fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2545fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2546fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2547fb4d8502Sjsg modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2548fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2549fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2550fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2551fb4d8502Sjsg modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2552fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2553fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2554fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2555fb4d8502Sjsg modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2556fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2557fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2558fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2559fb4d8502Sjsg modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2560fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2561fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2562fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2563fb4d8502Sjsg modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2564fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2565fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2566fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2567fb4d8502Sjsg modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2568fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2569fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2570fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2571fb4d8502Sjsg modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2572fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2573fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2574fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2575fb4d8502Sjsg
2576fb4d8502Sjsg mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2577fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2578fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2579fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2580fb4d8502Sjsg mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2581fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2582fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2583fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2584fb4d8502Sjsg mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2585fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2586fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2587fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2588fb4d8502Sjsg mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2589fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2590fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2591fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2592fb4d8502Sjsg mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2593fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2594fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2595fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2596fb4d8502Sjsg mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2597fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2598fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2599fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2600fb4d8502Sjsg mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2601fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2602fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2603fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2604fb4d8502Sjsg mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2605fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2606fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2607fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2608fb4d8502Sjsg mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2610fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2611fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2612fb4d8502Sjsg mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2613fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2614fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2615fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2616fb4d8502Sjsg mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2617fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2618fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2619fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2620fb4d8502Sjsg mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2621fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2622fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2623fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2624fb4d8502Sjsg mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2625fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2626fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2627fb4d8502Sjsg NUM_BANKS(ADDR_SURF_4_BANK));
2628fb4d8502Sjsg mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2629fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2630fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2631fb4d8502Sjsg NUM_BANKS(ADDR_SURF_4_BANK));
2632fb4d8502Sjsg
2633fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2634fb4d8502Sjsg WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2635fb4d8502Sjsg
2636fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2637fb4d8502Sjsg if (reg_offset != 7)
2638fb4d8502Sjsg WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2639fb4d8502Sjsg
2640fb4d8502Sjsg break;
2641fb4d8502Sjsg case CHIP_POLARIS11:
2642fb4d8502Sjsg case CHIP_POLARIS12:
2643fb4d8502Sjsg modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2644fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2645fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2646fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2647fb4d8502Sjsg modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2648fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2649fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2650fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2651fb4d8502Sjsg modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2652fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2653fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2654fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2655fb4d8502Sjsg modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2656fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2657fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2658fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2659fb4d8502Sjsg modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2660fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2661fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2662fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2663fb4d8502Sjsg modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2664fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2665fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2666fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2667fb4d8502Sjsg modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2668fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2669fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2670fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2671fb4d8502Sjsg modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2672fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2673fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2674fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2675fb4d8502Sjsg modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2676fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16));
2677fb4d8502Sjsg modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2678fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2679fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2680fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2681fb4d8502Sjsg modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2682fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2683fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2684fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2685fb4d8502Sjsg modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2686fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2687fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2688fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2689fb4d8502Sjsg modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2690fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2691fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2692fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2693fb4d8502Sjsg modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2694fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2695fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2696fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2697fb4d8502Sjsg modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2698fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2699fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2700fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2701fb4d8502Sjsg modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2702fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2703fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2704fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2705fb4d8502Sjsg modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2706fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2707fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2708fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2709fb4d8502Sjsg modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2710fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2711fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2712fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2713fb4d8502Sjsg modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2714fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2715fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2716fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2717fb4d8502Sjsg modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2718fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2719fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2720fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2721fb4d8502Sjsg modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2722fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2723fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2724fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2725fb4d8502Sjsg modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2726fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2727fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2728fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2729fb4d8502Sjsg modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2730fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2731fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2732fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2733fb4d8502Sjsg modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2734fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2735fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2736fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2737fb4d8502Sjsg modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2738fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2739fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2740fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2741fb4d8502Sjsg modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2742fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2743fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2744fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2745fb4d8502Sjsg modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2746fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2747fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2748fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2749fb4d8502Sjsg modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2750fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2751fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2752fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2753fb4d8502Sjsg modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2754fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2755fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2756fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2757fb4d8502Sjsg modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2758fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2759fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2760fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2761fb4d8502Sjsg modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2762fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2763fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2764fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2765fb4d8502Sjsg
2766fb4d8502Sjsg mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2767fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2768fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2769fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2770fb4d8502Sjsg
2771fb4d8502Sjsg mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2772fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2773fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2774fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2775fb4d8502Sjsg
2776fb4d8502Sjsg mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2777fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2778fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2779fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2780fb4d8502Sjsg
2781fb4d8502Sjsg mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2782fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2783fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2784fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2785fb4d8502Sjsg
2786fb4d8502Sjsg mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2787fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2788fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2789fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2790fb4d8502Sjsg
2791fb4d8502Sjsg mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2792fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2793fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2794fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2795fb4d8502Sjsg
2796fb4d8502Sjsg mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2797fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2798fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2799fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2800fb4d8502Sjsg
2801fb4d8502Sjsg mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2802fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2803fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2804fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2805fb4d8502Sjsg
2806fb4d8502Sjsg mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2807fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2808fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2809fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2810fb4d8502Sjsg
2811fb4d8502Sjsg mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2812fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2813fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2814fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2815fb4d8502Sjsg
2816fb4d8502Sjsg mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2817fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2818fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2819fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2820fb4d8502Sjsg
2821fb4d8502Sjsg mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2822fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2823fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2824fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2825fb4d8502Sjsg
2826fb4d8502Sjsg mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2827fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2828fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2829fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
2830fb4d8502Sjsg
2831fb4d8502Sjsg mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2832fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2833fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2834fb4d8502Sjsg NUM_BANKS(ADDR_SURF_4_BANK));
2835fb4d8502Sjsg
2836fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2837fb4d8502Sjsg WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2838fb4d8502Sjsg
2839fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2840fb4d8502Sjsg if (reg_offset != 7)
2841fb4d8502Sjsg WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2842fb4d8502Sjsg
2843fb4d8502Sjsg break;
2844fb4d8502Sjsg case CHIP_POLARIS10:
2845fb4d8502Sjsg modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2846fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2847fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2848fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2849fb4d8502Sjsg modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2850fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2851fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2852fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2853fb4d8502Sjsg modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2854fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2855fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2856fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2857fb4d8502Sjsg modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2858fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2859fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2860fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2861fb4d8502Sjsg modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2862fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2863fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2864fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2865fb4d8502Sjsg modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2866fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2867fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2868fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2869fb4d8502Sjsg modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2870fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2871fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2872fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2873fb4d8502Sjsg modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2874fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2875fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2876fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2877fb4d8502Sjsg modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2878fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2879fb4d8502Sjsg modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2880fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2881fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2882fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2883fb4d8502Sjsg modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2884fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2885fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2886fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2887fb4d8502Sjsg modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2888fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2889fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2890fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2891fb4d8502Sjsg modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2892fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2893fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2894fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2895fb4d8502Sjsg modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2896fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2897fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2898fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2899fb4d8502Sjsg modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2900fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2901fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2902fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2903fb4d8502Sjsg modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2904fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2905fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2906fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2907fb4d8502Sjsg modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2908fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2909fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2910fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2911fb4d8502Sjsg modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2912fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2913fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2914fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2915fb4d8502Sjsg modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2916fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2917fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2918fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2919fb4d8502Sjsg modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2920fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2921fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2922fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2923fb4d8502Sjsg modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2924fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2925fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2926fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2927fb4d8502Sjsg modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2928fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2929fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2930fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2931fb4d8502Sjsg modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2932fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2933fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2934fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2935fb4d8502Sjsg modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2936fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2937fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2938fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2939fb4d8502Sjsg modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2940fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2941fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2942fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2943fb4d8502Sjsg modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2944fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2945fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2946fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2947fb4d8502Sjsg modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2948fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2949fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2950fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2951fb4d8502Sjsg modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2952fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2953fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2954fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2955fb4d8502Sjsg modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2956fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2957fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2958fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2959fb4d8502Sjsg modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2960fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2961fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2962fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2963fb4d8502Sjsg modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2964fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2965fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2966fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2967fb4d8502Sjsg
2968fb4d8502Sjsg mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2969fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2970fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2971fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2972fb4d8502Sjsg
2973fb4d8502Sjsg mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2974fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2975fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2976fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2977fb4d8502Sjsg
2978fb4d8502Sjsg mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2979fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2980fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2981fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2982fb4d8502Sjsg
2983fb4d8502Sjsg mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2984fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2985fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2986fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2987fb4d8502Sjsg
2988fb4d8502Sjsg mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2989fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2990fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2991fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2992fb4d8502Sjsg
2993fb4d8502Sjsg mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2994fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2995fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2996fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
2997fb4d8502Sjsg
2998fb4d8502Sjsg mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2999fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3000fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3001fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3002fb4d8502Sjsg
3003fb4d8502Sjsg mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3004fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3005fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3006fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3007fb4d8502Sjsg
3008fb4d8502Sjsg mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3009fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3010fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3011fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3012fb4d8502Sjsg
3013fb4d8502Sjsg mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3014fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3015fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3016fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3017fb4d8502Sjsg
3018fb4d8502Sjsg mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3019fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3020fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3021fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3022fb4d8502Sjsg
3023fb4d8502Sjsg mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3024fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3025fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3026fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3027fb4d8502Sjsg
3028fb4d8502Sjsg mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3029fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3030fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3031fb4d8502Sjsg NUM_BANKS(ADDR_SURF_4_BANK));
3032fb4d8502Sjsg
3033fb4d8502Sjsg mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3034fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3035fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3036fb4d8502Sjsg NUM_BANKS(ADDR_SURF_4_BANK));
3037fb4d8502Sjsg
3038fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3039fb4d8502Sjsg WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3040fb4d8502Sjsg
3041fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3042fb4d8502Sjsg if (reg_offset != 7)
3043fb4d8502Sjsg WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3044fb4d8502Sjsg
3045fb4d8502Sjsg break;
3046fb4d8502Sjsg case CHIP_STONEY:
3047fb4d8502Sjsg modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3048fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3049fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3050fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3051fb4d8502Sjsg modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3052fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3053fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3054fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3055fb4d8502Sjsg modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3056fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3057fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3058fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3059fb4d8502Sjsg modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3060fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3061fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3062fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3063fb4d8502Sjsg modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3064fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3065fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3066fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3067fb4d8502Sjsg modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3068fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3069fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3070fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3071fb4d8502Sjsg modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3072fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3073fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3074fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3075fb4d8502Sjsg modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3076fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2));
3077fb4d8502Sjsg modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3078fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3079fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3080fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3081fb4d8502Sjsg modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3082fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3083fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3084fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3085fb4d8502Sjsg modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3086fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3087fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3088fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3089fb4d8502Sjsg modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3090fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3091fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3092fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3093fb4d8502Sjsg modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3094fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3095fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3096fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3097fb4d8502Sjsg modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3098fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3099fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3100fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3101fb4d8502Sjsg modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3102fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3103fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3104fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3105fb4d8502Sjsg modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3106fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3107fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3108fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3109fb4d8502Sjsg modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3110fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3111fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3112fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3113fb4d8502Sjsg modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3114fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3115fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3116fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3117fb4d8502Sjsg modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3118fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3119fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3120fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3121fb4d8502Sjsg modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3122fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3123fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3124fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3125fb4d8502Sjsg modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3126fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3127fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3128fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3129fb4d8502Sjsg modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3130fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3131fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3132fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3133fb4d8502Sjsg modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3134fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3135fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3136fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3137fb4d8502Sjsg modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3138fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3139fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3140fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3141fb4d8502Sjsg modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3142fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3143fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3144fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3145fb4d8502Sjsg modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3146fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3147fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3148fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3149fb4d8502Sjsg
3150fb4d8502Sjsg mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3151fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3152fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3153fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3154fb4d8502Sjsg mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3155fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3156fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3157fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3158fb4d8502Sjsg mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3159fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3160fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3161fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3162fb4d8502Sjsg mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3163fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3164fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3165fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3166fb4d8502Sjsg mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3167fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3168fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3169fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3170fb4d8502Sjsg mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3171fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3172fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3173fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3174fb4d8502Sjsg mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3175fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3176fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3177fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3178fb4d8502Sjsg mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3179fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3180fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3181fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3182fb4d8502Sjsg mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3183fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3184fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3185fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3186fb4d8502Sjsg mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3187fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3188fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3189fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3190fb4d8502Sjsg mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3191fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3192fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3193fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3194fb4d8502Sjsg mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3195fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3196fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3197fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3198fb4d8502Sjsg mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3199fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3200fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3201fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3202fb4d8502Sjsg mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3203fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3204fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3205fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3206fb4d8502Sjsg
3207fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3208fb4d8502Sjsg if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3209fb4d8502Sjsg reg_offset != 23)
3210fb4d8502Sjsg WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3211fb4d8502Sjsg
3212fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3213fb4d8502Sjsg if (reg_offset != 7)
3214fb4d8502Sjsg WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3215fb4d8502Sjsg
3216fb4d8502Sjsg break;
3217fb4d8502Sjsg default:
3218fb4d8502Sjsg dev_warn(adev->dev,
3219fb4d8502Sjsg "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3220fb4d8502Sjsg adev->asic_type);
3221ad8b1aafSjsg fallthrough;
3222fb4d8502Sjsg
3223fb4d8502Sjsg case CHIP_CARRIZO:
3224fb4d8502Sjsg modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3225fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3226fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3227fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3228fb4d8502Sjsg modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3229fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3230fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3231fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3232fb4d8502Sjsg modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3233fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3234fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3235fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3236fb4d8502Sjsg modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3237fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3238fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3239fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3240fb4d8502Sjsg modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3241fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3242fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3243fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3244fb4d8502Sjsg modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3245fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3246fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3247fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3248fb4d8502Sjsg modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3249fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3250fb4d8502Sjsg TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3251fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3252fb4d8502Sjsg modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3253fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2));
3254fb4d8502Sjsg modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3255fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3256fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3257fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3258fb4d8502Sjsg modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3259fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3260fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3261fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3262fb4d8502Sjsg modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3263fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3264fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3265fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3266fb4d8502Sjsg modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3267fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3268fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3269fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3270fb4d8502Sjsg modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3271fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3272fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3273fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3274fb4d8502Sjsg modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3275fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3276fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3277fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3278fb4d8502Sjsg modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3279fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3280fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3281fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3282fb4d8502Sjsg modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3283fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3284fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3285fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3286fb4d8502Sjsg modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3287fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3288fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3289fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3290fb4d8502Sjsg modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3291fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3292fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3293fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3294fb4d8502Sjsg modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3295fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3296fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3297fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3298fb4d8502Sjsg modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3299fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3300fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3301fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3302fb4d8502Sjsg modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3303fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3304fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3305fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3306fb4d8502Sjsg modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3307fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3308fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3309fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3310fb4d8502Sjsg modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3311fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3312fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3313fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3314fb4d8502Sjsg modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3315fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3316fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3317fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3318fb4d8502Sjsg modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3319fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3320fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3321fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3322fb4d8502Sjsg modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3323fb4d8502Sjsg PIPE_CONFIG(ADDR_SURF_P2) |
3324fb4d8502Sjsg MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3325fb4d8502Sjsg SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3326fb4d8502Sjsg
3327fb4d8502Sjsg mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3328fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3329fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3330fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3331fb4d8502Sjsg mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3332fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3333fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3334fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3335fb4d8502Sjsg mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3336fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3337fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3338fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3339fb4d8502Sjsg mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3340fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3341fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3342fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3343fb4d8502Sjsg mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3344fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3345fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3346fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3347fb4d8502Sjsg mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3348fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3349fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3350fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3351fb4d8502Sjsg mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3352fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3353fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3354fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3355fb4d8502Sjsg mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3356fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3357fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3358fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3359fb4d8502Sjsg mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3360fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3361fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3362fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3363fb4d8502Sjsg mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3364fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3365fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3366fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3367fb4d8502Sjsg mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3368fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3369fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3370fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3371fb4d8502Sjsg mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3372fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3373fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3374fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3375fb4d8502Sjsg mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3376fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3377fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3378fb4d8502Sjsg NUM_BANKS(ADDR_SURF_16_BANK));
3379fb4d8502Sjsg mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3380fb4d8502Sjsg BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3381fb4d8502Sjsg MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3382fb4d8502Sjsg NUM_BANKS(ADDR_SURF_8_BANK));
3383fb4d8502Sjsg
3384fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3385fb4d8502Sjsg if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3386fb4d8502Sjsg reg_offset != 23)
3387fb4d8502Sjsg WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3388fb4d8502Sjsg
3389fb4d8502Sjsg for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3390fb4d8502Sjsg if (reg_offset != 7)
3391fb4d8502Sjsg WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3392fb4d8502Sjsg
3393fb4d8502Sjsg break;
3394fb4d8502Sjsg }
3395fb4d8502Sjsg }
3396fb4d8502Sjsg
gfx_v8_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)3397fb4d8502Sjsg static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3398*f005ef32Sjsg u32 se_num, u32 sh_num, u32 instance,
3399*f005ef32Sjsg int xcc_id)
3400fb4d8502Sjsg {
3401fb4d8502Sjsg u32 data;
3402fb4d8502Sjsg
3403fb4d8502Sjsg if (instance == 0xffffffff)
3404fb4d8502Sjsg data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3405fb4d8502Sjsg else
3406fb4d8502Sjsg data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3407fb4d8502Sjsg
3408fb4d8502Sjsg if (se_num == 0xffffffff)
3409fb4d8502Sjsg data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3410fb4d8502Sjsg else
3411fb4d8502Sjsg data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3412fb4d8502Sjsg
3413fb4d8502Sjsg if (sh_num == 0xffffffff)
3414fb4d8502Sjsg data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3415fb4d8502Sjsg else
3416fb4d8502Sjsg data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3417fb4d8502Sjsg
3418fb4d8502Sjsg WREG32(mmGRBM_GFX_INDEX, data);
3419fb4d8502Sjsg }
3420fb4d8502Sjsg
gfx_v8_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)3421fb4d8502Sjsg static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3422*f005ef32Sjsg u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
3423fb4d8502Sjsg {
3424c349dbc7Sjsg vi_srbm_select(adev, me, pipe, q, vm);
3425fb4d8502Sjsg }
3426fb4d8502Sjsg
gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device * adev)3427fb4d8502Sjsg static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3428fb4d8502Sjsg {
3429fb4d8502Sjsg u32 data, mask;
3430fb4d8502Sjsg
3431fb4d8502Sjsg data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3432fb4d8502Sjsg RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3433fb4d8502Sjsg
3434fb4d8502Sjsg data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3435fb4d8502Sjsg
3436fb4d8502Sjsg mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3437fb4d8502Sjsg adev->gfx.config.max_sh_per_se);
3438fb4d8502Sjsg
3439fb4d8502Sjsg return (~data) & mask;
3440fb4d8502Sjsg }
3441fb4d8502Sjsg
3442fb4d8502Sjsg static void
gfx_v8_0_raster_config(struct amdgpu_device * adev,u32 * rconf,u32 * rconf1)3443fb4d8502Sjsg gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3444fb4d8502Sjsg {
3445fb4d8502Sjsg switch (adev->asic_type) {
3446fb4d8502Sjsg case CHIP_FIJI:
3447fb4d8502Sjsg case CHIP_VEGAM:
3448fb4d8502Sjsg *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3449fb4d8502Sjsg RB_XSEL2(1) | PKR_MAP(2) |
3450fb4d8502Sjsg PKR_XSEL(1) | PKR_YSEL(1) |
3451fb4d8502Sjsg SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3452fb4d8502Sjsg *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3453fb4d8502Sjsg SE_PAIR_YSEL(2);
3454fb4d8502Sjsg break;
3455fb4d8502Sjsg case CHIP_TONGA:
3456fb4d8502Sjsg case CHIP_POLARIS10:
3457fb4d8502Sjsg *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3458fb4d8502Sjsg SE_XSEL(1) | SE_YSEL(1);
3459fb4d8502Sjsg *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3460fb4d8502Sjsg SE_PAIR_YSEL(2);
3461fb4d8502Sjsg break;
3462fb4d8502Sjsg case CHIP_TOPAZ:
3463fb4d8502Sjsg case CHIP_CARRIZO:
3464fb4d8502Sjsg *rconf |= RB_MAP_PKR0(2);
3465fb4d8502Sjsg *rconf1 |= 0x0;
3466fb4d8502Sjsg break;
3467fb4d8502Sjsg case CHIP_POLARIS11:
3468fb4d8502Sjsg case CHIP_POLARIS12:
3469fb4d8502Sjsg *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3470fb4d8502Sjsg SE_XSEL(1) | SE_YSEL(1);
3471fb4d8502Sjsg *rconf1 |= 0x0;
3472fb4d8502Sjsg break;
3473fb4d8502Sjsg case CHIP_STONEY:
3474fb4d8502Sjsg *rconf |= 0x0;
3475fb4d8502Sjsg *rconf1 |= 0x0;
3476fb4d8502Sjsg break;
3477fb4d8502Sjsg default:
3478fb4d8502Sjsg DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3479fb4d8502Sjsg break;
3480fb4d8502Sjsg }
3481fb4d8502Sjsg }
3482fb4d8502Sjsg
3483fb4d8502Sjsg static void
gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device * adev,u32 raster_config,u32 raster_config_1,unsigned rb_mask,unsigned num_rb)3484fb4d8502Sjsg gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3485fb4d8502Sjsg u32 raster_config, u32 raster_config_1,
3486fb4d8502Sjsg unsigned rb_mask, unsigned num_rb)
3487fb4d8502Sjsg {
3488fb4d8502Sjsg unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3489fb4d8502Sjsg unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3490fb4d8502Sjsg unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3491fb4d8502Sjsg unsigned rb_per_se = num_rb / num_se;
3492fb4d8502Sjsg unsigned se_mask[4];
3493fb4d8502Sjsg unsigned se;
3494fb4d8502Sjsg
3495fb4d8502Sjsg se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3496fb4d8502Sjsg se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3497fb4d8502Sjsg se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3498fb4d8502Sjsg se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3499fb4d8502Sjsg
3500fb4d8502Sjsg WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3501fb4d8502Sjsg WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3502fb4d8502Sjsg WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3503fb4d8502Sjsg
3504fb4d8502Sjsg if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3505fb4d8502Sjsg (!se_mask[2] && !se_mask[3]))) {
3506fb4d8502Sjsg raster_config_1 &= ~SE_PAIR_MAP_MASK;
3507fb4d8502Sjsg
3508fb4d8502Sjsg if (!se_mask[0] && !se_mask[1]) {
3509fb4d8502Sjsg raster_config_1 |=
3510fb4d8502Sjsg SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3511fb4d8502Sjsg } else {
3512fb4d8502Sjsg raster_config_1 |=
3513fb4d8502Sjsg SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3514fb4d8502Sjsg }
3515fb4d8502Sjsg }
3516fb4d8502Sjsg
3517fb4d8502Sjsg for (se = 0; se < num_se; se++) {
3518fb4d8502Sjsg unsigned raster_config_se = raster_config;
3519fb4d8502Sjsg unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3520fb4d8502Sjsg unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3521fb4d8502Sjsg int idx = (se / 2) * 2;
3522fb4d8502Sjsg
3523fb4d8502Sjsg if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3524fb4d8502Sjsg raster_config_se &= ~SE_MAP_MASK;
3525fb4d8502Sjsg
3526fb4d8502Sjsg if (!se_mask[idx]) {
3527fb4d8502Sjsg raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3528fb4d8502Sjsg } else {
3529fb4d8502Sjsg raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3530fb4d8502Sjsg }
3531fb4d8502Sjsg }
3532fb4d8502Sjsg
3533fb4d8502Sjsg pkr0_mask &= rb_mask;
3534fb4d8502Sjsg pkr1_mask &= rb_mask;
3535fb4d8502Sjsg if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3536fb4d8502Sjsg raster_config_se &= ~PKR_MAP_MASK;
3537fb4d8502Sjsg
3538fb4d8502Sjsg if (!pkr0_mask) {
3539fb4d8502Sjsg raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3540fb4d8502Sjsg } else {
3541fb4d8502Sjsg raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3542fb4d8502Sjsg }
3543fb4d8502Sjsg }
3544fb4d8502Sjsg
3545fb4d8502Sjsg if (rb_per_se >= 2) {
3546fb4d8502Sjsg unsigned rb0_mask = 1 << (se * rb_per_se);
3547fb4d8502Sjsg unsigned rb1_mask = rb0_mask << 1;
3548fb4d8502Sjsg
3549fb4d8502Sjsg rb0_mask &= rb_mask;
3550fb4d8502Sjsg rb1_mask &= rb_mask;
3551fb4d8502Sjsg if (!rb0_mask || !rb1_mask) {
3552fb4d8502Sjsg raster_config_se &= ~RB_MAP_PKR0_MASK;
3553fb4d8502Sjsg
3554fb4d8502Sjsg if (!rb0_mask) {
3555fb4d8502Sjsg raster_config_se |=
3556fb4d8502Sjsg RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3557fb4d8502Sjsg } else {
3558fb4d8502Sjsg raster_config_se |=
3559fb4d8502Sjsg RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3560fb4d8502Sjsg }
3561fb4d8502Sjsg }
3562fb4d8502Sjsg
3563fb4d8502Sjsg if (rb_per_se > 2) {
3564fb4d8502Sjsg rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3565fb4d8502Sjsg rb1_mask = rb0_mask << 1;
3566fb4d8502Sjsg rb0_mask &= rb_mask;
3567fb4d8502Sjsg rb1_mask &= rb_mask;
3568fb4d8502Sjsg if (!rb0_mask || !rb1_mask) {
3569fb4d8502Sjsg raster_config_se &= ~RB_MAP_PKR1_MASK;
3570fb4d8502Sjsg
3571fb4d8502Sjsg if (!rb0_mask) {
3572fb4d8502Sjsg raster_config_se |=
3573fb4d8502Sjsg RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3574fb4d8502Sjsg } else {
3575fb4d8502Sjsg raster_config_se |=
3576fb4d8502Sjsg RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3577fb4d8502Sjsg }
3578fb4d8502Sjsg }
3579fb4d8502Sjsg }
3580fb4d8502Sjsg }
3581fb4d8502Sjsg
3582fb4d8502Sjsg /* GRBM_GFX_INDEX has a different offset on VI */
3583*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);
3584fb4d8502Sjsg WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3585fb4d8502Sjsg WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3586fb4d8502Sjsg }
3587fb4d8502Sjsg
3588fb4d8502Sjsg /* GRBM_GFX_INDEX has a different offset on VI */
3589*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3590fb4d8502Sjsg }
3591fb4d8502Sjsg
gfx_v8_0_setup_rb(struct amdgpu_device * adev)3592fb4d8502Sjsg static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3593fb4d8502Sjsg {
3594fb4d8502Sjsg int i, j;
3595fb4d8502Sjsg u32 data;
3596fb4d8502Sjsg u32 raster_config = 0, raster_config_1 = 0;
3597fb4d8502Sjsg u32 active_rbs = 0;
3598fb4d8502Sjsg u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3599fb4d8502Sjsg adev->gfx.config.max_sh_per_se;
3600fb4d8502Sjsg unsigned num_rb_pipes;
3601fb4d8502Sjsg
3602fb4d8502Sjsg mutex_lock(&adev->grbm_idx_mutex);
3603fb4d8502Sjsg for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3604fb4d8502Sjsg for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3605*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3606fb4d8502Sjsg data = gfx_v8_0_get_rb_active_bitmap(adev);
3607fb4d8502Sjsg active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3608fb4d8502Sjsg rb_bitmap_width_per_sh);
3609fb4d8502Sjsg }
3610fb4d8502Sjsg }
3611*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3612fb4d8502Sjsg
3613fb4d8502Sjsg adev->gfx.config.backend_enable_mask = active_rbs;
3614fb4d8502Sjsg adev->gfx.config.num_rbs = hweight32(active_rbs);
3615fb4d8502Sjsg
3616fb4d8502Sjsg num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3617fb4d8502Sjsg adev->gfx.config.max_shader_engines, 16);
3618fb4d8502Sjsg
3619fb4d8502Sjsg gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3620fb4d8502Sjsg
3621fb4d8502Sjsg if (!adev->gfx.config.backend_enable_mask ||
3622fb4d8502Sjsg adev->gfx.config.num_rbs >= num_rb_pipes) {
3623fb4d8502Sjsg WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3624fb4d8502Sjsg WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3625fb4d8502Sjsg } else {
3626fb4d8502Sjsg gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3627fb4d8502Sjsg adev->gfx.config.backend_enable_mask,
3628fb4d8502Sjsg num_rb_pipes);
3629fb4d8502Sjsg }
3630fb4d8502Sjsg
3631fb4d8502Sjsg /* cache the values for userspace */
3632fb4d8502Sjsg for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3633fb4d8502Sjsg for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3634*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3635fb4d8502Sjsg adev->gfx.config.rb_config[i][j].rb_backend_disable =
3636fb4d8502Sjsg RREG32(mmCC_RB_BACKEND_DISABLE);
3637fb4d8502Sjsg adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3638fb4d8502Sjsg RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3639fb4d8502Sjsg adev->gfx.config.rb_config[i][j].raster_config =
3640fb4d8502Sjsg RREG32(mmPA_SC_RASTER_CONFIG);
3641fb4d8502Sjsg adev->gfx.config.rb_config[i][j].raster_config_1 =
3642fb4d8502Sjsg RREG32(mmPA_SC_RASTER_CONFIG_1);
3643fb4d8502Sjsg }
3644fb4d8502Sjsg }
3645*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3646fb4d8502Sjsg mutex_unlock(&adev->grbm_idx_mutex);
3647fb4d8502Sjsg }
3648fb4d8502Sjsg
36495ca02815Sjsg #define DEFAULT_SH_MEM_BASES (0x6000)
3650fb4d8502Sjsg /**
3651fb4d8502Sjsg * gfx_v8_0_init_compute_vmid - gart enable
3652fb4d8502Sjsg *
3653fb4d8502Sjsg * @adev: amdgpu_device pointer
3654fb4d8502Sjsg *
3655fb4d8502Sjsg * Initialize compute vmid sh_mem registers
3656fb4d8502Sjsg *
3657fb4d8502Sjsg */
gfx_v8_0_init_compute_vmid(struct amdgpu_device * adev)3658fb4d8502Sjsg static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3659fb4d8502Sjsg {
3660fb4d8502Sjsg int i;
3661fb4d8502Sjsg uint32_t sh_mem_config;
3662fb4d8502Sjsg uint32_t sh_mem_bases;
3663fb4d8502Sjsg
3664fb4d8502Sjsg /*
3665fb4d8502Sjsg * Configure apertures:
3666fb4d8502Sjsg * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3667fb4d8502Sjsg * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3668fb4d8502Sjsg * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3669fb4d8502Sjsg */
3670fb4d8502Sjsg sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3671fb4d8502Sjsg
3672fb4d8502Sjsg sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3673fb4d8502Sjsg SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3674fb4d8502Sjsg SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3675fb4d8502Sjsg SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3676fb4d8502Sjsg MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3677fb4d8502Sjsg SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3678fb4d8502Sjsg
3679fb4d8502Sjsg mutex_lock(&adev->srbm_mutex);
3680ad8b1aafSjsg for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3681fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, i);
3682fb4d8502Sjsg /* CP and shaders */
3683fb4d8502Sjsg WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3684fb4d8502Sjsg WREG32(mmSH_MEM_APE1_BASE, 1);
3685fb4d8502Sjsg WREG32(mmSH_MEM_APE1_LIMIT, 0);
3686fb4d8502Sjsg WREG32(mmSH_MEM_BASES, sh_mem_bases);
3687fb4d8502Sjsg }
3688fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, 0);
3689fb4d8502Sjsg mutex_unlock(&adev->srbm_mutex);
3690c349dbc7Sjsg
3691c349dbc7Sjsg /* Initialize all compute VMIDs to have no GDS, GWS, or OA
36921bb76ff1Sjsg access. These should be enabled by FW for target VMIDs. */
3693ad8b1aafSjsg for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3694c349dbc7Sjsg WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
3695c349dbc7Sjsg WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
3696c349dbc7Sjsg WREG32(amdgpu_gds_reg_offset[i].gws, 0);
3697c349dbc7Sjsg WREG32(amdgpu_gds_reg_offset[i].oa, 0);
3698c349dbc7Sjsg }
3699c349dbc7Sjsg }
3700c349dbc7Sjsg
gfx_v8_0_init_gds_vmid(struct amdgpu_device * adev)3701c349dbc7Sjsg static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
3702c349dbc7Sjsg {
3703c349dbc7Sjsg int vmid;
3704c349dbc7Sjsg
3705c349dbc7Sjsg /*
3706c349dbc7Sjsg * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
3707c349dbc7Sjsg * access. Compute VMIDs should be enabled by FW for target VMIDs,
3708c349dbc7Sjsg * the driver can enable them for graphics. VMID0 should maintain
3709c349dbc7Sjsg * access so that HWS firmware can save/restore entries.
3710c349dbc7Sjsg */
37115ca02815Sjsg for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
3712c349dbc7Sjsg WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
3713c349dbc7Sjsg WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
3714c349dbc7Sjsg WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
3715c349dbc7Sjsg WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
3716c349dbc7Sjsg }
3717fb4d8502Sjsg }
3718fb4d8502Sjsg
gfx_v8_0_config_init(struct amdgpu_device * adev)3719fb4d8502Sjsg static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3720fb4d8502Sjsg {
3721fb4d8502Sjsg switch (adev->asic_type) {
3722fb4d8502Sjsg default:
3723fb4d8502Sjsg adev->gfx.config.double_offchip_lds_buf = 1;
3724fb4d8502Sjsg break;
3725fb4d8502Sjsg case CHIP_CARRIZO:
3726fb4d8502Sjsg case CHIP_STONEY:
3727fb4d8502Sjsg adev->gfx.config.double_offchip_lds_buf = 0;
3728fb4d8502Sjsg break;
3729fb4d8502Sjsg }
3730fb4d8502Sjsg }
3731fb4d8502Sjsg
gfx_v8_0_constants_init(struct amdgpu_device * adev)3732c349dbc7Sjsg static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
3733fb4d8502Sjsg {
3734fb4d8502Sjsg u32 tmp, sh_static_mem_cfg;
3735fb4d8502Sjsg int i;
3736fb4d8502Sjsg
3737fb4d8502Sjsg WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3738fb4d8502Sjsg WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3739fb4d8502Sjsg WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3740fb4d8502Sjsg WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3741fb4d8502Sjsg
3742fb4d8502Sjsg gfx_v8_0_tiling_mode_table_init(adev);
3743fb4d8502Sjsg gfx_v8_0_setup_rb(adev);
3744fb4d8502Sjsg gfx_v8_0_get_cu_info(adev);
3745fb4d8502Sjsg gfx_v8_0_config_init(adev);
3746fb4d8502Sjsg
3747fb4d8502Sjsg /* XXX SH_MEM regs */
3748fb4d8502Sjsg /* where to put LDS, scratch, GPUVM in FSA64 space */
3749fb4d8502Sjsg sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3750fb4d8502Sjsg SWIZZLE_ENABLE, 1);
3751fb4d8502Sjsg sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3752fb4d8502Sjsg ELEMENT_SIZE, 1);
3753fb4d8502Sjsg sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3754fb4d8502Sjsg INDEX_STRIDE, 3);
3755fb4d8502Sjsg WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3756fb4d8502Sjsg
3757fb4d8502Sjsg mutex_lock(&adev->srbm_mutex);
3758fb4d8502Sjsg for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3759fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, i);
3760fb4d8502Sjsg /* CP and shaders */
3761fb4d8502Sjsg if (i == 0) {
3762fb4d8502Sjsg tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3763fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3764fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3765fb4d8502Sjsg SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3766fb4d8502Sjsg WREG32(mmSH_MEM_CONFIG, tmp);
3767fb4d8502Sjsg WREG32(mmSH_MEM_BASES, 0);
3768fb4d8502Sjsg } else {
3769fb4d8502Sjsg tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3770fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3771fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3772fb4d8502Sjsg SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3773fb4d8502Sjsg WREG32(mmSH_MEM_CONFIG, tmp);
3774fb4d8502Sjsg tmp = adev->gmc.shared_aperture_start >> 48;
3775fb4d8502Sjsg WREG32(mmSH_MEM_BASES, tmp);
3776fb4d8502Sjsg }
3777fb4d8502Sjsg
3778fb4d8502Sjsg WREG32(mmSH_MEM_APE1_BASE, 1);
3779fb4d8502Sjsg WREG32(mmSH_MEM_APE1_LIMIT, 0);
3780fb4d8502Sjsg }
3781fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, 0);
3782fb4d8502Sjsg mutex_unlock(&adev->srbm_mutex);
3783fb4d8502Sjsg
3784fb4d8502Sjsg gfx_v8_0_init_compute_vmid(adev);
3785c349dbc7Sjsg gfx_v8_0_init_gds_vmid(adev);
3786fb4d8502Sjsg
3787fb4d8502Sjsg mutex_lock(&adev->grbm_idx_mutex);
3788fb4d8502Sjsg /*
3789fb4d8502Sjsg * making sure that the following register writes will be broadcasted
3790fb4d8502Sjsg * to all the shaders
3791fb4d8502Sjsg */
3792*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3793fb4d8502Sjsg
3794fb4d8502Sjsg WREG32(mmPA_SC_FIFO_SIZE,
3795fb4d8502Sjsg (adev->gfx.config.sc_prim_fifo_size_frontend <<
3796fb4d8502Sjsg PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3797fb4d8502Sjsg (adev->gfx.config.sc_prim_fifo_size_backend <<
3798fb4d8502Sjsg PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3799fb4d8502Sjsg (adev->gfx.config.sc_hiz_tile_fifo_size <<
3800fb4d8502Sjsg PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3801fb4d8502Sjsg (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3802fb4d8502Sjsg PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3803fb4d8502Sjsg
3804fb4d8502Sjsg tmp = RREG32(mmSPI_ARB_PRIORITY);
3805fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3806fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3807fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3808fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3809fb4d8502Sjsg WREG32(mmSPI_ARB_PRIORITY, tmp);
3810fb4d8502Sjsg
3811fb4d8502Sjsg mutex_unlock(&adev->grbm_idx_mutex);
3812fb4d8502Sjsg
3813fb4d8502Sjsg }
3814fb4d8502Sjsg
gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device * adev)3815fb4d8502Sjsg static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3816fb4d8502Sjsg {
3817fb4d8502Sjsg u32 i, j, k;
3818fb4d8502Sjsg u32 mask;
3819fb4d8502Sjsg
3820fb4d8502Sjsg mutex_lock(&adev->grbm_idx_mutex);
3821fb4d8502Sjsg for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3822fb4d8502Sjsg for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3823*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3824fb4d8502Sjsg for (k = 0; k < adev->usec_timeout; k++) {
3825fb4d8502Sjsg if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3826fb4d8502Sjsg break;
3827fb4d8502Sjsg udelay(1);
3828fb4d8502Sjsg }
3829fb4d8502Sjsg if (k == adev->usec_timeout) {
3830fb4d8502Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff,
3831*f005ef32Sjsg 0xffffffff, 0xffffffff, 0);
3832fb4d8502Sjsg mutex_unlock(&adev->grbm_idx_mutex);
3833fb4d8502Sjsg DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3834fb4d8502Sjsg i, j);
3835fb4d8502Sjsg return;
3836fb4d8502Sjsg }
3837fb4d8502Sjsg }
3838fb4d8502Sjsg }
3839*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3840fb4d8502Sjsg mutex_unlock(&adev->grbm_idx_mutex);
3841fb4d8502Sjsg
3842fb4d8502Sjsg mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3843fb4d8502Sjsg RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3844fb4d8502Sjsg RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3845fb4d8502Sjsg RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3846fb4d8502Sjsg for (k = 0; k < adev->usec_timeout; k++) {
3847fb4d8502Sjsg if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3848fb4d8502Sjsg break;
3849fb4d8502Sjsg udelay(1);
3850fb4d8502Sjsg }
3851fb4d8502Sjsg }
3852fb4d8502Sjsg
gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)3853fb4d8502Sjsg static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3854fb4d8502Sjsg bool enable)
3855fb4d8502Sjsg {
3856fb4d8502Sjsg u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3857fb4d8502Sjsg
3858fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3859fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3860fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3861fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3862fb4d8502Sjsg
3863fb4d8502Sjsg WREG32(mmCP_INT_CNTL_RING0, tmp);
3864fb4d8502Sjsg }
3865fb4d8502Sjsg
gfx_v8_0_init_csb(struct amdgpu_device * adev)3866fb4d8502Sjsg static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3867fb4d8502Sjsg {
3868c349dbc7Sjsg adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
3869fb4d8502Sjsg /* csib */
3870fb4d8502Sjsg WREG32(mmRLC_CSIB_ADDR_HI,
3871fb4d8502Sjsg adev->gfx.rlc.clear_state_gpu_addr >> 32);
3872fb4d8502Sjsg WREG32(mmRLC_CSIB_ADDR_LO,
3873fb4d8502Sjsg adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3874fb4d8502Sjsg WREG32(mmRLC_CSIB_LENGTH,
3875fb4d8502Sjsg adev->gfx.rlc.clear_state_size);
3876fb4d8502Sjsg }
3877fb4d8502Sjsg
gfx_v8_0_parse_ind_reg_list(int * register_list_format,int ind_offset,int list_size,int * unique_indices,int * indices_count,int max_indices,int * ind_start_offsets,int * offset_count,int max_offset)3878fb4d8502Sjsg static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3879fb4d8502Sjsg int ind_offset,
3880fb4d8502Sjsg int list_size,
3881fb4d8502Sjsg int *unique_indices,
3882fb4d8502Sjsg int *indices_count,
3883fb4d8502Sjsg int max_indices,
3884fb4d8502Sjsg int *ind_start_offsets,
3885fb4d8502Sjsg int *offset_count,
3886fb4d8502Sjsg int max_offset)
3887fb4d8502Sjsg {
3888fb4d8502Sjsg int indices;
3889fb4d8502Sjsg bool new_entry = true;
3890fb4d8502Sjsg
3891fb4d8502Sjsg for (; ind_offset < list_size; ind_offset++) {
3892fb4d8502Sjsg
3893fb4d8502Sjsg if (new_entry) {
3894fb4d8502Sjsg new_entry = false;
3895fb4d8502Sjsg ind_start_offsets[*offset_count] = ind_offset;
3896fb4d8502Sjsg *offset_count = *offset_count + 1;
3897fb4d8502Sjsg BUG_ON(*offset_count >= max_offset);
3898fb4d8502Sjsg }
3899fb4d8502Sjsg
3900fb4d8502Sjsg if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3901fb4d8502Sjsg new_entry = true;
3902fb4d8502Sjsg continue;
3903fb4d8502Sjsg }
3904fb4d8502Sjsg
3905fb4d8502Sjsg ind_offset += 2;
3906fb4d8502Sjsg
3907fb4d8502Sjsg /* look for the matching indice */
3908fb4d8502Sjsg for (indices = 0;
3909fb4d8502Sjsg indices < *indices_count;
3910fb4d8502Sjsg indices++) {
3911fb4d8502Sjsg if (unique_indices[indices] ==
3912fb4d8502Sjsg register_list_format[ind_offset])
3913fb4d8502Sjsg break;
3914fb4d8502Sjsg }
3915fb4d8502Sjsg
3916fb4d8502Sjsg if (indices >= *indices_count) {
3917fb4d8502Sjsg unique_indices[*indices_count] =
3918fb4d8502Sjsg register_list_format[ind_offset];
3919fb4d8502Sjsg indices = *indices_count;
3920fb4d8502Sjsg *indices_count = *indices_count + 1;
3921fb4d8502Sjsg BUG_ON(*indices_count >= max_indices);
3922fb4d8502Sjsg }
3923fb4d8502Sjsg
3924fb4d8502Sjsg register_list_format[ind_offset] = indices;
3925fb4d8502Sjsg }
3926fb4d8502Sjsg }
3927fb4d8502Sjsg
gfx_v8_0_init_save_restore_list(struct amdgpu_device * adev)3928fb4d8502Sjsg static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3929fb4d8502Sjsg {
3930fb4d8502Sjsg int i, temp, data;
3931fb4d8502Sjsg int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3932fb4d8502Sjsg int indices_count = 0;
3933fb4d8502Sjsg int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3934fb4d8502Sjsg int offset_count = 0;
3935fb4d8502Sjsg
3936fb4d8502Sjsg int list_size;
3937fb4d8502Sjsg unsigned int *register_list_format =
3938c349dbc7Sjsg kmemdup(adev->gfx.rlc.register_list_format,
3939c349dbc7Sjsg adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3940fb4d8502Sjsg if (!register_list_format)
3941fb4d8502Sjsg return -ENOMEM;
3942fb4d8502Sjsg
3943fb4d8502Sjsg gfx_v8_0_parse_ind_reg_list(register_list_format,
3944fb4d8502Sjsg RLC_FormatDirectRegListLength,
3945fb4d8502Sjsg adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3946fb4d8502Sjsg unique_indices,
3947fb4d8502Sjsg &indices_count,
3948fb4d8502Sjsg ARRAY_SIZE(unique_indices),
3949fb4d8502Sjsg indirect_start_offsets,
3950fb4d8502Sjsg &offset_count,
3951fb4d8502Sjsg ARRAY_SIZE(indirect_start_offsets));
3952fb4d8502Sjsg
3953fb4d8502Sjsg /* save and restore list */
3954fb4d8502Sjsg WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3955fb4d8502Sjsg
3956fb4d8502Sjsg WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3957fb4d8502Sjsg for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3958fb4d8502Sjsg WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3959fb4d8502Sjsg
3960fb4d8502Sjsg /* indirect list */
3961fb4d8502Sjsg WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3962fb4d8502Sjsg for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3963fb4d8502Sjsg WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3964fb4d8502Sjsg
3965fb4d8502Sjsg list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3966fb4d8502Sjsg list_size = list_size >> 1;
3967fb4d8502Sjsg WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3968fb4d8502Sjsg WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3969fb4d8502Sjsg
3970fb4d8502Sjsg /* starting offsets starts */
3971fb4d8502Sjsg WREG32(mmRLC_GPM_SCRATCH_ADDR,
3972fb4d8502Sjsg adev->gfx.rlc.starting_offsets_start);
3973fb4d8502Sjsg for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
3974fb4d8502Sjsg WREG32(mmRLC_GPM_SCRATCH_DATA,
3975fb4d8502Sjsg indirect_start_offsets[i]);
3976fb4d8502Sjsg
3977fb4d8502Sjsg /* unique indices */
3978fb4d8502Sjsg temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
3979fb4d8502Sjsg data = mmRLC_SRM_INDEX_CNTL_DATA_0;
3980fb4d8502Sjsg for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
3981fb4d8502Sjsg if (unique_indices[i] != 0) {
3982fb4d8502Sjsg WREG32(temp + i, unique_indices[i] & 0x3FFFF);
3983fb4d8502Sjsg WREG32(data + i, unique_indices[i] >> 20);
3984fb4d8502Sjsg }
3985fb4d8502Sjsg }
3986fb4d8502Sjsg kfree(register_list_format);
3987fb4d8502Sjsg
3988fb4d8502Sjsg return 0;
3989fb4d8502Sjsg }
3990fb4d8502Sjsg
gfx_v8_0_enable_save_restore_machine(struct amdgpu_device * adev)3991fb4d8502Sjsg static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
3992fb4d8502Sjsg {
3993fb4d8502Sjsg WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
3994fb4d8502Sjsg }
3995fb4d8502Sjsg
gfx_v8_0_init_power_gating(struct amdgpu_device * adev)3996fb4d8502Sjsg static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
3997fb4d8502Sjsg {
3998fb4d8502Sjsg uint32_t data;
3999fb4d8502Sjsg
4000fb4d8502Sjsg WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
4001fb4d8502Sjsg
4002fb4d8502Sjsg data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
4003fb4d8502Sjsg data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
4004fb4d8502Sjsg data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
4005fb4d8502Sjsg data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
4006fb4d8502Sjsg WREG32(mmRLC_PG_DELAY, data);
4007fb4d8502Sjsg
4008fb4d8502Sjsg WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4009fb4d8502Sjsg WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4010fb4d8502Sjsg
4011fb4d8502Sjsg }
4012fb4d8502Sjsg
cz_enable_sck_slow_down_on_power_up(struct amdgpu_device * adev,bool enable)4013fb4d8502Sjsg static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
4014fb4d8502Sjsg bool enable)
4015fb4d8502Sjsg {
4016fb4d8502Sjsg WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4017fb4d8502Sjsg }
4018fb4d8502Sjsg
cz_enable_sck_slow_down_on_power_down(struct amdgpu_device * adev,bool enable)4019fb4d8502Sjsg static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
4020fb4d8502Sjsg bool enable)
4021fb4d8502Sjsg {
4022fb4d8502Sjsg WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4023fb4d8502Sjsg }
4024fb4d8502Sjsg
cz_enable_cp_power_gating(struct amdgpu_device * adev,bool enable)4025fb4d8502Sjsg static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
4026fb4d8502Sjsg {
4027fb4d8502Sjsg WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4028fb4d8502Sjsg }
4029fb4d8502Sjsg
gfx_v8_0_init_pg(struct amdgpu_device * adev)4030fb4d8502Sjsg static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4031fb4d8502Sjsg {
4032fb4d8502Sjsg if ((adev->asic_type == CHIP_CARRIZO) ||
4033fb4d8502Sjsg (adev->asic_type == CHIP_STONEY)) {
4034fb4d8502Sjsg gfx_v8_0_init_csb(adev);
4035fb4d8502Sjsg gfx_v8_0_init_save_restore_list(adev);
4036fb4d8502Sjsg gfx_v8_0_enable_save_restore_machine(adev);
4037fb4d8502Sjsg WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4038fb4d8502Sjsg gfx_v8_0_init_power_gating(adev);
4039fb4d8502Sjsg WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4040fb4d8502Sjsg } else if ((adev->asic_type == CHIP_POLARIS11) ||
4041fb4d8502Sjsg (adev->asic_type == CHIP_POLARIS12) ||
4042fb4d8502Sjsg (adev->asic_type == CHIP_VEGAM)) {
4043fb4d8502Sjsg gfx_v8_0_init_csb(adev);
4044fb4d8502Sjsg gfx_v8_0_init_save_restore_list(adev);
4045fb4d8502Sjsg gfx_v8_0_enable_save_restore_machine(adev);
4046fb4d8502Sjsg gfx_v8_0_init_power_gating(adev);
4047fb4d8502Sjsg }
4048fb4d8502Sjsg
4049fb4d8502Sjsg }
4050fb4d8502Sjsg
gfx_v8_0_rlc_stop(struct amdgpu_device * adev)4051fb4d8502Sjsg static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
4052fb4d8502Sjsg {
4053fb4d8502Sjsg WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4054fb4d8502Sjsg
4055fb4d8502Sjsg gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4056fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
4057fb4d8502Sjsg }
4058fb4d8502Sjsg
gfx_v8_0_rlc_reset(struct amdgpu_device * adev)4059fb4d8502Sjsg static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4060fb4d8502Sjsg {
4061fb4d8502Sjsg WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4062fb4d8502Sjsg udelay(50);
4063fb4d8502Sjsg
4064fb4d8502Sjsg WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4065fb4d8502Sjsg udelay(50);
4066fb4d8502Sjsg }
4067fb4d8502Sjsg
gfx_v8_0_rlc_start(struct amdgpu_device * adev)4068fb4d8502Sjsg static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4069fb4d8502Sjsg {
4070fb4d8502Sjsg WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
4071fb4d8502Sjsg
4072fb4d8502Sjsg /* carrizo do enable cp interrupt after cp inited */
4073fb4d8502Sjsg if (!(adev->flags & AMD_IS_APU))
4074fb4d8502Sjsg gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4075fb4d8502Sjsg
4076fb4d8502Sjsg udelay(50);
4077fb4d8502Sjsg }
4078fb4d8502Sjsg
gfx_v8_0_rlc_resume(struct amdgpu_device * adev)4079c349dbc7Sjsg static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4080fb4d8502Sjsg {
4081c349dbc7Sjsg if (amdgpu_sriov_vf(adev)) {
4082c349dbc7Sjsg gfx_v8_0_init_csb(adev);
4083fb4d8502Sjsg return 0;
4084fb4d8502Sjsg }
4085fb4d8502Sjsg
4086c349dbc7Sjsg adev->gfx.rlc.funcs->stop(adev);
4087c349dbc7Sjsg adev->gfx.rlc.funcs->reset(adev);
4088fb4d8502Sjsg gfx_v8_0_init_pg(adev);
4089c349dbc7Sjsg adev->gfx.rlc.funcs->start(adev);
4090fb4d8502Sjsg
4091fb4d8502Sjsg return 0;
4092fb4d8502Sjsg }
4093fb4d8502Sjsg
gfx_v8_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)4094fb4d8502Sjsg static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4095fb4d8502Sjsg {
4096fb4d8502Sjsg u32 tmp = RREG32(mmCP_ME_CNTL);
4097fb4d8502Sjsg
4098fb4d8502Sjsg if (enable) {
4099fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4100fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4101fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4102fb4d8502Sjsg } else {
4103fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4104fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4105fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4106fb4d8502Sjsg }
4107fb4d8502Sjsg WREG32(mmCP_ME_CNTL, tmp);
4108fb4d8502Sjsg udelay(50);
4109fb4d8502Sjsg }
4110fb4d8502Sjsg
gfx_v8_0_get_csb_size(struct amdgpu_device * adev)4111fb4d8502Sjsg static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4112fb4d8502Sjsg {
4113fb4d8502Sjsg u32 count = 0;
4114fb4d8502Sjsg const struct cs_section_def *sect = NULL;
4115fb4d8502Sjsg const struct cs_extent_def *ext = NULL;
4116fb4d8502Sjsg
4117fb4d8502Sjsg /* begin clear state */
4118fb4d8502Sjsg count += 2;
4119fb4d8502Sjsg /* context control state */
4120fb4d8502Sjsg count += 3;
4121fb4d8502Sjsg
4122fb4d8502Sjsg for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4123fb4d8502Sjsg for (ext = sect->section; ext->extent != NULL; ++ext) {
4124fb4d8502Sjsg if (sect->id == SECT_CONTEXT)
4125fb4d8502Sjsg count += 2 + ext->reg_count;
4126fb4d8502Sjsg else
4127fb4d8502Sjsg return 0;
4128fb4d8502Sjsg }
4129fb4d8502Sjsg }
4130fb4d8502Sjsg /* pa_sc_raster_config/pa_sc_raster_config1 */
4131fb4d8502Sjsg count += 4;
4132fb4d8502Sjsg /* end clear state */
4133fb4d8502Sjsg count += 2;
4134fb4d8502Sjsg /* clear state */
4135fb4d8502Sjsg count += 2;
4136fb4d8502Sjsg
4137fb4d8502Sjsg return count;
4138fb4d8502Sjsg }
4139fb4d8502Sjsg
gfx_v8_0_cp_gfx_start(struct amdgpu_device * adev)4140fb4d8502Sjsg static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4141fb4d8502Sjsg {
4142fb4d8502Sjsg struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4143fb4d8502Sjsg const struct cs_section_def *sect = NULL;
4144fb4d8502Sjsg const struct cs_extent_def *ext = NULL;
4145fb4d8502Sjsg int r, i;
4146fb4d8502Sjsg
4147fb4d8502Sjsg /* init the CP */
4148fb4d8502Sjsg WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4149fb4d8502Sjsg WREG32(mmCP_ENDIAN_SWAP, 0);
4150fb4d8502Sjsg WREG32(mmCP_DEVICE_ID, 1);
4151fb4d8502Sjsg
4152fb4d8502Sjsg gfx_v8_0_cp_gfx_enable(adev, true);
4153fb4d8502Sjsg
4154fb4d8502Sjsg r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
4155fb4d8502Sjsg if (r) {
4156fb4d8502Sjsg DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4157fb4d8502Sjsg return r;
4158fb4d8502Sjsg }
4159fb4d8502Sjsg
4160fb4d8502Sjsg /* clear state buffer */
4161fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4162fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4163fb4d8502Sjsg
4164fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4165fb4d8502Sjsg amdgpu_ring_write(ring, 0x80000000);
4166fb4d8502Sjsg amdgpu_ring_write(ring, 0x80000000);
4167fb4d8502Sjsg
4168fb4d8502Sjsg for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4169fb4d8502Sjsg for (ext = sect->section; ext->extent != NULL; ++ext) {
4170fb4d8502Sjsg if (sect->id == SECT_CONTEXT) {
4171fb4d8502Sjsg amdgpu_ring_write(ring,
4172fb4d8502Sjsg PACKET3(PACKET3_SET_CONTEXT_REG,
4173fb4d8502Sjsg ext->reg_count));
4174fb4d8502Sjsg amdgpu_ring_write(ring,
4175fb4d8502Sjsg ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4176fb4d8502Sjsg for (i = 0; i < ext->reg_count; i++)
4177fb4d8502Sjsg amdgpu_ring_write(ring, ext->extent[i]);
4178fb4d8502Sjsg }
4179fb4d8502Sjsg }
4180fb4d8502Sjsg }
4181fb4d8502Sjsg
4182fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4183fb4d8502Sjsg amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4184fb4d8502Sjsg amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
4185fb4d8502Sjsg amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
4186fb4d8502Sjsg
4187fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4188fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4189fb4d8502Sjsg
4190fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4191fb4d8502Sjsg amdgpu_ring_write(ring, 0);
4192fb4d8502Sjsg
4193fb4d8502Sjsg /* init the CE partitions */
4194fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4195fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4196fb4d8502Sjsg amdgpu_ring_write(ring, 0x8000);
4197fb4d8502Sjsg amdgpu_ring_write(ring, 0x8000);
4198fb4d8502Sjsg
4199fb4d8502Sjsg amdgpu_ring_commit(ring);
4200fb4d8502Sjsg
4201fb4d8502Sjsg return 0;
4202fb4d8502Sjsg }
gfx_v8_0_set_cpg_door_bell(struct amdgpu_device * adev,struct amdgpu_ring * ring)4203fb4d8502Sjsg static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
4204fb4d8502Sjsg {
4205fb4d8502Sjsg u32 tmp;
4206fb4d8502Sjsg /* no gfx doorbells on iceland */
4207fb4d8502Sjsg if (adev->asic_type == CHIP_TOPAZ)
4208fb4d8502Sjsg return;
4209fb4d8502Sjsg
4210fb4d8502Sjsg tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4211fb4d8502Sjsg
4212fb4d8502Sjsg if (ring->use_doorbell) {
4213fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4214fb4d8502Sjsg DOORBELL_OFFSET, ring->doorbell_index);
4215fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4216fb4d8502Sjsg DOORBELL_HIT, 0);
4217fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4218fb4d8502Sjsg DOORBELL_EN, 1);
4219fb4d8502Sjsg } else {
4220fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
4221fb4d8502Sjsg }
4222fb4d8502Sjsg
4223fb4d8502Sjsg WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4224fb4d8502Sjsg
4225fb4d8502Sjsg if (adev->flags & AMD_IS_APU)
4226fb4d8502Sjsg return;
4227fb4d8502Sjsg
4228fb4d8502Sjsg tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4229fb4d8502Sjsg DOORBELL_RANGE_LOWER,
4230c349dbc7Sjsg adev->doorbell_index.gfx_ring0);
4231fb4d8502Sjsg WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4232fb4d8502Sjsg
4233fb4d8502Sjsg WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4234fb4d8502Sjsg CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4235fb4d8502Sjsg }
4236fb4d8502Sjsg
gfx_v8_0_cp_gfx_resume(struct amdgpu_device * adev)4237fb4d8502Sjsg static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4238fb4d8502Sjsg {
4239fb4d8502Sjsg struct amdgpu_ring *ring;
4240fb4d8502Sjsg u32 tmp;
4241fb4d8502Sjsg u32 rb_bufsz;
4242fb4d8502Sjsg u64 rb_addr, rptr_addr, wptr_gpu_addr;
4243fb4d8502Sjsg
4244fb4d8502Sjsg /* Set the write pointer delay */
4245fb4d8502Sjsg WREG32(mmCP_RB_WPTR_DELAY, 0);
4246fb4d8502Sjsg
4247fb4d8502Sjsg /* set the RB to use vmid 0 */
4248fb4d8502Sjsg WREG32(mmCP_RB_VMID, 0);
4249fb4d8502Sjsg
4250fb4d8502Sjsg /* Set ring buffer size */
4251fb4d8502Sjsg ring = &adev->gfx.gfx_ring[0];
4252fb4d8502Sjsg rb_bufsz = order_base_2(ring->ring_size / 8);
4253fb4d8502Sjsg tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4254fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4255fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4256fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4257fb4d8502Sjsg #ifdef __BIG_ENDIAN
4258fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4259fb4d8502Sjsg #endif
4260fb4d8502Sjsg WREG32(mmCP_RB0_CNTL, tmp);
4261fb4d8502Sjsg
4262fb4d8502Sjsg /* Initialize the ring buffer's read and write pointers */
4263fb4d8502Sjsg WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4264fb4d8502Sjsg ring->wptr = 0;
4265fb4d8502Sjsg WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4266fb4d8502Sjsg
4267fb4d8502Sjsg /* set the wb address wether it's enabled or not */
42681bb76ff1Sjsg rptr_addr = ring->rptr_gpu_addr;
4269fb4d8502Sjsg WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4270fb4d8502Sjsg WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4271fb4d8502Sjsg
42721bb76ff1Sjsg wptr_gpu_addr = ring->wptr_gpu_addr;
4273fb4d8502Sjsg WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4274fb4d8502Sjsg WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4275fb4d8502Sjsg mdelay(1);
4276fb4d8502Sjsg WREG32(mmCP_RB0_CNTL, tmp);
4277fb4d8502Sjsg
4278fb4d8502Sjsg rb_addr = ring->gpu_addr >> 8;
4279fb4d8502Sjsg WREG32(mmCP_RB0_BASE, rb_addr);
4280fb4d8502Sjsg WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4281fb4d8502Sjsg
4282fb4d8502Sjsg gfx_v8_0_set_cpg_door_bell(adev, ring);
4283fb4d8502Sjsg /* start the ring */
4284fb4d8502Sjsg amdgpu_ring_clear_ring(ring);
4285fb4d8502Sjsg gfx_v8_0_cp_gfx_start(adev);
4286fb4d8502Sjsg
4287c349dbc7Sjsg return 0;
4288fb4d8502Sjsg }
4289fb4d8502Sjsg
gfx_v8_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)4290fb4d8502Sjsg static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4291fb4d8502Sjsg {
4292fb4d8502Sjsg if (enable) {
4293fb4d8502Sjsg WREG32(mmCP_MEC_CNTL, 0);
4294fb4d8502Sjsg } else {
4295fb4d8502Sjsg WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4296*f005ef32Sjsg adev->gfx.kiq[0].ring.sched.ready = false;
4297fb4d8502Sjsg }
4298fb4d8502Sjsg udelay(50);
4299fb4d8502Sjsg }
4300fb4d8502Sjsg
4301fb4d8502Sjsg /* KIQ functions */
gfx_v8_0_kiq_setting(struct amdgpu_ring * ring)4302fb4d8502Sjsg static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
4303fb4d8502Sjsg {
4304fb4d8502Sjsg uint32_t tmp;
4305fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
4306fb4d8502Sjsg
4307fb4d8502Sjsg /* tell RLC which is KIQ queue */
4308fb4d8502Sjsg tmp = RREG32(mmRLC_CP_SCHEDULERS);
4309fb4d8502Sjsg tmp &= 0xffffff00;
4310fb4d8502Sjsg tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
4311fb4d8502Sjsg WREG32(mmRLC_CP_SCHEDULERS, tmp);
4312fb4d8502Sjsg tmp |= 0x80;
4313fb4d8502Sjsg WREG32(mmRLC_CP_SCHEDULERS, tmp);
4314fb4d8502Sjsg }
4315fb4d8502Sjsg
gfx_v8_0_kiq_kcq_enable(struct amdgpu_device * adev)4316fb4d8502Sjsg static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
4317fb4d8502Sjsg {
4318*f005ef32Sjsg struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
4319fb4d8502Sjsg uint64_t queue_mask = 0;
4320fb4d8502Sjsg int r, i;
4321fb4d8502Sjsg
4322fb4d8502Sjsg for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4323*f005ef32Sjsg if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap))
4324fb4d8502Sjsg continue;
4325fb4d8502Sjsg
4326fb4d8502Sjsg /* This situation may be hit in the future if a new HW
4327fb4d8502Sjsg * generation exposes more than 64 queues. If so, the
4328fb4d8502Sjsg * definition of queue_mask needs updating */
4329fb4d8502Sjsg if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
4330fb4d8502Sjsg DRM_ERROR("Invalid KCQ enabled: %d\n", i);
4331fb4d8502Sjsg break;
4332fb4d8502Sjsg }
4333fb4d8502Sjsg
4334fb4d8502Sjsg queue_mask |= (1ull << i);
4335fb4d8502Sjsg }
4336fb4d8502Sjsg
4337c349dbc7Sjsg r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
4338fb4d8502Sjsg if (r) {
4339fb4d8502Sjsg DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4340fb4d8502Sjsg return r;
4341fb4d8502Sjsg }
4342fb4d8502Sjsg /* set resources */
4343fb4d8502Sjsg amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4344fb4d8502Sjsg amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4345fb4d8502Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4346fb4d8502Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4347fb4d8502Sjsg amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4348fb4d8502Sjsg amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4349fb4d8502Sjsg amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4350fb4d8502Sjsg amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
4351fb4d8502Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4352fb4d8502Sjsg struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4353fb4d8502Sjsg uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
43541bb76ff1Sjsg uint64_t wptr_addr = ring->wptr_gpu_addr;
4355fb4d8502Sjsg
4356fb4d8502Sjsg /* map queues */
4357fb4d8502Sjsg amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
4358fb4d8502Sjsg /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
4359fb4d8502Sjsg amdgpu_ring_write(kiq_ring,
4360fb4d8502Sjsg PACKET3_MAP_QUEUES_NUM_QUEUES(1));
4361fb4d8502Sjsg amdgpu_ring_write(kiq_ring,
4362fb4d8502Sjsg PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) |
4363fb4d8502Sjsg PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
4364fb4d8502Sjsg PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
4365fb4d8502Sjsg PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */
4366fb4d8502Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
4367fb4d8502Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
4368fb4d8502Sjsg amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
4369fb4d8502Sjsg amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
4370fb4d8502Sjsg }
4371c349dbc7Sjsg
4372fb4d8502Sjsg amdgpu_ring_commit(kiq_ring);
4373fb4d8502Sjsg
4374c349dbc7Sjsg return 0;
4375fb4d8502Sjsg }
4376fb4d8502Sjsg
gfx_v8_0_deactivate_hqd(struct amdgpu_device * adev,u32 req)4377fb4d8502Sjsg static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
4378fb4d8502Sjsg {
4379fb4d8502Sjsg int i, r = 0;
4380fb4d8502Sjsg
4381fb4d8502Sjsg if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4382fb4d8502Sjsg WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
4383fb4d8502Sjsg for (i = 0; i < adev->usec_timeout; i++) {
4384fb4d8502Sjsg if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4385fb4d8502Sjsg break;
4386fb4d8502Sjsg udelay(1);
4387fb4d8502Sjsg }
4388fb4d8502Sjsg if (i == adev->usec_timeout)
4389fb4d8502Sjsg r = -ETIMEDOUT;
4390fb4d8502Sjsg }
4391fb4d8502Sjsg WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
4392fb4d8502Sjsg WREG32(mmCP_HQD_PQ_RPTR, 0);
4393fb4d8502Sjsg WREG32(mmCP_HQD_PQ_WPTR, 0);
4394fb4d8502Sjsg
4395fb4d8502Sjsg return r;
4396fb4d8502Sjsg }
4397fb4d8502Sjsg
gfx_v8_0_mqd_set_priority(struct amdgpu_ring * ring,struct vi_mqd * mqd)4398c349dbc7Sjsg static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd)
4399c349dbc7Sjsg {
4400c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
4401c349dbc7Sjsg
4402c349dbc7Sjsg if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
44035ca02815Sjsg if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
4404c349dbc7Sjsg mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
4405c349dbc7Sjsg mqd->cp_hqd_queue_priority =
4406c349dbc7Sjsg AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
4407c349dbc7Sjsg }
4408c349dbc7Sjsg }
4409c349dbc7Sjsg }
4410c349dbc7Sjsg
gfx_v8_0_mqd_init(struct amdgpu_ring * ring)4411fb4d8502Sjsg static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4412fb4d8502Sjsg {
4413fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
4414fb4d8502Sjsg struct vi_mqd *mqd = ring->mqd_ptr;
4415fb4d8502Sjsg uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4416fb4d8502Sjsg uint32_t tmp;
4417fb4d8502Sjsg
4418fb4d8502Sjsg mqd->header = 0xC0310800;
4419fb4d8502Sjsg mqd->compute_pipelinestat_enable = 0x00000001;
4420fb4d8502Sjsg mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4421fb4d8502Sjsg mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4422fb4d8502Sjsg mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4423fb4d8502Sjsg mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4424fb4d8502Sjsg mqd->compute_misc_reserved = 0x00000003;
4425fb4d8502Sjsg mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4426fb4d8502Sjsg + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4427fb4d8502Sjsg mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4428fb4d8502Sjsg + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4429fb4d8502Sjsg eop_base_addr = ring->eop_gpu_addr >> 8;
4430fb4d8502Sjsg mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4431fb4d8502Sjsg mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4432fb4d8502Sjsg
4433fb4d8502Sjsg /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4434fb4d8502Sjsg tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4435fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4436fb4d8502Sjsg (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1));
4437fb4d8502Sjsg
4438fb4d8502Sjsg mqd->cp_hqd_eop_control = tmp;
4439fb4d8502Sjsg
4440fb4d8502Sjsg /* enable doorbell? */
4441fb4d8502Sjsg tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
4442fb4d8502Sjsg CP_HQD_PQ_DOORBELL_CONTROL,
4443fb4d8502Sjsg DOORBELL_EN,
4444fb4d8502Sjsg ring->use_doorbell ? 1 : 0);
4445fb4d8502Sjsg
4446fb4d8502Sjsg mqd->cp_hqd_pq_doorbell_control = tmp;
4447fb4d8502Sjsg
4448fb4d8502Sjsg /* set the pointer to the MQD */
4449fb4d8502Sjsg mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4450fb4d8502Sjsg mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4451fb4d8502Sjsg
4452fb4d8502Sjsg /* set MQD vmid to 0 */
4453fb4d8502Sjsg tmp = RREG32(mmCP_MQD_CONTROL);
4454fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4455fb4d8502Sjsg mqd->cp_mqd_control = tmp;
4456fb4d8502Sjsg
4457fb4d8502Sjsg /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4458fb4d8502Sjsg hqd_gpu_addr = ring->gpu_addr >> 8;
4459fb4d8502Sjsg mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4460fb4d8502Sjsg mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4461fb4d8502Sjsg
4462fb4d8502Sjsg /* set up the HQD, this is similar to CP_RB0_CNTL */
4463fb4d8502Sjsg tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4464fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4465fb4d8502Sjsg (order_base_2(ring->ring_size / 4) - 1));
4466fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
44671bb76ff1Sjsg (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
4468fb4d8502Sjsg #ifdef __BIG_ENDIAN
4469fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4470fb4d8502Sjsg #endif
4471fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4472fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4473fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4474fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4475fb4d8502Sjsg mqd->cp_hqd_pq_control = tmp;
4476fb4d8502Sjsg
4477fb4d8502Sjsg /* set the wb address whether it's enabled or not */
44781bb76ff1Sjsg wb_gpu_addr = ring->rptr_gpu_addr;
4479fb4d8502Sjsg mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4480fb4d8502Sjsg mqd->cp_hqd_pq_rptr_report_addr_hi =
4481fb4d8502Sjsg upper_32_bits(wb_gpu_addr) & 0xffff;
4482fb4d8502Sjsg
4483fb4d8502Sjsg /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
44841bb76ff1Sjsg wb_gpu_addr = ring->wptr_gpu_addr;
4485fb4d8502Sjsg mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4486fb4d8502Sjsg mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4487fb4d8502Sjsg
4488fb4d8502Sjsg tmp = 0;
4489fb4d8502Sjsg /* enable the doorbell if requested */
4490fb4d8502Sjsg if (ring->use_doorbell) {
4491fb4d8502Sjsg tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4492fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4493fb4d8502Sjsg DOORBELL_OFFSET, ring->doorbell_index);
4494fb4d8502Sjsg
4495fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4496fb4d8502Sjsg DOORBELL_EN, 1);
4497fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4498fb4d8502Sjsg DOORBELL_SOURCE, 0);
4499fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4500fb4d8502Sjsg DOORBELL_HIT, 0);
4501fb4d8502Sjsg }
4502fb4d8502Sjsg
4503fb4d8502Sjsg mqd->cp_hqd_pq_doorbell_control = tmp;
4504fb4d8502Sjsg
4505fb4d8502Sjsg /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4506fb4d8502Sjsg ring->wptr = 0;
4507fb4d8502Sjsg mqd->cp_hqd_pq_wptr = ring->wptr;
4508fb4d8502Sjsg mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4509fb4d8502Sjsg
4510fb4d8502Sjsg /* set the vmid for the queue */
4511fb4d8502Sjsg mqd->cp_hqd_vmid = 0;
4512fb4d8502Sjsg
4513fb4d8502Sjsg tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4514fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4515fb4d8502Sjsg mqd->cp_hqd_persistent_state = tmp;
4516fb4d8502Sjsg
4517fb4d8502Sjsg /* set MTYPE */
4518fb4d8502Sjsg tmp = RREG32(mmCP_HQD_IB_CONTROL);
4519fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4520fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
4521fb4d8502Sjsg mqd->cp_hqd_ib_control = tmp;
4522fb4d8502Sjsg
4523fb4d8502Sjsg tmp = RREG32(mmCP_HQD_IQ_TIMER);
4524fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
4525fb4d8502Sjsg mqd->cp_hqd_iq_timer = tmp;
4526fb4d8502Sjsg
4527fb4d8502Sjsg tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
4528fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4529fb4d8502Sjsg mqd->cp_hqd_ctx_save_control = tmp;
4530fb4d8502Sjsg
4531fb4d8502Sjsg /* defaults */
4532fb4d8502Sjsg mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4533fb4d8502Sjsg mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4534fb4d8502Sjsg mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4535fb4d8502Sjsg mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4536fb4d8502Sjsg mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4537fb4d8502Sjsg mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4538fb4d8502Sjsg mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4539fb4d8502Sjsg mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4540fb4d8502Sjsg mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4541fb4d8502Sjsg mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4542fb4d8502Sjsg mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4543fb4d8502Sjsg mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4544fb4d8502Sjsg
4545c349dbc7Sjsg /* set static priority for a queue/ring */
4546c349dbc7Sjsg gfx_v8_0_mqd_set_priority(ring, mqd);
4547c349dbc7Sjsg mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4548c349dbc7Sjsg
4549c349dbc7Sjsg /* map_queues packet doesn't need activate the queue,
4550c349dbc7Sjsg * so only kiq need set this field.
4551c349dbc7Sjsg */
4552c349dbc7Sjsg if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
4553fb4d8502Sjsg mqd->cp_hqd_active = 1;
4554fb4d8502Sjsg
4555fb4d8502Sjsg return 0;
4556fb4d8502Sjsg }
4557fb4d8502Sjsg
gfx_v8_0_mqd_commit(struct amdgpu_device * adev,struct vi_mqd * mqd)4558ad8b1aafSjsg static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4559fb4d8502Sjsg struct vi_mqd *mqd)
4560fb4d8502Sjsg {
4561fb4d8502Sjsg uint32_t mqd_reg;
4562fb4d8502Sjsg uint32_t *mqd_data;
4563fb4d8502Sjsg
4564fb4d8502Sjsg /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4565fb4d8502Sjsg mqd_data = &mqd->cp_mqd_base_addr_lo;
4566fb4d8502Sjsg
4567fb4d8502Sjsg /* disable wptr polling */
4568fb4d8502Sjsg WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4569fb4d8502Sjsg
4570fb4d8502Sjsg /* program all HQD registers */
4571fb4d8502Sjsg for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
4572fb4d8502Sjsg WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4573fb4d8502Sjsg
4574fb4d8502Sjsg /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
4575fb4d8502Sjsg * This is safe since EOP RPTR==WPTR for any inactive HQD
4576fb4d8502Sjsg * on ASICs that do not support context-save.
4577fb4d8502Sjsg * EOP writes/reads can start anywhere in the ring.
4578fb4d8502Sjsg */
4579fb4d8502Sjsg if (adev->asic_type != CHIP_TONGA) {
4580fb4d8502Sjsg WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4581fb4d8502Sjsg WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4582fb4d8502Sjsg WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4583fb4d8502Sjsg }
4584fb4d8502Sjsg
4585fb4d8502Sjsg for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
4586fb4d8502Sjsg WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4587fb4d8502Sjsg
4588fb4d8502Sjsg /* activate the HQD */
4589fb4d8502Sjsg for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4590fb4d8502Sjsg WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4591fb4d8502Sjsg
4592fb4d8502Sjsg return 0;
4593fb4d8502Sjsg }
4594fb4d8502Sjsg
gfx_v8_0_kiq_init_queue(struct amdgpu_ring * ring)4595fb4d8502Sjsg static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4596fb4d8502Sjsg {
4597fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
4598fb4d8502Sjsg struct vi_mqd *mqd = ring->mqd_ptr;
4599fb4d8502Sjsg
4600fb4d8502Sjsg gfx_v8_0_kiq_setting(ring);
4601fb4d8502Sjsg
4602ad8b1aafSjsg if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4603fb4d8502Sjsg /* reset MQD to a clean status */
4604*f005ef32Sjsg if (adev->gfx.kiq[0].mqd_backup)
4605*f005ef32Sjsg memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation));
4606fb4d8502Sjsg
4607fb4d8502Sjsg /* reset ring buffer */
4608fb4d8502Sjsg ring->wptr = 0;
4609fb4d8502Sjsg amdgpu_ring_clear_ring(ring);
4610fb4d8502Sjsg mutex_lock(&adev->srbm_mutex);
4611fb4d8502Sjsg vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4612fb4d8502Sjsg gfx_v8_0_mqd_commit(adev, mqd);
4613fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, 0);
4614fb4d8502Sjsg mutex_unlock(&adev->srbm_mutex);
4615fb4d8502Sjsg } else {
4616fb4d8502Sjsg memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4617fb4d8502Sjsg ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4618fb4d8502Sjsg ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4619*f005ef32Sjsg if (amdgpu_sriov_vf(adev) && adev->in_suspend)
4620*f005ef32Sjsg amdgpu_ring_clear_ring(ring);
4621fb4d8502Sjsg mutex_lock(&adev->srbm_mutex);
4622fb4d8502Sjsg vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4623fb4d8502Sjsg gfx_v8_0_mqd_init(ring);
4624fb4d8502Sjsg gfx_v8_0_mqd_commit(adev, mqd);
4625fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, 0);
4626fb4d8502Sjsg mutex_unlock(&adev->srbm_mutex);
4627fb4d8502Sjsg
4628*f005ef32Sjsg if (adev->gfx.kiq[0].mqd_backup)
4629*f005ef32Sjsg memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation));
4630fb4d8502Sjsg }
4631fb4d8502Sjsg
4632fb4d8502Sjsg return 0;
4633fb4d8502Sjsg }
4634fb4d8502Sjsg
gfx_v8_0_kcq_init_queue(struct amdgpu_ring * ring)4635fb4d8502Sjsg static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4636fb4d8502Sjsg {
4637fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
4638fb4d8502Sjsg struct vi_mqd *mqd = ring->mqd_ptr;
4639fb4d8502Sjsg int mqd_idx = ring - &adev->gfx.compute_ring[0];
4640fb4d8502Sjsg
4641ad8b1aafSjsg if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4642fb4d8502Sjsg memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4643fb4d8502Sjsg ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4644fb4d8502Sjsg ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4645fb4d8502Sjsg mutex_lock(&adev->srbm_mutex);
4646fb4d8502Sjsg vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4647fb4d8502Sjsg gfx_v8_0_mqd_init(ring);
4648fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, 0);
4649fb4d8502Sjsg mutex_unlock(&adev->srbm_mutex);
4650fb4d8502Sjsg
4651fb4d8502Sjsg if (adev->gfx.mec.mqd_backup[mqd_idx])
4652fb4d8502Sjsg memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4653*f005ef32Sjsg } else {
4654*f005ef32Sjsg /* restore MQD to a clean status */
4655fb4d8502Sjsg if (adev->gfx.mec.mqd_backup[mqd_idx])
4656fb4d8502Sjsg memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4657fb4d8502Sjsg /* reset ring buffer */
4658fb4d8502Sjsg ring->wptr = 0;
4659fb4d8502Sjsg amdgpu_ring_clear_ring(ring);
4660fb4d8502Sjsg }
4661fb4d8502Sjsg return 0;
4662fb4d8502Sjsg }
4663fb4d8502Sjsg
gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device * adev)4664fb4d8502Sjsg static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
4665fb4d8502Sjsg {
4666fb4d8502Sjsg if (adev->asic_type > CHIP_TONGA) {
4667c349dbc7Sjsg WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
4668c349dbc7Sjsg WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
4669fb4d8502Sjsg }
4670fb4d8502Sjsg /* enable doorbells */
4671fb4d8502Sjsg WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4672fb4d8502Sjsg }
4673fb4d8502Sjsg
gfx_v8_0_kiq_resume(struct amdgpu_device * adev)4674fb4d8502Sjsg static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4675fb4d8502Sjsg {
4676c349dbc7Sjsg struct amdgpu_ring *ring;
4677c349dbc7Sjsg int r;
4678fb4d8502Sjsg
4679*f005ef32Sjsg ring = &adev->gfx.kiq[0].ring;
4680fb4d8502Sjsg
4681fb4d8502Sjsg r = amdgpu_bo_reserve(ring->mqd_obj, false);
4682fb4d8502Sjsg if (unlikely(r != 0))
4683c349dbc7Sjsg return r;
4684fb4d8502Sjsg
4685fb4d8502Sjsg r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4686*f005ef32Sjsg if (unlikely(r != 0)) {
4687*f005ef32Sjsg amdgpu_bo_unreserve(ring->mqd_obj);
4688c349dbc7Sjsg return r;
4689*f005ef32Sjsg }
4690c349dbc7Sjsg
4691c349dbc7Sjsg gfx_v8_0_kiq_init_queue(ring);
4692fb4d8502Sjsg amdgpu_bo_kunmap(ring->mqd_obj);
4693fb4d8502Sjsg ring->mqd_ptr = NULL;
4694fb4d8502Sjsg amdgpu_bo_unreserve(ring->mqd_obj);
4695c349dbc7Sjsg return 0;
4696c349dbc7Sjsg }
4697c349dbc7Sjsg
gfx_v8_0_kcq_resume(struct amdgpu_device * adev)4698c349dbc7Sjsg static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
4699c349dbc7Sjsg {
4700c349dbc7Sjsg struct amdgpu_ring *ring = NULL;
4701c349dbc7Sjsg int r = 0, i;
4702c349dbc7Sjsg
4703c349dbc7Sjsg gfx_v8_0_cp_compute_enable(adev, true);
4704fb4d8502Sjsg
4705fb4d8502Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4706fb4d8502Sjsg ring = &adev->gfx.compute_ring[i];
4707fb4d8502Sjsg
4708fb4d8502Sjsg r = amdgpu_bo_reserve(ring->mqd_obj, false);
4709fb4d8502Sjsg if (unlikely(r != 0))
4710fb4d8502Sjsg goto done;
4711fb4d8502Sjsg r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4712fb4d8502Sjsg if (!r) {
4713fb4d8502Sjsg r = gfx_v8_0_kcq_init_queue(ring);
4714fb4d8502Sjsg amdgpu_bo_kunmap(ring->mqd_obj);
4715fb4d8502Sjsg ring->mqd_ptr = NULL;
4716fb4d8502Sjsg }
4717fb4d8502Sjsg amdgpu_bo_unreserve(ring->mqd_obj);
4718fb4d8502Sjsg if (r)
4719fb4d8502Sjsg goto done;
4720fb4d8502Sjsg }
4721fb4d8502Sjsg
4722fb4d8502Sjsg gfx_v8_0_set_mec_doorbell_range(adev);
4723fb4d8502Sjsg
4724fb4d8502Sjsg r = gfx_v8_0_kiq_kcq_enable(adev);
4725fb4d8502Sjsg if (r)
4726fb4d8502Sjsg goto done;
4727fb4d8502Sjsg
4728fb4d8502Sjsg done:
4729fb4d8502Sjsg return r;
4730fb4d8502Sjsg }
4731fb4d8502Sjsg
gfx_v8_0_cp_test_all_rings(struct amdgpu_device * adev)4732c349dbc7Sjsg static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
4733c349dbc7Sjsg {
4734c349dbc7Sjsg int r, i;
4735c349dbc7Sjsg struct amdgpu_ring *ring;
4736c349dbc7Sjsg
4737c349dbc7Sjsg /* collect all the ring_tests here, gfx, kiq, compute */
4738c349dbc7Sjsg ring = &adev->gfx.gfx_ring[0];
4739c349dbc7Sjsg r = amdgpu_ring_test_helper(ring);
4740c349dbc7Sjsg if (r)
4741c349dbc7Sjsg return r;
4742c349dbc7Sjsg
4743*f005ef32Sjsg ring = &adev->gfx.kiq[0].ring;
4744c349dbc7Sjsg r = amdgpu_ring_test_helper(ring);
4745c349dbc7Sjsg if (r)
4746c349dbc7Sjsg return r;
4747c349dbc7Sjsg
4748c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4749c349dbc7Sjsg ring = &adev->gfx.compute_ring[i];
4750c349dbc7Sjsg amdgpu_ring_test_helper(ring);
4751c349dbc7Sjsg }
4752c349dbc7Sjsg
4753c349dbc7Sjsg return 0;
4754c349dbc7Sjsg }
4755c349dbc7Sjsg
gfx_v8_0_cp_resume(struct amdgpu_device * adev)4756fb4d8502Sjsg static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4757fb4d8502Sjsg {
4758fb4d8502Sjsg int r;
4759fb4d8502Sjsg
4760fb4d8502Sjsg if (!(adev->flags & AMD_IS_APU))
4761fb4d8502Sjsg gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4762fb4d8502Sjsg
4763c349dbc7Sjsg r = gfx_v8_0_kiq_resume(adev);
4764fb4d8502Sjsg if (r)
4765fb4d8502Sjsg return r;
4766fb4d8502Sjsg
4767fb4d8502Sjsg r = gfx_v8_0_cp_gfx_resume(adev);
4768fb4d8502Sjsg if (r)
4769fb4d8502Sjsg return r;
4770fb4d8502Sjsg
4771c349dbc7Sjsg r = gfx_v8_0_kcq_resume(adev);
4772c349dbc7Sjsg if (r)
4773c349dbc7Sjsg return r;
4774c349dbc7Sjsg
4775c349dbc7Sjsg r = gfx_v8_0_cp_test_all_rings(adev);
4776fb4d8502Sjsg if (r)
4777fb4d8502Sjsg return r;
4778fb4d8502Sjsg
4779fb4d8502Sjsg gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4780fb4d8502Sjsg
4781fb4d8502Sjsg return 0;
4782fb4d8502Sjsg }
4783fb4d8502Sjsg
gfx_v8_0_cp_enable(struct amdgpu_device * adev,bool enable)4784fb4d8502Sjsg static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4785fb4d8502Sjsg {
4786fb4d8502Sjsg gfx_v8_0_cp_gfx_enable(adev, enable);
4787fb4d8502Sjsg gfx_v8_0_cp_compute_enable(adev, enable);
4788fb4d8502Sjsg }
4789fb4d8502Sjsg
gfx_v8_0_hw_init(void * handle)4790fb4d8502Sjsg static int gfx_v8_0_hw_init(void *handle)
4791fb4d8502Sjsg {
4792fb4d8502Sjsg int r;
4793fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4794fb4d8502Sjsg
4795fb4d8502Sjsg gfx_v8_0_init_golden_registers(adev);
4796c349dbc7Sjsg gfx_v8_0_constants_init(adev);
4797fb4d8502Sjsg
4798c349dbc7Sjsg r = adev->gfx.rlc.funcs->resume(adev);
4799fb4d8502Sjsg if (r)
4800fb4d8502Sjsg return r;
4801fb4d8502Sjsg
4802fb4d8502Sjsg r = gfx_v8_0_cp_resume(adev);
4803fb4d8502Sjsg
4804fb4d8502Sjsg return r;
4805fb4d8502Sjsg }
4806fb4d8502Sjsg
gfx_v8_0_kcq_disable(struct amdgpu_device * adev)4807c349dbc7Sjsg static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
4808fb4d8502Sjsg {
4809fb4d8502Sjsg int r, i;
4810*f005ef32Sjsg struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
4811fb4d8502Sjsg
4812c349dbc7Sjsg r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
4813c349dbc7Sjsg if (r)
4814fb4d8502Sjsg DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4815fb4d8502Sjsg
4816c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4817c349dbc7Sjsg struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4818c349dbc7Sjsg
4819fb4d8502Sjsg amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
4820fb4d8502Sjsg amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
4821fb4d8502Sjsg PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
4822fb4d8502Sjsg PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
4823fb4d8502Sjsg PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
4824fb4d8502Sjsg PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
4825fb4d8502Sjsg amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
4826fb4d8502Sjsg amdgpu_ring_write(kiq_ring, 0);
4827fb4d8502Sjsg amdgpu_ring_write(kiq_ring, 0);
4828fb4d8502Sjsg amdgpu_ring_write(kiq_ring, 0);
4829fb4d8502Sjsg }
4830c349dbc7Sjsg r = amdgpu_ring_test_helper(kiq_ring);
4831c349dbc7Sjsg if (r)
4832c349dbc7Sjsg DRM_ERROR("KCQ disable failed\n");
4833fb4d8502Sjsg
4834fb4d8502Sjsg return r;
4835fb4d8502Sjsg }
4836fb4d8502Sjsg
gfx_v8_0_is_idle(void * handle)4837fb4d8502Sjsg static bool gfx_v8_0_is_idle(void *handle)
4838fb4d8502Sjsg {
4839fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4840fb4d8502Sjsg
4841c349dbc7Sjsg if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
4842c349dbc7Sjsg || RREG32(mmGRBM_STATUS2) != 0x8)
4843fb4d8502Sjsg return false;
4844fb4d8502Sjsg else
4845fb4d8502Sjsg return true;
4846fb4d8502Sjsg }
4847fb4d8502Sjsg
gfx_v8_0_rlc_is_idle(void * handle)4848c349dbc7Sjsg static bool gfx_v8_0_rlc_is_idle(void *handle)
4849c349dbc7Sjsg {
4850c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4851c349dbc7Sjsg
4852c349dbc7Sjsg if (RREG32(mmGRBM_STATUS2) != 0x8)
4853c349dbc7Sjsg return false;
4854c349dbc7Sjsg else
4855c349dbc7Sjsg return true;
4856c349dbc7Sjsg }
4857c349dbc7Sjsg
gfx_v8_0_wait_for_rlc_idle(void * handle)4858c349dbc7Sjsg static int gfx_v8_0_wait_for_rlc_idle(void *handle)
4859c349dbc7Sjsg {
4860c349dbc7Sjsg unsigned int i;
4861c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4862c349dbc7Sjsg
4863c349dbc7Sjsg for (i = 0; i < adev->usec_timeout; i++) {
4864c349dbc7Sjsg if (gfx_v8_0_rlc_is_idle(handle))
4865c349dbc7Sjsg return 0;
4866c349dbc7Sjsg
4867c349dbc7Sjsg udelay(1);
4868c349dbc7Sjsg }
4869c349dbc7Sjsg return -ETIMEDOUT;
4870c349dbc7Sjsg }
4871c349dbc7Sjsg
gfx_v8_0_wait_for_idle(void * handle)4872fb4d8502Sjsg static int gfx_v8_0_wait_for_idle(void *handle)
4873fb4d8502Sjsg {
4874c349dbc7Sjsg unsigned int i;
4875fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4876fb4d8502Sjsg
4877fb4d8502Sjsg for (i = 0; i < adev->usec_timeout; i++) {
4878fb4d8502Sjsg if (gfx_v8_0_is_idle(handle))
4879fb4d8502Sjsg return 0;
4880fb4d8502Sjsg
4881fb4d8502Sjsg udelay(1);
4882fb4d8502Sjsg }
4883fb4d8502Sjsg return -ETIMEDOUT;
4884fb4d8502Sjsg }
4885fb4d8502Sjsg
gfx_v8_0_hw_fini(void * handle)4886c349dbc7Sjsg static int gfx_v8_0_hw_fini(void *handle)
4887c349dbc7Sjsg {
4888c349dbc7Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4889c349dbc7Sjsg
4890c349dbc7Sjsg amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4891c349dbc7Sjsg amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4892c349dbc7Sjsg
4893c349dbc7Sjsg amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4894c349dbc7Sjsg
4895c349dbc7Sjsg amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);
4896c349dbc7Sjsg
4897c349dbc7Sjsg /* disable KCQ to avoid CPC touch memory not valid anymore */
4898c349dbc7Sjsg gfx_v8_0_kcq_disable(adev);
4899c349dbc7Sjsg
4900c349dbc7Sjsg if (amdgpu_sriov_vf(adev)) {
4901c349dbc7Sjsg pr_debug("For SRIOV client, shouldn't do anything.\n");
4902c349dbc7Sjsg return 0;
4903c349dbc7Sjsg }
4904*f005ef32Sjsg amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4905c349dbc7Sjsg if (!gfx_v8_0_wait_for_idle(adev))
4906c349dbc7Sjsg gfx_v8_0_cp_enable(adev, false);
4907c349dbc7Sjsg else
4908c349dbc7Sjsg pr_err("cp is busy, skip halt cp\n");
4909c349dbc7Sjsg if (!gfx_v8_0_wait_for_rlc_idle(adev))
4910c349dbc7Sjsg adev->gfx.rlc.funcs->stop(adev);
4911c349dbc7Sjsg else
4912c349dbc7Sjsg pr_err("rlc is busy, skip halt rlc\n");
4913*f005ef32Sjsg amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4914c349dbc7Sjsg
4915c349dbc7Sjsg return 0;
4916c349dbc7Sjsg }
4917c349dbc7Sjsg
gfx_v8_0_suspend(void * handle)4918c349dbc7Sjsg static int gfx_v8_0_suspend(void *handle)
4919c349dbc7Sjsg {
4920c349dbc7Sjsg return gfx_v8_0_hw_fini(handle);
4921c349dbc7Sjsg }
4922c349dbc7Sjsg
gfx_v8_0_resume(void * handle)4923c349dbc7Sjsg static int gfx_v8_0_resume(void *handle)
4924c349dbc7Sjsg {
4925c349dbc7Sjsg return gfx_v8_0_hw_init(handle);
4926c349dbc7Sjsg }
4927c349dbc7Sjsg
gfx_v8_0_check_soft_reset(void * handle)4928fb4d8502Sjsg static bool gfx_v8_0_check_soft_reset(void *handle)
4929fb4d8502Sjsg {
4930fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4931fb4d8502Sjsg u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4932fb4d8502Sjsg u32 tmp;
4933fb4d8502Sjsg
4934fb4d8502Sjsg /* GRBM_STATUS */
4935fb4d8502Sjsg tmp = RREG32(mmGRBM_STATUS);
4936fb4d8502Sjsg if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4937fb4d8502Sjsg GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4938fb4d8502Sjsg GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4939fb4d8502Sjsg GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4940fb4d8502Sjsg GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4941fb4d8502Sjsg GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
4942fb4d8502Sjsg GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4943fb4d8502Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4944fb4d8502Sjsg GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4945fb4d8502Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4946fb4d8502Sjsg GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4947fb4d8502Sjsg srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4948fb4d8502Sjsg SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4949fb4d8502Sjsg }
4950fb4d8502Sjsg
4951fb4d8502Sjsg /* GRBM_STATUS2 */
4952fb4d8502Sjsg tmp = RREG32(mmGRBM_STATUS2);
4953fb4d8502Sjsg if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4954fb4d8502Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4955fb4d8502Sjsg GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4956fb4d8502Sjsg
4957fb4d8502Sjsg if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
4958fb4d8502Sjsg REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
4959fb4d8502Sjsg REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
4960fb4d8502Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4961fb4d8502Sjsg SOFT_RESET_CPF, 1);
4962fb4d8502Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4963fb4d8502Sjsg SOFT_RESET_CPC, 1);
4964fb4d8502Sjsg grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4965fb4d8502Sjsg SOFT_RESET_CPG, 1);
4966fb4d8502Sjsg srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
4967fb4d8502Sjsg SOFT_RESET_GRBM, 1);
4968fb4d8502Sjsg }
4969fb4d8502Sjsg
4970fb4d8502Sjsg /* SRBM_STATUS */
4971fb4d8502Sjsg tmp = RREG32(mmSRBM_STATUS);
4972fb4d8502Sjsg if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4973fb4d8502Sjsg srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4974fb4d8502Sjsg SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4975fb4d8502Sjsg if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
4976fb4d8502Sjsg srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4977fb4d8502Sjsg SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
4978fb4d8502Sjsg
4979fb4d8502Sjsg if (grbm_soft_reset || srbm_soft_reset) {
4980fb4d8502Sjsg adev->gfx.grbm_soft_reset = grbm_soft_reset;
4981fb4d8502Sjsg adev->gfx.srbm_soft_reset = srbm_soft_reset;
4982fb4d8502Sjsg return true;
4983fb4d8502Sjsg } else {
4984fb4d8502Sjsg adev->gfx.grbm_soft_reset = 0;
4985fb4d8502Sjsg adev->gfx.srbm_soft_reset = 0;
4986fb4d8502Sjsg return false;
4987fb4d8502Sjsg }
4988fb4d8502Sjsg }
4989fb4d8502Sjsg
gfx_v8_0_pre_soft_reset(void * handle)4990fb4d8502Sjsg static int gfx_v8_0_pre_soft_reset(void *handle)
4991fb4d8502Sjsg {
4992fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4993c349dbc7Sjsg u32 grbm_soft_reset = 0;
4994fb4d8502Sjsg
4995fb4d8502Sjsg if ((!adev->gfx.grbm_soft_reset) &&
4996fb4d8502Sjsg (!adev->gfx.srbm_soft_reset))
4997fb4d8502Sjsg return 0;
4998fb4d8502Sjsg
4999fb4d8502Sjsg grbm_soft_reset = adev->gfx.grbm_soft_reset;
5000fb4d8502Sjsg
5001fb4d8502Sjsg /* stop the rlc */
5002c349dbc7Sjsg adev->gfx.rlc.funcs->stop(adev);
5003fb4d8502Sjsg
5004fb4d8502Sjsg if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5005fb4d8502Sjsg REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5006fb4d8502Sjsg /* Disable GFX parsing/prefetching */
5007fb4d8502Sjsg gfx_v8_0_cp_gfx_enable(adev, false);
5008fb4d8502Sjsg
5009fb4d8502Sjsg if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5010fb4d8502Sjsg REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5011fb4d8502Sjsg REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5012fb4d8502Sjsg REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5013fb4d8502Sjsg int i;
5014fb4d8502Sjsg
5015fb4d8502Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5016fb4d8502Sjsg struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5017fb4d8502Sjsg
5018fb4d8502Sjsg mutex_lock(&adev->srbm_mutex);
5019fb4d8502Sjsg vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5020fb4d8502Sjsg gfx_v8_0_deactivate_hqd(adev, 2);
5021fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, 0);
5022fb4d8502Sjsg mutex_unlock(&adev->srbm_mutex);
5023fb4d8502Sjsg }
5024fb4d8502Sjsg /* Disable MEC parsing/prefetching */
5025fb4d8502Sjsg gfx_v8_0_cp_compute_enable(adev, false);
5026fb4d8502Sjsg }
5027fb4d8502Sjsg
5028fb4d8502Sjsg return 0;
5029fb4d8502Sjsg }
5030fb4d8502Sjsg
gfx_v8_0_soft_reset(void * handle)5031fb4d8502Sjsg static int gfx_v8_0_soft_reset(void *handle)
5032fb4d8502Sjsg {
5033fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5034fb4d8502Sjsg u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5035fb4d8502Sjsg u32 tmp;
5036fb4d8502Sjsg
5037fb4d8502Sjsg if ((!adev->gfx.grbm_soft_reset) &&
5038fb4d8502Sjsg (!adev->gfx.srbm_soft_reset))
5039fb4d8502Sjsg return 0;
5040fb4d8502Sjsg
5041fb4d8502Sjsg grbm_soft_reset = adev->gfx.grbm_soft_reset;
5042fb4d8502Sjsg srbm_soft_reset = adev->gfx.srbm_soft_reset;
5043fb4d8502Sjsg
5044fb4d8502Sjsg if (grbm_soft_reset || srbm_soft_reset) {
5045fb4d8502Sjsg tmp = RREG32(mmGMCON_DEBUG);
5046fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5047fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5048fb4d8502Sjsg WREG32(mmGMCON_DEBUG, tmp);
5049fb4d8502Sjsg udelay(50);
5050fb4d8502Sjsg }
5051fb4d8502Sjsg
5052fb4d8502Sjsg if (grbm_soft_reset) {
5053fb4d8502Sjsg tmp = RREG32(mmGRBM_SOFT_RESET);
5054fb4d8502Sjsg tmp |= grbm_soft_reset;
5055fb4d8502Sjsg dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5056fb4d8502Sjsg WREG32(mmGRBM_SOFT_RESET, tmp);
5057fb4d8502Sjsg tmp = RREG32(mmGRBM_SOFT_RESET);
5058fb4d8502Sjsg
5059fb4d8502Sjsg udelay(50);
5060fb4d8502Sjsg
5061fb4d8502Sjsg tmp &= ~grbm_soft_reset;
5062fb4d8502Sjsg WREG32(mmGRBM_SOFT_RESET, tmp);
5063fb4d8502Sjsg tmp = RREG32(mmGRBM_SOFT_RESET);
5064fb4d8502Sjsg }
5065fb4d8502Sjsg
5066fb4d8502Sjsg if (srbm_soft_reset) {
5067fb4d8502Sjsg tmp = RREG32(mmSRBM_SOFT_RESET);
5068fb4d8502Sjsg tmp |= srbm_soft_reset;
5069fb4d8502Sjsg dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5070fb4d8502Sjsg WREG32(mmSRBM_SOFT_RESET, tmp);
5071fb4d8502Sjsg tmp = RREG32(mmSRBM_SOFT_RESET);
5072fb4d8502Sjsg
5073fb4d8502Sjsg udelay(50);
5074fb4d8502Sjsg
5075fb4d8502Sjsg tmp &= ~srbm_soft_reset;
5076fb4d8502Sjsg WREG32(mmSRBM_SOFT_RESET, tmp);
5077fb4d8502Sjsg tmp = RREG32(mmSRBM_SOFT_RESET);
5078fb4d8502Sjsg }
5079fb4d8502Sjsg
5080fb4d8502Sjsg if (grbm_soft_reset || srbm_soft_reset) {
5081fb4d8502Sjsg tmp = RREG32(mmGMCON_DEBUG);
5082fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5083fb4d8502Sjsg tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5084fb4d8502Sjsg WREG32(mmGMCON_DEBUG, tmp);
5085fb4d8502Sjsg }
5086fb4d8502Sjsg
5087fb4d8502Sjsg /* Wait a little for things to settle down */
5088fb4d8502Sjsg udelay(50);
5089fb4d8502Sjsg
5090fb4d8502Sjsg return 0;
5091fb4d8502Sjsg }
5092fb4d8502Sjsg
gfx_v8_0_post_soft_reset(void * handle)5093fb4d8502Sjsg static int gfx_v8_0_post_soft_reset(void *handle)
5094fb4d8502Sjsg {
5095fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5096c349dbc7Sjsg u32 grbm_soft_reset = 0;
5097fb4d8502Sjsg
5098fb4d8502Sjsg if ((!adev->gfx.grbm_soft_reset) &&
5099fb4d8502Sjsg (!adev->gfx.srbm_soft_reset))
5100fb4d8502Sjsg return 0;
5101fb4d8502Sjsg
5102fb4d8502Sjsg grbm_soft_reset = adev->gfx.grbm_soft_reset;
5103fb4d8502Sjsg
5104fb4d8502Sjsg if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5105fb4d8502Sjsg REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5106fb4d8502Sjsg REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5107fb4d8502Sjsg REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5108fb4d8502Sjsg int i;
5109fb4d8502Sjsg
5110fb4d8502Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5111fb4d8502Sjsg struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5112fb4d8502Sjsg
5113fb4d8502Sjsg mutex_lock(&adev->srbm_mutex);
5114fb4d8502Sjsg vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5115fb4d8502Sjsg gfx_v8_0_deactivate_hqd(adev, 2);
5116fb4d8502Sjsg vi_srbm_select(adev, 0, 0, 0, 0);
5117fb4d8502Sjsg mutex_unlock(&adev->srbm_mutex);
5118fb4d8502Sjsg }
5119fb4d8502Sjsg gfx_v8_0_kiq_resume(adev);
5120c349dbc7Sjsg gfx_v8_0_kcq_resume(adev);
5121fb4d8502Sjsg }
5122c349dbc7Sjsg
5123c349dbc7Sjsg if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5124c349dbc7Sjsg REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5125c349dbc7Sjsg gfx_v8_0_cp_gfx_resume(adev);
5126c349dbc7Sjsg
5127c349dbc7Sjsg gfx_v8_0_cp_test_all_rings(adev);
5128c349dbc7Sjsg
5129c349dbc7Sjsg adev->gfx.rlc.funcs->start(adev);
5130fb4d8502Sjsg
5131fb4d8502Sjsg return 0;
5132fb4d8502Sjsg }
5133fb4d8502Sjsg
5134fb4d8502Sjsg /**
5135fb4d8502Sjsg * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5136fb4d8502Sjsg *
5137fb4d8502Sjsg * @adev: amdgpu_device pointer
5138fb4d8502Sjsg *
5139fb4d8502Sjsg * Fetches a GPU clock counter snapshot.
5140fb4d8502Sjsg * Returns the 64 bit clock counter snapshot.
5141fb4d8502Sjsg */
gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device * adev)5142fb4d8502Sjsg static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5143fb4d8502Sjsg {
5144fb4d8502Sjsg uint64_t clock;
5145fb4d8502Sjsg
5146fb4d8502Sjsg mutex_lock(&adev->gfx.gpu_clock_mutex);
5147fb4d8502Sjsg WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5148fb4d8502Sjsg clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5149fb4d8502Sjsg ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5150fb4d8502Sjsg mutex_unlock(&adev->gfx.gpu_clock_mutex);
5151fb4d8502Sjsg return clock;
5152fb4d8502Sjsg }
5153fb4d8502Sjsg
gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)5154fb4d8502Sjsg static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5155fb4d8502Sjsg uint32_t vmid,
5156fb4d8502Sjsg uint32_t gds_base, uint32_t gds_size,
5157fb4d8502Sjsg uint32_t gws_base, uint32_t gws_size,
5158fb4d8502Sjsg uint32_t oa_base, uint32_t oa_size)
5159fb4d8502Sjsg {
5160fb4d8502Sjsg /* GDS Base */
5161fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5162fb4d8502Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5163fb4d8502Sjsg WRITE_DATA_DST_SEL(0)));
5164fb4d8502Sjsg amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5165fb4d8502Sjsg amdgpu_ring_write(ring, 0);
5166fb4d8502Sjsg amdgpu_ring_write(ring, gds_base);
5167fb4d8502Sjsg
5168fb4d8502Sjsg /* GDS Size */
5169fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5170fb4d8502Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5171fb4d8502Sjsg WRITE_DATA_DST_SEL(0)));
5172fb4d8502Sjsg amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5173fb4d8502Sjsg amdgpu_ring_write(ring, 0);
5174fb4d8502Sjsg amdgpu_ring_write(ring, gds_size);
5175fb4d8502Sjsg
5176fb4d8502Sjsg /* GWS */
5177fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5178fb4d8502Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5179fb4d8502Sjsg WRITE_DATA_DST_SEL(0)));
5180fb4d8502Sjsg amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5181fb4d8502Sjsg amdgpu_ring_write(ring, 0);
5182fb4d8502Sjsg amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5183fb4d8502Sjsg
5184fb4d8502Sjsg /* OA */
5185fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5186fb4d8502Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5187fb4d8502Sjsg WRITE_DATA_DST_SEL(0)));
5188fb4d8502Sjsg amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5189fb4d8502Sjsg amdgpu_ring_write(ring, 0);
5190fb4d8502Sjsg amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5191fb4d8502Sjsg }
5192fb4d8502Sjsg
wave_read_ind(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t address)5193fb4d8502Sjsg static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5194fb4d8502Sjsg {
5195fb4d8502Sjsg WREG32(mmSQ_IND_INDEX,
5196fb4d8502Sjsg (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5197fb4d8502Sjsg (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5198fb4d8502Sjsg (address << SQ_IND_INDEX__INDEX__SHIFT) |
5199fb4d8502Sjsg (SQ_IND_INDEX__FORCE_READ_MASK));
5200fb4d8502Sjsg return RREG32(mmSQ_IND_DATA);
5201fb4d8502Sjsg }
5202fb4d8502Sjsg
wave_read_regs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)5203fb4d8502Sjsg static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5204fb4d8502Sjsg uint32_t wave, uint32_t thread,
5205fb4d8502Sjsg uint32_t regno, uint32_t num, uint32_t *out)
5206fb4d8502Sjsg {
5207fb4d8502Sjsg WREG32(mmSQ_IND_INDEX,
5208fb4d8502Sjsg (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5209fb4d8502Sjsg (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5210fb4d8502Sjsg (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5211fb4d8502Sjsg (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5212fb4d8502Sjsg (SQ_IND_INDEX__FORCE_READ_MASK) |
5213fb4d8502Sjsg (SQ_IND_INDEX__AUTO_INCR_MASK));
5214fb4d8502Sjsg while (num--)
5215fb4d8502Sjsg *(out++) = RREG32(mmSQ_IND_DATA);
5216fb4d8502Sjsg }
5217fb4d8502Sjsg
gfx_v8_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)5218*f005ef32Sjsg static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5219fb4d8502Sjsg {
5220fb4d8502Sjsg /* type 0 wave data */
5221fb4d8502Sjsg dst[(*no_fields)++] = 0;
5222fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5223fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5224fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5225fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5226fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5227fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5228fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5229fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5230fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5231fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5232fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5233fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
5234fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5235fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5236fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5237fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5238fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5239fb4d8502Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
52405ca02815Sjsg dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
5241fb4d8502Sjsg }
5242fb4d8502Sjsg
gfx_v8_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)5243*f005ef32Sjsg static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
5244fb4d8502Sjsg uint32_t wave, uint32_t start,
5245fb4d8502Sjsg uint32_t size, uint32_t *dst)
5246fb4d8502Sjsg {
5247fb4d8502Sjsg wave_read_regs(
5248fb4d8502Sjsg adev, simd, wave, 0,
5249fb4d8502Sjsg start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5250fb4d8502Sjsg }
5251fb4d8502Sjsg
5252fb4d8502Sjsg
5253fb4d8502Sjsg static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5254fb4d8502Sjsg .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5255fb4d8502Sjsg .select_se_sh = &gfx_v8_0_select_se_sh,
5256fb4d8502Sjsg .read_wave_data = &gfx_v8_0_read_wave_data,
5257fb4d8502Sjsg .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5258fb4d8502Sjsg .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
5259fb4d8502Sjsg };
5260fb4d8502Sjsg
gfx_v8_0_early_init(void * handle)5261fb4d8502Sjsg static int gfx_v8_0_early_init(void *handle)
5262fb4d8502Sjsg {
5263fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5264fb4d8502Sjsg
5265*f005ef32Sjsg adev->gfx.xcc_mask = 1;
5266fb4d8502Sjsg adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
52675ca02815Sjsg adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
52685ca02815Sjsg AMDGPU_MAX_COMPUTE_RINGS);
5269fb4d8502Sjsg adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
5270fb4d8502Sjsg gfx_v8_0_set_ring_funcs(adev);
5271fb4d8502Sjsg gfx_v8_0_set_irq_funcs(adev);
5272fb4d8502Sjsg gfx_v8_0_set_gds_init(adev);
5273fb4d8502Sjsg gfx_v8_0_set_rlc_funcs(adev);
5274fb4d8502Sjsg
5275fb4d8502Sjsg return 0;
5276fb4d8502Sjsg }
5277fb4d8502Sjsg
gfx_v8_0_late_init(void * handle)5278fb4d8502Sjsg static int gfx_v8_0_late_init(void *handle)
5279fb4d8502Sjsg {
5280fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5281fb4d8502Sjsg int r;
5282fb4d8502Sjsg
5283fb4d8502Sjsg r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5284fb4d8502Sjsg if (r)
5285fb4d8502Sjsg return r;
5286fb4d8502Sjsg
5287fb4d8502Sjsg r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5288fb4d8502Sjsg if (r)
5289fb4d8502Sjsg return r;
5290fb4d8502Sjsg
5291fb4d8502Sjsg /* requires IBs so do in late init after IB pool is initialized */
5292fb4d8502Sjsg r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5293fb4d8502Sjsg if (r)
5294fb4d8502Sjsg return r;
5295fb4d8502Sjsg
5296fb4d8502Sjsg r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
5297fb4d8502Sjsg if (r) {
5298fb4d8502Sjsg DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r);
5299fb4d8502Sjsg return r;
5300fb4d8502Sjsg }
5301fb4d8502Sjsg
5302fb4d8502Sjsg r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);
5303fb4d8502Sjsg if (r) {
5304fb4d8502Sjsg DRM_ERROR(
5305fb4d8502Sjsg "amdgpu_irq_get() failed to get IRQ for SQ, r: %d.\n",
5306fb4d8502Sjsg r);
5307fb4d8502Sjsg return r;
5308fb4d8502Sjsg }
5309fb4d8502Sjsg
5310fb4d8502Sjsg return 0;
5311fb4d8502Sjsg }
5312fb4d8502Sjsg
gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device * adev,bool enable)5313fb4d8502Sjsg static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5314fb4d8502Sjsg bool enable)
5315fb4d8502Sjsg {
5316ad8b1aafSjsg if ((adev->asic_type == CHIP_POLARIS11) ||
5317fb4d8502Sjsg (adev->asic_type == CHIP_POLARIS12) ||
5318ad8b1aafSjsg (adev->asic_type == CHIP_VEGAM))
5319fb4d8502Sjsg /* Send msg to SMU via Powerplay */
5320fb4d8502Sjsg amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
5321fb4d8502Sjsg
5322fb4d8502Sjsg WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5323fb4d8502Sjsg }
5324fb4d8502Sjsg
gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device * adev,bool enable)5325fb4d8502Sjsg static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5326fb4d8502Sjsg bool enable)
5327fb4d8502Sjsg {
5328fb4d8502Sjsg WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5329fb4d8502Sjsg }
5330fb4d8502Sjsg
polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device * adev,bool enable)5331fb4d8502Sjsg static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5332fb4d8502Sjsg bool enable)
5333fb4d8502Sjsg {
5334fb4d8502Sjsg WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5335fb4d8502Sjsg }
5336fb4d8502Sjsg
cz_enable_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)5337fb4d8502Sjsg static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5338fb4d8502Sjsg bool enable)
5339fb4d8502Sjsg {
5340fb4d8502Sjsg WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5341fb4d8502Sjsg }
5342fb4d8502Sjsg
cz_enable_gfx_pipeline_power_gating(struct amdgpu_device * adev,bool enable)5343fb4d8502Sjsg static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5344fb4d8502Sjsg bool enable)
5345fb4d8502Sjsg {
5346fb4d8502Sjsg WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
5347fb4d8502Sjsg
5348fb4d8502Sjsg /* Read any GFX register to wake up GFX. */
5349fb4d8502Sjsg if (!enable)
5350fb4d8502Sjsg RREG32(mmDB_RENDER_CONTROL);
5351fb4d8502Sjsg }
5352fb4d8502Sjsg
cz_update_gfx_cg_power_gating(struct amdgpu_device * adev,bool enable)5353fb4d8502Sjsg static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5354fb4d8502Sjsg bool enable)
5355fb4d8502Sjsg {
5356fb4d8502Sjsg if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5357fb4d8502Sjsg cz_enable_gfx_cg_power_gating(adev, true);
5358fb4d8502Sjsg if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5359fb4d8502Sjsg cz_enable_gfx_pipeline_power_gating(adev, true);
5360fb4d8502Sjsg } else {
5361fb4d8502Sjsg cz_enable_gfx_cg_power_gating(adev, false);
5362fb4d8502Sjsg cz_enable_gfx_pipeline_power_gating(adev, false);
5363fb4d8502Sjsg }
5364fb4d8502Sjsg }
5365fb4d8502Sjsg
gfx_v8_0_set_powergating_state(void * handle,enum amd_powergating_state state)5366fb4d8502Sjsg static int gfx_v8_0_set_powergating_state(void *handle,
5367fb4d8502Sjsg enum amd_powergating_state state)
5368fb4d8502Sjsg {
5369fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5370fb4d8502Sjsg bool enable = (state == AMD_PG_STATE_GATE);
5371fb4d8502Sjsg
5372fb4d8502Sjsg if (amdgpu_sriov_vf(adev))
5373fb4d8502Sjsg return 0;
5374fb4d8502Sjsg
5375fb4d8502Sjsg if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5376fb4d8502Sjsg AMD_PG_SUPPORT_RLC_SMU_HS |
5377fb4d8502Sjsg AMD_PG_SUPPORT_CP |
5378fb4d8502Sjsg AMD_PG_SUPPORT_GFX_DMG))
5379*f005ef32Sjsg amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5380fb4d8502Sjsg switch (adev->asic_type) {
5381fb4d8502Sjsg case CHIP_CARRIZO:
5382fb4d8502Sjsg case CHIP_STONEY:
5383fb4d8502Sjsg
5384fb4d8502Sjsg if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5385fb4d8502Sjsg cz_enable_sck_slow_down_on_power_up(adev, true);
5386fb4d8502Sjsg cz_enable_sck_slow_down_on_power_down(adev, true);
5387fb4d8502Sjsg } else {
5388fb4d8502Sjsg cz_enable_sck_slow_down_on_power_up(adev, false);
5389fb4d8502Sjsg cz_enable_sck_slow_down_on_power_down(adev, false);
5390fb4d8502Sjsg }
5391fb4d8502Sjsg if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5392fb4d8502Sjsg cz_enable_cp_power_gating(adev, true);
5393fb4d8502Sjsg else
5394fb4d8502Sjsg cz_enable_cp_power_gating(adev, false);
5395fb4d8502Sjsg
5396fb4d8502Sjsg cz_update_gfx_cg_power_gating(adev, enable);
5397fb4d8502Sjsg
5398fb4d8502Sjsg if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5399fb4d8502Sjsg gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5400fb4d8502Sjsg else
5401fb4d8502Sjsg gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5402fb4d8502Sjsg
5403fb4d8502Sjsg if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5404fb4d8502Sjsg gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5405fb4d8502Sjsg else
5406fb4d8502Sjsg gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5407fb4d8502Sjsg break;
5408fb4d8502Sjsg case CHIP_POLARIS11:
5409fb4d8502Sjsg case CHIP_POLARIS12:
5410fb4d8502Sjsg case CHIP_VEGAM:
5411fb4d8502Sjsg if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5412fb4d8502Sjsg gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5413fb4d8502Sjsg else
5414fb4d8502Sjsg gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5415fb4d8502Sjsg
5416fb4d8502Sjsg if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5417fb4d8502Sjsg gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5418fb4d8502Sjsg else
5419fb4d8502Sjsg gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5420fb4d8502Sjsg
5421fb4d8502Sjsg if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5422fb4d8502Sjsg polaris11_enable_gfx_quick_mg_power_gating(adev, true);
5423fb4d8502Sjsg else
5424fb4d8502Sjsg polaris11_enable_gfx_quick_mg_power_gating(adev, false);
5425fb4d8502Sjsg break;
5426fb4d8502Sjsg default:
5427fb4d8502Sjsg break;
5428fb4d8502Sjsg }
5429fb4d8502Sjsg if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5430fb4d8502Sjsg AMD_PG_SUPPORT_RLC_SMU_HS |
5431fb4d8502Sjsg AMD_PG_SUPPORT_CP |
5432fb4d8502Sjsg AMD_PG_SUPPORT_GFX_DMG))
5433*f005ef32Sjsg amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5434fb4d8502Sjsg return 0;
5435fb4d8502Sjsg }
5436fb4d8502Sjsg
gfx_v8_0_get_clockgating_state(void * handle,u64 * flags)54371bb76ff1Sjsg static void gfx_v8_0_get_clockgating_state(void *handle, u64 *flags)
5438fb4d8502Sjsg {
5439fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5440fb4d8502Sjsg int data;
5441fb4d8502Sjsg
5442fb4d8502Sjsg if (amdgpu_sriov_vf(adev))
5443fb4d8502Sjsg *flags = 0;
5444fb4d8502Sjsg
5445fb4d8502Sjsg /* AMD_CG_SUPPORT_GFX_MGCG */
5446fb4d8502Sjsg data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5447fb4d8502Sjsg if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
5448fb4d8502Sjsg *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5449fb4d8502Sjsg
5450fb4d8502Sjsg /* AMD_CG_SUPPORT_GFX_CGLG */
5451fb4d8502Sjsg data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5452fb4d8502Sjsg if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5453fb4d8502Sjsg *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5454fb4d8502Sjsg
5455fb4d8502Sjsg /* AMD_CG_SUPPORT_GFX_CGLS */
5456fb4d8502Sjsg if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5457fb4d8502Sjsg *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5458fb4d8502Sjsg
5459fb4d8502Sjsg /* AMD_CG_SUPPORT_GFX_CGTS */
5460fb4d8502Sjsg data = RREG32(mmCGTS_SM_CTRL_REG);
5461fb4d8502Sjsg if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
5462fb4d8502Sjsg *flags |= AMD_CG_SUPPORT_GFX_CGTS;
5463fb4d8502Sjsg
5464fb4d8502Sjsg /* AMD_CG_SUPPORT_GFX_CGTS_LS */
5465fb4d8502Sjsg if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
5466fb4d8502Sjsg *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
5467fb4d8502Sjsg
5468fb4d8502Sjsg /* AMD_CG_SUPPORT_GFX_RLC_LS */
5469fb4d8502Sjsg data = RREG32(mmRLC_MEM_SLP_CNTL);
5470fb4d8502Sjsg if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5471fb4d8502Sjsg *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5472fb4d8502Sjsg
5473fb4d8502Sjsg /* AMD_CG_SUPPORT_GFX_CP_LS */
5474fb4d8502Sjsg data = RREG32(mmCP_MEM_SLP_CNTL);
5475fb4d8502Sjsg if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5476fb4d8502Sjsg *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5477fb4d8502Sjsg }
5478fb4d8502Sjsg
gfx_v8_0_send_serdes_cmd(struct amdgpu_device * adev,uint32_t reg_addr,uint32_t cmd)5479fb4d8502Sjsg static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
5480fb4d8502Sjsg uint32_t reg_addr, uint32_t cmd)
5481fb4d8502Sjsg {
5482fb4d8502Sjsg uint32_t data;
5483fb4d8502Sjsg
5484*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5485fb4d8502Sjsg
5486fb4d8502Sjsg WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5487fb4d8502Sjsg WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5488fb4d8502Sjsg
5489fb4d8502Sjsg data = RREG32(mmRLC_SERDES_WR_CTRL);
5490fb4d8502Sjsg if (adev->asic_type == CHIP_STONEY)
5491fb4d8502Sjsg data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5492fb4d8502Sjsg RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5493fb4d8502Sjsg RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5494fb4d8502Sjsg RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5495fb4d8502Sjsg RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5496fb4d8502Sjsg RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5497fb4d8502Sjsg RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5498fb4d8502Sjsg RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5499fb4d8502Sjsg RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5500fb4d8502Sjsg else
5501fb4d8502Sjsg data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5502fb4d8502Sjsg RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5503fb4d8502Sjsg RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5504fb4d8502Sjsg RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5505fb4d8502Sjsg RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5506fb4d8502Sjsg RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5507fb4d8502Sjsg RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5508fb4d8502Sjsg RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5509fb4d8502Sjsg RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5510fb4d8502Sjsg RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5511fb4d8502Sjsg RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5512fb4d8502Sjsg data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
5513fb4d8502Sjsg (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5514fb4d8502Sjsg (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5515fb4d8502Sjsg (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
5516fb4d8502Sjsg
5517fb4d8502Sjsg WREG32(mmRLC_SERDES_WR_CTRL, data);
5518fb4d8502Sjsg }
5519fb4d8502Sjsg
5520fb4d8502Sjsg #define MSG_ENTER_RLC_SAFE_MODE 1
5521fb4d8502Sjsg #define MSG_EXIT_RLC_SAFE_MODE 0
5522fb4d8502Sjsg #define RLC_GPR_REG2__REQ_MASK 0x00000001
5523fb4d8502Sjsg #define RLC_GPR_REG2__REQ__SHIFT 0
5524fb4d8502Sjsg #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5525fb4d8502Sjsg #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5526fb4d8502Sjsg
gfx_v8_0_is_rlc_enabled(struct amdgpu_device * adev)5527c349dbc7Sjsg static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
5528fb4d8502Sjsg {
5529c349dbc7Sjsg uint32_t rlc_setting;
5530c349dbc7Sjsg
5531c349dbc7Sjsg rlc_setting = RREG32(mmRLC_CNTL);
5532c349dbc7Sjsg if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
5533c349dbc7Sjsg return false;
5534c349dbc7Sjsg
5535c349dbc7Sjsg return true;
5536c349dbc7Sjsg }
5537c349dbc7Sjsg
gfx_v8_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)5538*f005ef32Sjsg static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
5539c349dbc7Sjsg {
5540c349dbc7Sjsg uint32_t data;
5541fb4d8502Sjsg unsigned i;
5542fb4d8502Sjsg data = RREG32(mmRLC_CNTL);
5543fb4d8502Sjsg data |= RLC_SAFE_MODE__CMD_MASK;
5544fb4d8502Sjsg data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5545fb4d8502Sjsg data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5546fb4d8502Sjsg WREG32(mmRLC_SAFE_MODE, data);
5547fb4d8502Sjsg
5548c349dbc7Sjsg /* wait for RLC_SAFE_MODE */
5549fb4d8502Sjsg for (i = 0; i < adev->usec_timeout; i++) {
5550fb4d8502Sjsg if ((RREG32(mmRLC_GPM_STAT) &
5551fb4d8502Sjsg (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5552fb4d8502Sjsg RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5553fb4d8502Sjsg (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5554fb4d8502Sjsg RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5555fb4d8502Sjsg break;
5556fb4d8502Sjsg udelay(1);
5557fb4d8502Sjsg }
5558fb4d8502Sjsg for (i = 0; i < adev->usec_timeout; i++) {
5559fb4d8502Sjsg if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5560fb4d8502Sjsg break;
5561fb4d8502Sjsg udelay(1);
5562fb4d8502Sjsg }
5563fb4d8502Sjsg }
5564fb4d8502Sjsg
gfx_v8_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)5565*f005ef32Sjsg static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
5566fb4d8502Sjsg {
5567c349dbc7Sjsg uint32_t data;
5568fb4d8502Sjsg unsigned i;
5569fb4d8502Sjsg
5570fb4d8502Sjsg data = RREG32(mmRLC_CNTL);
5571fb4d8502Sjsg data |= RLC_SAFE_MODE__CMD_MASK;
5572fb4d8502Sjsg data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5573fb4d8502Sjsg WREG32(mmRLC_SAFE_MODE, data);
5574fb4d8502Sjsg
5575fb4d8502Sjsg for (i = 0; i < adev->usec_timeout; i++) {
5576fb4d8502Sjsg if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5577fb4d8502Sjsg break;
5578fb4d8502Sjsg udelay(1);
5579fb4d8502Sjsg }
5580fb4d8502Sjsg }
5581fb4d8502Sjsg
gfx_v8_0_update_spm_vmid(struct amdgpu_device * adev,unsigned vmid)5582c349dbc7Sjsg static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5583c349dbc7Sjsg {
5584c349dbc7Sjsg u32 data;
5585c349dbc7Sjsg
55861bb76ff1Sjsg amdgpu_gfx_off_ctrl(adev, false);
55871bb76ff1Sjsg
5588ad8b1aafSjsg if (amdgpu_sriov_is_pp_one_vf(adev))
5589ad8b1aafSjsg data = RREG32_NO_KIQ(mmRLC_SPM_VMID);
5590ad8b1aafSjsg else
5591c349dbc7Sjsg data = RREG32(mmRLC_SPM_VMID);
5592c349dbc7Sjsg
5593c349dbc7Sjsg data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
5594c349dbc7Sjsg data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
5595c349dbc7Sjsg
5596ad8b1aafSjsg if (amdgpu_sriov_is_pp_one_vf(adev))
5597ad8b1aafSjsg WREG32_NO_KIQ(mmRLC_SPM_VMID, data);
5598ad8b1aafSjsg else
5599c349dbc7Sjsg WREG32(mmRLC_SPM_VMID, data);
56001bb76ff1Sjsg
56011bb76ff1Sjsg amdgpu_gfx_off_ctrl(adev, true);
5602c349dbc7Sjsg }
5603c349dbc7Sjsg
5604fb4d8502Sjsg static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5605c349dbc7Sjsg .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
5606c349dbc7Sjsg .set_safe_mode = gfx_v8_0_set_safe_mode,
5607c349dbc7Sjsg .unset_safe_mode = gfx_v8_0_unset_safe_mode,
5608c349dbc7Sjsg .init = gfx_v8_0_rlc_init,
5609c349dbc7Sjsg .get_csb_size = gfx_v8_0_get_csb_size,
5610c349dbc7Sjsg .get_csb_buffer = gfx_v8_0_get_csb_buffer,
5611c349dbc7Sjsg .get_cp_table_num = gfx_v8_0_cp_jump_table_num,
5612c349dbc7Sjsg .resume = gfx_v8_0_rlc_resume,
5613c349dbc7Sjsg .stop = gfx_v8_0_rlc_stop,
5614c349dbc7Sjsg .reset = gfx_v8_0_rlc_reset,
5615c349dbc7Sjsg .start = gfx_v8_0_rlc_start,
5616c349dbc7Sjsg .update_spm_vmid = gfx_v8_0_update_spm_vmid
5617fb4d8502Sjsg };
5618fb4d8502Sjsg
gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)5619fb4d8502Sjsg static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5620fb4d8502Sjsg bool enable)
5621fb4d8502Sjsg {
5622fb4d8502Sjsg uint32_t temp, data;
5623fb4d8502Sjsg
5624*f005ef32Sjsg amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5625fb4d8502Sjsg
5626fb4d8502Sjsg /* It is disabled by HW by default */
5627fb4d8502Sjsg if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5628fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5629fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
5630fb4d8502Sjsg /* 1 - RLC memory Light sleep */
5631fb4d8502Sjsg WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
5632fb4d8502Sjsg
5633fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5634fb4d8502Sjsg WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
5635fb4d8502Sjsg }
5636fb4d8502Sjsg
5637fb4d8502Sjsg /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5638fb4d8502Sjsg temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5639fb4d8502Sjsg if (adev->flags & AMD_IS_APU)
5640fb4d8502Sjsg data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5641fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5642fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5643fb4d8502Sjsg else
5644fb4d8502Sjsg data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5645fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5646fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5647fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5648fb4d8502Sjsg
5649fb4d8502Sjsg if (temp != data)
5650fb4d8502Sjsg WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5651fb4d8502Sjsg
5652fb4d8502Sjsg /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5653fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5654fb4d8502Sjsg
5655fb4d8502Sjsg /* 5 - clear mgcg override */
5656fb4d8502Sjsg gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5657fb4d8502Sjsg
5658fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5659fb4d8502Sjsg /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5660fb4d8502Sjsg temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5661fb4d8502Sjsg data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5662fb4d8502Sjsg data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5663fb4d8502Sjsg data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5664fb4d8502Sjsg data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5665fb4d8502Sjsg if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5666fb4d8502Sjsg (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5667fb4d8502Sjsg data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5668fb4d8502Sjsg data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5669fb4d8502Sjsg data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5670fb4d8502Sjsg if (temp != data)
5671fb4d8502Sjsg WREG32(mmCGTS_SM_CTRL_REG, data);
5672fb4d8502Sjsg }
5673fb4d8502Sjsg udelay(50);
5674fb4d8502Sjsg
5675fb4d8502Sjsg /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5676fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5677fb4d8502Sjsg } else {
5678fb4d8502Sjsg /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5679fb4d8502Sjsg temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5680fb4d8502Sjsg data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5681fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5682fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5683fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5684fb4d8502Sjsg if (temp != data)
5685fb4d8502Sjsg WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5686fb4d8502Sjsg
5687fb4d8502Sjsg /* 2 - disable MGLS in RLC */
5688fb4d8502Sjsg data = RREG32(mmRLC_MEM_SLP_CNTL);
5689fb4d8502Sjsg if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5690fb4d8502Sjsg data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5691fb4d8502Sjsg WREG32(mmRLC_MEM_SLP_CNTL, data);
5692fb4d8502Sjsg }
5693fb4d8502Sjsg
5694fb4d8502Sjsg /* 3 - disable MGLS in CP */
5695fb4d8502Sjsg data = RREG32(mmCP_MEM_SLP_CNTL);
5696fb4d8502Sjsg if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5697fb4d8502Sjsg data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5698fb4d8502Sjsg WREG32(mmCP_MEM_SLP_CNTL, data);
5699fb4d8502Sjsg }
5700fb4d8502Sjsg
5701fb4d8502Sjsg /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5702fb4d8502Sjsg temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5703fb4d8502Sjsg data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5704fb4d8502Sjsg CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5705fb4d8502Sjsg if (temp != data)
5706fb4d8502Sjsg WREG32(mmCGTS_SM_CTRL_REG, data);
5707fb4d8502Sjsg
5708fb4d8502Sjsg /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5709fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5710fb4d8502Sjsg
5711fb4d8502Sjsg /* 6 - set mgcg override */
5712fb4d8502Sjsg gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5713fb4d8502Sjsg
5714fb4d8502Sjsg udelay(50);
5715fb4d8502Sjsg
5716fb4d8502Sjsg /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5717fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5718fb4d8502Sjsg }
5719fb4d8502Sjsg
5720*f005ef32Sjsg amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5721fb4d8502Sjsg }
5722fb4d8502Sjsg
gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)5723fb4d8502Sjsg static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5724fb4d8502Sjsg bool enable)
5725fb4d8502Sjsg {
5726fb4d8502Sjsg uint32_t temp, temp1, data, data1;
5727fb4d8502Sjsg
5728fb4d8502Sjsg temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5729fb4d8502Sjsg
5730*f005ef32Sjsg amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5731fb4d8502Sjsg
5732fb4d8502Sjsg if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5733fb4d8502Sjsg temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5734fb4d8502Sjsg data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5735fb4d8502Sjsg if (temp1 != data1)
5736fb4d8502Sjsg WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5737fb4d8502Sjsg
5738fb4d8502Sjsg /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5739fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5740fb4d8502Sjsg
5741fb4d8502Sjsg /* 2 - clear cgcg override */
5742fb4d8502Sjsg gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5743fb4d8502Sjsg
5744fb4d8502Sjsg /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5745fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5746fb4d8502Sjsg
5747fb4d8502Sjsg /* 3 - write cmd to set CGLS */
5748fb4d8502Sjsg gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5749fb4d8502Sjsg
5750fb4d8502Sjsg /* 4 - enable cgcg */
5751fb4d8502Sjsg data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5752fb4d8502Sjsg
5753fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5754fb4d8502Sjsg /* enable cgls*/
5755fb4d8502Sjsg data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5756fb4d8502Sjsg
5757fb4d8502Sjsg temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5758fb4d8502Sjsg data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
5759fb4d8502Sjsg
5760fb4d8502Sjsg if (temp1 != data1)
5761fb4d8502Sjsg WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5762fb4d8502Sjsg } else {
5763fb4d8502Sjsg data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5764fb4d8502Sjsg }
5765fb4d8502Sjsg
5766fb4d8502Sjsg if (temp != data)
5767fb4d8502Sjsg WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5768fb4d8502Sjsg
5769fb4d8502Sjsg /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5770fb4d8502Sjsg * Cmp_busy/GFX_Idle interrupts
5771fb4d8502Sjsg */
5772fb4d8502Sjsg gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5773fb4d8502Sjsg } else {
5774fb4d8502Sjsg /* disable cntx_empty_int_enable & GFX Idle interrupt */
5775fb4d8502Sjsg gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5776fb4d8502Sjsg
5777fb4d8502Sjsg /* TEST CGCG */
5778fb4d8502Sjsg temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5779fb4d8502Sjsg data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5780fb4d8502Sjsg RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5781fb4d8502Sjsg if (temp1 != data1)
5782fb4d8502Sjsg WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5783fb4d8502Sjsg
5784fb4d8502Sjsg /* read gfx register to wake up cgcg */
5785fb4d8502Sjsg RREG32(mmCB_CGTT_SCLK_CTRL);
5786fb4d8502Sjsg RREG32(mmCB_CGTT_SCLK_CTRL);
5787fb4d8502Sjsg RREG32(mmCB_CGTT_SCLK_CTRL);
5788fb4d8502Sjsg RREG32(mmCB_CGTT_SCLK_CTRL);
5789fb4d8502Sjsg
5790fb4d8502Sjsg /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5791fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5792fb4d8502Sjsg
57931bb76ff1Sjsg /* write cmd to Set CGCG Override */
5794fb4d8502Sjsg gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5795fb4d8502Sjsg
5796fb4d8502Sjsg /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5797fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5798fb4d8502Sjsg
5799fb4d8502Sjsg /* write cmd to Clear CGLS */
5800fb4d8502Sjsg gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
5801fb4d8502Sjsg
5802fb4d8502Sjsg /* disable cgcg, cgls should be disabled too. */
5803fb4d8502Sjsg data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
5804fb4d8502Sjsg RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
5805fb4d8502Sjsg if (temp != data)
5806fb4d8502Sjsg WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5807fb4d8502Sjsg /* enable interrupts again for PG */
5808fb4d8502Sjsg gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5809fb4d8502Sjsg }
5810fb4d8502Sjsg
5811fb4d8502Sjsg gfx_v8_0_wait_for_rlc_serdes(adev);
5812fb4d8502Sjsg
5813*f005ef32Sjsg amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5814fb4d8502Sjsg }
gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)5815fb4d8502Sjsg static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5816fb4d8502Sjsg bool enable)
5817fb4d8502Sjsg {
5818fb4d8502Sjsg if (enable) {
5819fb4d8502Sjsg /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5820fb4d8502Sjsg * === MGCG + MGLS + TS(CG/LS) ===
5821fb4d8502Sjsg */
5822fb4d8502Sjsg gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5823fb4d8502Sjsg gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5824fb4d8502Sjsg } else {
5825fb4d8502Sjsg /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5826fb4d8502Sjsg * === CGCG + CGLS ===
5827fb4d8502Sjsg */
5828fb4d8502Sjsg gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5829fb4d8502Sjsg gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5830fb4d8502Sjsg }
5831fb4d8502Sjsg return 0;
5832fb4d8502Sjsg }
5833fb4d8502Sjsg
gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device * adev,enum amd_clockgating_state state)5834fb4d8502Sjsg static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5835fb4d8502Sjsg enum amd_clockgating_state state)
5836fb4d8502Sjsg {
5837fb4d8502Sjsg uint32_t msg_id, pp_state = 0;
5838fb4d8502Sjsg uint32_t pp_support_state = 0;
5839fb4d8502Sjsg
5840fb4d8502Sjsg if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5841fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5842fb4d8502Sjsg pp_support_state = PP_STATE_SUPPORT_LS;
5843fb4d8502Sjsg pp_state = PP_STATE_LS;
5844fb4d8502Sjsg }
5845fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5846fb4d8502Sjsg pp_support_state |= PP_STATE_SUPPORT_CG;
5847fb4d8502Sjsg pp_state |= PP_STATE_CG;
5848fb4d8502Sjsg }
5849fb4d8502Sjsg if (state == AMD_CG_STATE_UNGATE)
5850fb4d8502Sjsg pp_state = 0;
5851fb4d8502Sjsg
5852fb4d8502Sjsg msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5853fb4d8502Sjsg PP_BLOCK_GFX_CG,
5854fb4d8502Sjsg pp_support_state,
5855fb4d8502Sjsg pp_state);
5856fb4d8502Sjsg amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5857fb4d8502Sjsg }
5858fb4d8502Sjsg
5859fb4d8502Sjsg if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5860fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5861fb4d8502Sjsg pp_support_state = PP_STATE_SUPPORT_LS;
5862fb4d8502Sjsg pp_state = PP_STATE_LS;
5863fb4d8502Sjsg }
5864fb4d8502Sjsg
5865fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5866fb4d8502Sjsg pp_support_state |= PP_STATE_SUPPORT_CG;
5867fb4d8502Sjsg pp_state |= PP_STATE_CG;
5868fb4d8502Sjsg }
5869fb4d8502Sjsg
5870fb4d8502Sjsg if (state == AMD_CG_STATE_UNGATE)
5871fb4d8502Sjsg pp_state = 0;
5872fb4d8502Sjsg
5873fb4d8502Sjsg msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5874fb4d8502Sjsg PP_BLOCK_GFX_MG,
5875fb4d8502Sjsg pp_support_state,
5876fb4d8502Sjsg pp_state);
5877fb4d8502Sjsg amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5878fb4d8502Sjsg }
5879fb4d8502Sjsg
5880fb4d8502Sjsg return 0;
5881fb4d8502Sjsg }
5882fb4d8502Sjsg
gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device * adev,enum amd_clockgating_state state)5883fb4d8502Sjsg static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5884fb4d8502Sjsg enum amd_clockgating_state state)
5885fb4d8502Sjsg {
5886fb4d8502Sjsg
5887fb4d8502Sjsg uint32_t msg_id, pp_state = 0;
5888fb4d8502Sjsg uint32_t pp_support_state = 0;
5889fb4d8502Sjsg
5890fb4d8502Sjsg if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5891fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5892fb4d8502Sjsg pp_support_state = PP_STATE_SUPPORT_LS;
5893fb4d8502Sjsg pp_state = PP_STATE_LS;
5894fb4d8502Sjsg }
5895fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5896fb4d8502Sjsg pp_support_state |= PP_STATE_SUPPORT_CG;
5897fb4d8502Sjsg pp_state |= PP_STATE_CG;
5898fb4d8502Sjsg }
5899fb4d8502Sjsg if (state == AMD_CG_STATE_UNGATE)
5900fb4d8502Sjsg pp_state = 0;
5901fb4d8502Sjsg
5902fb4d8502Sjsg msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5903fb4d8502Sjsg PP_BLOCK_GFX_CG,
5904fb4d8502Sjsg pp_support_state,
5905fb4d8502Sjsg pp_state);
5906fb4d8502Sjsg amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5907fb4d8502Sjsg }
5908fb4d8502Sjsg
5909fb4d8502Sjsg if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5910fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5911fb4d8502Sjsg pp_support_state = PP_STATE_SUPPORT_LS;
5912fb4d8502Sjsg pp_state = PP_STATE_LS;
5913fb4d8502Sjsg }
5914fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5915fb4d8502Sjsg pp_support_state |= PP_STATE_SUPPORT_CG;
5916fb4d8502Sjsg pp_state |= PP_STATE_CG;
5917fb4d8502Sjsg }
5918fb4d8502Sjsg if (state == AMD_CG_STATE_UNGATE)
5919fb4d8502Sjsg pp_state = 0;
5920fb4d8502Sjsg
5921fb4d8502Sjsg msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5922fb4d8502Sjsg PP_BLOCK_GFX_3D,
5923fb4d8502Sjsg pp_support_state,
5924fb4d8502Sjsg pp_state);
5925fb4d8502Sjsg amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5926fb4d8502Sjsg }
5927fb4d8502Sjsg
5928fb4d8502Sjsg if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5929fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5930fb4d8502Sjsg pp_support_state = PP_STATE_SUPPORT_LS;
5931fb4d8502Sjsg pp_state = PP_STATE_LS;
5932fb4d8502Sjsg }
5933fb4d8502Sjsg
5934fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5935fb4d8502Sjsg pp_support_state |= PP_STATE_SUPPORT_CG;
5936fb4d8502Sjsg pp_state |= PP_STATE_CG;
5937fb4d8502Sjsg }
5938fb4d8502Sjsg
5939fb4d8502Sjsg if (state == AMD_CG_STATE_UNGATE)
5940fb4d8502Sjsg pp_state = 0;
5941fb4d8502Sjsg
5942fb4d8502Sjsg msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5943fb4d8502Sjsg PP_BLOCK_GFX_MG,
5944fb4d8502Sjsg pp_support_state,
5945fb4d8502Sjsg pp_state);
5946fb4d8502Sjsg amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5947fb4d8502Sjsg }
5948fb4d8502Sjsg
5949fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5950fb4d8502Sjsg pp_support_state = PP_STATE_SUPPORT_LS;
5951fb4d8502Sjsg
5952fb4d8502Sjsg if (state == AMD_CG_STATE_UNGATE)
5953fb4d8502Sjsg pp_state = 0;
5954fb4d8502Sjsg else
5955fb4d8502Sjsg pp_state = PP_STATE_LS;
5956fb4d8502Sjsg
5957fb4d8502Sjsg msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5958fb4d8502Sjsg PP_BLOCK_GFX_RLC,
5959fb4d8502Sjsg pp_support_state,
5960fb4d8502Sjsg pp_state);
5961fb4d8502Sjsg amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5962fb4d8502Sjsg }
5963fb4d8502Sjsg
5964fb4d8502Sjsg if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5965fb4d8502Sjsg pp_support_state = PP_STATE_SUPPORT_LS;
5966fb4d8502Sjsg
5967fb4d8502Sjsg if (state == AMD_CG_STATE_UNGATE)
5968fb4d8502Sjsg pp_state = 0;
5969fb4d8502Sjsg else
5970fb4d8502Sjsg pp_state = PP_STATE_LS;
5971fb4d8502Sjsg msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5972fb4d8502Sjsg PP_BLOCK_GFX_CP,
5973fb4d8502Sjsg pp_support_state,
5974fb4d8502Sjsg pp_state);
5975fb4d8502Sjsg amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5976fb4d8502Sjsg }
5977fb4d8502Sjsg
5978fb4d8502Sjsg return 0;
5979fb4d8502Sjsg }
5980fb4d8502Sjsg
gfx_v8_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)5981fb4d8502Sjsg static int gfx_v8_0_set_clockgating_state(void *handle,
5982fb4d8502Sjsg enum amd_clockgating_state state)
5983fb4d8502Sjsg {
5984fb4d8502Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5985fb4d8502Sjsg
5986fb4d8502Sjsg if (amdgpu_sriov_vf(adev))
5987fb4d8502Sjsg return 0;
5988fb4d8502Sjsg
5989fb4d8502Sjsg switch (adev->asic_type) {
5990fb4d8502Sjsg case CHIP_FIJI:
5991fb4d8502Sjsg case CHIP_CARRIZO:
5992fb4d8502Sjsg case CHIP_STONEY:
5993fb4d8502Sjsg gfx_v8_0_update_gfx_clock_gating(adev,
5994fb4d8502Sjsg state == AMD_CG_STATE_GATE);
5995fb4d8502Sjsg break;
5996fb4d8502Sjsg case CHIP_TONGA:
5997fb4d8502Sjsg gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
5998fb4d8502Sjsg break;
5999fb4d8502Sjsg case CHIP_POLARIS10:
6000fb4d8502Sjsg case CHIP_POLARIS11:
6001fb4d8502Sjsg case CHIP_POLARIS12:
6002fb4d8502Sjsg case CHIP_VEGAM:
6003fb4d8502Sjsg gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
6004fb4d8502Sjsg break;
6005fb4d8502Sjsg default:
6006fb4d8502Sjsg break;
6007fb4d8502Sjsg }
6008fb4d8502Sjsg return 0;
6009fb4d8502Sjsg }
6010fb4d8502Sjsg
gfx_v8_0_ring_get_rptr(struct amdgpu_ring * ring)6011fb4d8502Sjsg static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
6012fb4d8502Sjsg {
60131bb76ff1Sjsg return *ring->rptr_cpu_addr;
6014fb4d8502Sjsg }
6015fb4d8502Sjsg
gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)6016fb4d8502Sjsg static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
6017fb4d8502Sjsg {
6018fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
6019fb4d8502Sjsg
6020fb4d8502Sjsg if (ring->use_doorbell)
6021fb4d8502Sjsg /* XXX check if swapping is necessary on BE */
60221bb76ff1Sjsg return *ring->wptr_cpu_addr;
6023fb4d8502Sjsg else
6024fb4d8502Sjsg return RREG32(mmCP_RB0_WPTR);
6025fb4d8502Sjsg }
6026fb4d8502Sjsg
gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)6027fb4d8502Sjsg static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
6028fb4d8502Sjsg {
6029fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
6030fb4d8502Sjsg
6031fb4d8502Sjsg if (ring->use_doorbell) {
6032fb4d8502Sjsg /* XXX check if swapping is necessary on BE */
60331bb76ff1Sjsg *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
6034fb4d8502Sjsg WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6035fb4d8502Sjsg } else {
6036fb4d8502Sjsg WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6037fb4d8502Sjsg (void)RREG32(mmCP_RB0_WPTR);
6038fb4d8502Sjsg }
6039fb4d8502Sjsg }
6040fb4d8502Sjsg
gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)6041fb4d8502Sjsg static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6042fb4d8502Sjsg {
6043fb4d8502Sjsg u32 ref_and_mask, reg_mem_engine;
6044fb4d8502Sjsg
6045fb4d8502Sjsg if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||
6046fb4d8502Sjsg (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {
6047fb4d8502Sjsg switch (ring->me) {
6048fb4d8502Sjsg case 1:
6049fb4d8502Sjsg ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6050fb4d8502Sjsg break;
6051fb4d8502Sjsg case 2:
6052fb4d8502Sjsg ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6053fb4d8502Sjsg break;
6054fb4d8502Sjsg default:
6055fb4d8502Sjsg return;
6056fb4d8502Sjsg }
6057fb4d8502Sjsg reg_mem_engine = 0;
6058fb4d8502Sjsg } else {
6059fb4d8502Sjsg ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6060fb4d8502Sjsg reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
6061fb4d8502Sjsg }
6062fb4d8502Sjsg
6063fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6064fb4d8502Sjsg amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
6065fb4d8502Sjsg WAIT_REG_MEM_FUNCTION(3) | /* == */
6066fb4d8502Sjsg reg_mem_engine));
6067fb4d8502Sjsg amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
6068fb4d8502Sjsg amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
6069fb4d8502Sjsg amdgpu_ring_write(ring, ref_and_mask);
6070fb4d8502Sjsg amdgpu_ring_write(ring, ref_and_mask);
6071fb4d8502Sjsg amdgpu_ring_write(ring, 0x20); /* poll interval */
6072fb4d8502Sjsg }
6073fb4d8502Sjsg
gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring * ring)6074fb4d8502Sjsg static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6075fb4d8502Sjsg {
6076fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6077fb4d8502Sjsg amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6078fb4d8502Sjsg EVENT_INDEX(4));
6079fb4d8502Sjsg
6080fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6081fb4d8502Sjsg amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6082fb4d8502Sjsg EVENT_INDEX(0));
6083fb4d8502Sjsg }
6084fb4d8502Sjsg
gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)6085fb4d8502Sjsg static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6086c349dbc7Sjsg struct amdgpu_job *job,
6087fb4d8502Sjsg struct amdgpu_ib *ib,
6088c349dbc7Sjsg uint32_t flags)
6089fb4d8502Sjsg {
6090c349dbc7Sjsg unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6091fb4d8502Sjsg u32 header, control = 0;
6092fb4d8502Sjsg
6093fb4d8502Sjsg if (ib->flags & AMDGPU_IB_FLAG_CE)
6094fb4d8502Sjsg header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
6095fb4d8502Sjsg else
6096fb4d8502Sjsg header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6097fb4d8502Sjsg
6098fb4d8502Sjsg control |= ib->length_dw | (vmid << 24);
6099fb4d8502Sjsg
6100fb4d8502Sjsg if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6101fb4d8502Sjsg control |= INDIRECT_BUFFER_PRE_ENB(1);
6102fb4d8502Sjsg
6103c349dbc7Sjsg if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
6104fb4d8502Sjsg gfx_v8_0_ring_emit_de_meta(ring);
6105fb4d8502Sjsg }
6106fb4d8502Sjsg
6107fb4d8502Sjsg amdgpu_ring_write(ring, header);
6108fb4d8502Sjsg amdgpu_ring_write(ring,
6109fb4d8502Sjsg #ifdef __BIG_ENDIAN
6110fb4d8502Sjsg (2 << 0) |
6111fb4d8502Sjsg #endif
6112fb4d8502Sjsg (ib->gpu_addr & 0xFFFFFFFC));
6113fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6114fb4d8502Sjsg amdgpu_ring_write(ring, control);
6115fb4d8502Sjsg }
6116fb4d8502Sjsg
gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)6117fb4d8502Sjsg static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6118c349dbc7Sjsg struct amdgpu_job *job,
6119fb4d8502Sjsg struct amdgpu_ib *ib,
6120c349dbc7Sjsg uint32_t flags)
6121fb4d8502Sjsg {
6122c349dbc7Sjsg unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6123fb4d8502Sjsg u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6124fb4d8502Sjsg
6125c349dbc7Sjsg /* Currently, there is a high possibility to get wave ID mismatch
6126c349dbc7Sjsg * between ME and GDS, leading to a hw deadlock, because ME generates
6127c349dbc7Sjsg * different wave IDs than the GDS expects. This situation happens
6128c349dbc7Sjsg * randomly when at least 5 compute pipes use GDS ordered append.
6129c349dbc7Sjsg * The wave IDs generated by ME are also wrong after suspend/resume.
6130c349dbc7Sjsg * Those are probably bugs somewhere else in the kernel driver.
6131c349dbc7Sjsg *
6132c349dbc7Sjsg * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
6133c349dbc7Sjsg * GDS to 0 for this ring (me/pipe).
6134c349dbc7Sjsg */
6135c349dbc7Sjsg if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
6136c349dbc7Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
6137c349dbc7Sjsg amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
6138c349dbc7Sjsg amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
6139c349dbc7Sjsg }
6140c349dbc7Sjsg
6141fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6142fb4d8502Sjsg amdgpu_ring_write(ring,
6143fb4d8502Sjsg #ifdef __BIG_ENDIAN
6144fb4d8502Sjsg (2 << 0) |
6145fb4d8502Sjsg #endif
6146fb4d8502Sjsg (ib->gpu_addr & 0xFFFFFFFC));
6147fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6148fb4d8502Sjsg amdgpu_ring_write(ring, control);
6149fb4d8502Sjsg }
6150fb4d8502Sjsg
gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)6151fb4d8502Sjsg static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
6152fb4d8502Sjsg u64 seq, unsigned flags)
6153fb4d8502Sjsg {
6154fb4d8502Sjsg bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6155fb4d8502Sjsg bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6156fb4d8502Sjsg
615792675d14Sjsg /* Workaround for cache flush problems. First send a dummy EOP
615892675d14Sjsg * event down the pipe with seq one below.
615992675d14Sjsg */
616092675d14Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
616192675d14Sjsg amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
616292675d14Sjsg EOP_TC_ACTION_EN |
616392675d14Sjsg EOP_TC_WB_ACTION_EN |
616492675d14Sjsg EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
616592675d14Sjsg EVENT_INDEX(5)));
616692675d14Sjsg amdgpu_ring_write(ring, addr & 0xfffffffc);
616792675d14Sjsg amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
616892675d14Sjsg DATA_SEL(1) | INT_SEL(0));
616992675d14Sjsg amdgpu_ring_write(ring, lower_32_bits(seq - 1));
617092675d14Sjsg amdgpu_ring_write(ring, upper_32_bits(seq - 1));
617192675d14Sjsg
617292675d14Sjsg /* Then send the real EOP event down the pipe:
617392675d14Sjsg * EVENT_WRITE_EOP - flush caches, send int */
6174fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6175fb4d8502Sjsg amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6176fb4d8502Sjsg EOP_TC_ACTION_EN |
6177fb4d8502Sjsg EOP_TC_WB_ACTION_EN |
6178fb4d8502Sjsg EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6179fb4d8502Sjsg EVENT_INDEX(5)));
6180fb4d8502Sjsg amdgpu_ring_write(ring, addr & 0xfffffffc);
6181fb4d8502Sjsg amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6182fb4d8502Sjsg DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6183fb4d8502Sjsg amdgpu_ring_write(ring, lower_32_bits(seq));
6184fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(seq));
6185fb4d8502Sjsg
6186fb4d8502Sjsg }
6187fb4d8502Sjsg
gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)6188fb4d8502Sjsg static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6189fb4d8502Sjsg {
6190fb4d8502Sjsg int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6191fb4d8502Sjsg uint32_t seq = ring->fence_drv.sync_seq;
6192fb4d8502Sjsg uint64_t addr = ring->fence_drv.gpu_addr;
6193fb4d8502Sjsg
6194fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6195fb4d8502Sjsg amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
6196fb4d8502Sjsg WAIT_REG_MEM_FUNCTION(3) | /* equal */
6197fb4d8502Sjsg WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
6198fb4d8502Sjsg amdgpu_ring_write(ring, addr & 0xfffffffc);
6199fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6200fb4d8502Sjsg amdgpu_ring_write(ring, seq);
6201fb4d8502Sjsg amdgpu_ring_write(ring, 0xffffffff);
6202fb4d8502Sjsg amdgpu_ring_write(ring, 4); /* poll interval */
6203fb4d8502Sjsg }
6204fb4d8502Sjsg
gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)6205fb4d8502Sjsg static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6206fb4d8502Sjsg unsigned vmid, uint64_t pd_addr)
6207fb4d8502Sjsg {
6208fb4d8502Sjsg int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6209fb4d8502Sjsg
6210fb4d8502Sjsg amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6211fb4d8502Sjsg
6212fb4d8502Sjsg /* wait for the invalidate to complete */
6213fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6214fb4d8502Sjsg amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6215fb4d8502Sjsg WAIT_REG_MEM_FUNCTION(0) | /* always */
6216fb4d8502Sjsg WAIT_REG_MEM_ENGINE(0))); /* me */
6217fb4d8502Sjsg amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6218fb4d8502Sjsg amdgpu_ring_write(ring, 0);
6219fb4d8502Sjsg amdgpu_ring_write(ring, 0); /* ref */
6220fb4d8502Sjsg amdgpu_ring_write(ring, 0); /* mask */
6221fb4d8502Sjsg amdgpu_ring_write(ring, 0x20); /* poll interval */
6222fb4d8502Sjsg
6223fb4d8502Sjsg /* compute doesn't have PFP */
6224fb4d8502Sjsg if (usepfp) {
6225fb4d8502Sjsg /* sync PFP to ME, otherwise we might get invalid PFP reads */
6226fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6227fb4d8502Sjsg amdgpu_ring_write(ring, 0x0);
6228fb4d8502Sjsg }
6229fb4d8502Sjsg }
6230fb4d8502Sjsg
gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring * ring)6231fb4d8502Sjsg static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6232fb4d8502Sjsg {
62331bb76ff1Sjsg return *ring->wptr_cpu_addr;
6234fb4d8502Sjsg }
6235fb4d8502Sjsg
gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring * ring)6236fb4d8502Sjsg static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6237fb4d8502Sjsg {
6238fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
6239fb4d8502Sjsg
6240fb4d8502Sjsg /* XXX check if swapping is necessary on BE */
62411bb76ff1Sjsg *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
6242fb4d8502Sjsg WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6243fb4d8502Sjsg }
6244fb4d8502Sjsg
gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)6245fb4d8502Sjsg static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6246fb4d8502Sjsg u64 addr, u64 seq,
6247fb4d8502Sjsg unsigned flags)
6248fb4d8502Sjsg {
6249fb4d8502Sjsg bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6250fb4d8502Sjsg bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6251fb4d8502Sjsg
6252fb4d8502Sjsg /* RELEASE_MEM - flush caches, send int */
6253fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6254fb4d8502Sjsg amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6255fb4d8502Sjsg EOP_TC_ACTION_EN |
6256fb4d8502Sjsg EOP_TC_WB_ACTION_EN |
6257fb4d8502Sjsg EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6258fb4d8502Sjsg EVENT_INDEX(5)));
6259fb4d8502Sjsg amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6260fb4d8502Sjsg amdgpu_ring_write(ring, addr & 0xfffffffc);
6261fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(addr));
6262fb4d8502Sjsg amdgpu_ring_write(ring, lower_32_bits(seq));
6263fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(seq));
6264fb4d8502Sjsg }
6265fb4d8502Sjsg
gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)6266fb4d8502Sjsg static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
6267fb4d8502Sjsg u64 seq, unsigned int flags)
6268fb4d8502Sjsg {
6269fb4d8502Sjsg /* we only allocate 32bit for each seq wb address */
6270fb4d8502Sjsg BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
6271fb4d8502Sjsg
6272fb4d8502Sjsg /* write fence seq to the "addr" */
6273fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6274fb4d8502Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6275fb4d8502Sjsg WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
6276fb4d8502Sjsg amdgpu_ring_write(ring, lower_32_bits(addr));
6277fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(addr));
6278fb4d8502Sjsg amdgpu_ring_write(ring, lower_32_bits(seq));
6279fb4d8502Sjsg
6280fb4d8502Sjsg if (flags & AMDGPU_FENCE_FLAG_INT) {
6281fb4d8502Sjsg /* set register to trigger INT */
6282fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6283fb4d8502Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6284fb4d8502Sjsg WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
6285fb4d8502Sjsg amdgpu_ring_write(ring, mmCPC_INT_STATUS);
6286fb4d8502Sjsg amdgpu_ring_write(ring, 0);
6287fb4d8502Sjsg amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
6288fb4d8502Sjsg }
6289fb4d8502Sjsg }
6290fb4d8502Sjsg
gfx_v8_ring_emit_sb(struct amdgpu_ring * ring)6291fb4d8502Sjsg static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6292fb4d8502Sjsg {
6293fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6294fb4d8502Sjsg amdgpu_ring_write(ring, 0);
6295fb4d8502Sjsg }
6296fb4d8502Sjsg
gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)6297fb4d8502Sjsg static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6298fb4d8502Sjsg {
6299fb4d8502Sjsg uint32_t dw2 = 0;
6300fb4d8502Sjsg
6301fb4d8502Sjsg if (amdgpu_sriov_vf(ring->adev))
6302fb4d8502Sjsg gfx_v8_0_ring_emit_ce_meta(ring);
6303fb4d8502Sjsg
6304fb4d8502Sjsg dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6305fb4d8502Sjsg if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6306fb4d8502Sjsg gfx_v8_0_ring_emit_vgt_flush(ring);
6307fb4d8502Sjsg /* set load_global_config & load_global_uconfig */
6308fb4d8502Sjsg dw2 |= 0x8001;
6309fb4d8502Sjsg /* set load_cs_sh_regs */
6310fb4d8502Sjsg dw2 |= 0x01000000;
6311fb4d8502Sjsg /* set load_per_context_state & load_gfx_sh_regs for GFX */
6312fb4d8502Sjsg dw2 |= 0x10002;
6313fb4d8502Sjsg
6314fb4d8502Sjsg /* set load_ce_ram if preamble presented */
6315fb4d8502Sjsg if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6316fb4d8502Sjsg dw2 |= 0x10000000;
6317fb4d8502Sjsg } else {
6318fb4d8502Sjsg /* still load_ce_ram if this is the first time preamble presented
6319fb4d8502Sjsg * although there is no context switch happens.
6320fb4d8502Sjsg */
6321fb4d8502Sjsg if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6322fb4d8502Sjsg dw2 |= 0x10000000;
6323fb4d8502Sjsg }
6324fb4d8502Sjsg
6325fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6326fb4d8502Sjsg amdgpu_ring_write(ring, dw2);
6327fb4d8502Sjsg amdgpu_ring_write(ring, 0);
6328fb4d8502Sjsg }
6329fb4d8502Sjsg
gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring)6330fb4d8502Sjsg static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
6331fb4d8502Sjsg {
6332fb4d8502Sjsg unsigned ret;
6333fb4d8502Sjsg
6334fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
6335fb4d8502Sjsg amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
6336fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
6337fb4d8502Sjsg amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
6338fb4d8502Sjsg ret = ring->wptr & ring->buf_mask;
6339fb4d8502Sjsg amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
6340fb4d8502Sjsg return ret;
6341fb4d8502Sjsg }
6342fb4d8502Sjsg
gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)6343fb4d8502Sjsg static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
6344fb4d8502Sjsg {
6345fb4d8502Sjsg unsigned cur;
6346fb4d8502Sjsg
6347fb4d8502Sjsg BUG_ON(offset > ring->buf_mask);
6348fb4d8502Sjsg BUG_ON(ring->ring[offset] != 0x55aa55aa);
6349fb4d8502Sjsg
6350fb4d8502Sjsg cur = (ring->wptr & ring->buf_mask) - 1;
6351fb4d8502Sjsg if (likely(cur > offset))
6352fb4d8502Sjsg ring->ring[offset] = cur - offset;
6353fb4d8502Sjsg else
6354fb4d8502Sjsg ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
6355fb4d8502Sjsg }
6356fb4d8502Sjsg
gfx_v8_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)6357ad8b1aafSjsg static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
6358ad8b1aafSjsg uint32_t reg_val_offs)
6359fb4d8502Sjsg {
6360fb4d8502Sjsg struct amdgpu_device *adev = ring->adev;
6361fb4d8502Sjsg
6362fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6363fb4d8502Sjsg amdgpu_ring_write(ring, 0 | /* src: register*/
6364fb4d8502Sjsg (5 << 8) | /* dst: memory */
6365fb4d8502Sjsg (1 << 20)); /* write confirm */
6366fb4d8502Sjsg amdgpu_ring_write(ring, reg);
6367fb4d8502Sjsg amdgpu_ring_write(ring, 0);
6368fb4d8502Sjsg amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6369ad8b1aafSjsg reg_val_offs * 4));
6370fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6371ad8b1aafSjsg reg_val_offs * 4));
6372fb4d8502Sjsg }
6373fb4d8502Sjsg
gfx_v8_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)6374fb4d8502Sjsg static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6375fb4d8502Sjsg uint32_t val)
6376fb4d8502Sjsg {
6377fb4d8502Sjsg uint32_t cmd;
6378fb4d8502Sjsg
6379fb4d8502Sjsg switch (ring->funcs->type) {
6380fb4d8502Sjsg case AMDGPU_RING_TYPE_GFX:
6381fb4d8502Sjsg cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6382fb4d8502Sjsg break;
6383fb4d8502Sjsg case AMDGPU_RING_TYPE_KIQ:
6384fb4d8502Sjsg cmd = 1 << 16; /* no inc addr */
6385fb4d8502Sjsg break;
6386fb4d8502Sjsg default:
6387fb4d8502Sjsg cmd = WR_CONFIRM;
6388fb4d8502Sjsg break;
6389fb4d8502Sjsg }
6390fb4d8502Sjsg
6391fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6392fb4d8502Sjsg amdgpu_ring_write(ring, cmd);
6393fb4d8502Sjsg amdgpu_ring_write(ring, reg);
6394fb4d8502Sjsg amdgpu_ring_write(ring, 0);
6395fb4d8502Sjsg amdgpu_ring_write(ring, val);
6396fb4d8502Sjsg }
6397fb4d8502Sjsg
gfx_v8_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned vmid)6398c349dbc7Sjsg static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
6399c349dbc7Sjsg {
6400c349dbc7Sjsg struct amdgpu_device *adev = ring->adev;
6401c349dbc7Sjsg uint32_t value = 0;
6402c349dbc7Sjsg
6403c349dbc7Sjsg value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6404c349dbc7Sjsg value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6405c349dbc7Sjsg value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6406c349dbc7Sjsg value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6407c349dbc7Sjsg WREG32(mmSQ_CMD, value);
6408c349dbc7Sjsg }
6409c349dbc7Sjsg
gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,enum amdgpu_interrupt_state state)6410fb4d8502Sjsg static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6411fb4d8502Sjsg enum amdgpu_interrupt_state state)
6412fb4d8502Sjsg {
6413fb4d8502Sjsg WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6414fb4d8502Sjsg state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6415fb4d8502Sjsg }
6416fb4d8502Sjsg
gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)6417fb4d8502Sjsg static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6418fb4d8502Sjsg int me, int pipe,
6419fb4d8502Sjsg enum amdgpu_interrupt_state state)
6420fb4d8502Sjsg {
6421fb4d8502Sjsg u32 mec_int_cntl, mec_int_cntl_reg;
6422fb4d8502Sjsg
6423fb4d8502Sjsg /*
6424fb4d8502Sjsg * amdgpu controls only the first MEC. That's why this function only
6425fb4d8502Sjsg * handles the setting of interrupts for this specific MEC. All other
6426fb4d8502Sjsg * pipes' interrupts are set by amdkfd.
6427fb4d8502Sjsg */
6428fb4d8502Sjsg
6429fb4d8502Sjsg if (me == 1) {
6430fb4d8502Sjsg switch (pipe) {
6431fb4d8502Sjsg case 0:
6432fb4d8502Sjsg mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6433fb4d8502Sjsg break;
6434fb4d8502Sjsg case 1:
6435fb4d8502Sjsg mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6436fb4d8502Sjsg break;
6437fb4d8502Sjsg case 2:
6438fb4d8502Sjsg mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6439fb4d8502Sjsg break;
6440fb4d8502Sjsg case 3:
6441fb4d8502Sjsg mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6442fb4d8502Sjsg break;
6443fb4d8502Sjsg default:
6444fb4d8502Sjsg DRM_DEBUG("invalid pipe %d\n", pipe);
6445fb4d8502Sjsg return;
6446fb4d8502Sjsg }
6447fb4d8502Sjsg } else {
6448fb4d8502Sjsg DRM_DEBUG("invalid me %d\n", me);
6449fb4d8502Sjsg return;
6450fb4d8502Sjsg }
6451fb4d8502Sjsg
6452fb4d8502Sjsg switch (state) {
6453fb4d8502Sjsg case AMDGPU_IRQ_STATE_DISABLE:
6454fb4d8502Sjsg mec_int_cntl = RREG32(mec_int_cntl_reg);
6455fb4d8502Sjsg mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6456fb4d8502Sjsg WREG32(mec_int_cntl_reg, mec_int_cntl);
6457fb4d8502Sjsg break;
6458fb4d8502Sjsg case AMDGPU_IRQ_STATE_ENABLE:
6459fb4d8502Sjsg mec_int_cntl = RREG32(mec_int_cntl_reg);
6460fb4d8502Sjsg mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6461fb4d8502Sjsg WREG32(mec_int_cntl_reg, mec_int_cntl);
6462fb4d8502Sjsg break;
6463fb4d8502Sjsg default:
6464fb4d8502Sjsg break;
6465fb4d8502Sjsg }
6466fb4d8502Sjsg }
6467fb4d8502Sjsg
gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)6468fb4d8502Sjsg static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6469fb4d8502Sjsg struct amdgpu_irq_src *source,
6470fb4d8502Sjsg unsigned type,
6471fb4d8502Sjsg enum amdgpu_interrupt_state state)
6472fb4d8502Sjsg {
6473fb4d8502Sjsg WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6474fb4d8502Sjsg state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6475fb4d8502Sjsg
6476fb4d8502Sjsg return 0;
6477fb4d8502Sjsg }
6478fb4d8502Sjsg
gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)6479fb4d8502Sjsg static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6480fb4d8502Sjsg struct amdgpu_irq_src *source,
6481fb4d8502Sjsg unsigned type,
6482fb4d8502Sjsg enum amdgpu_interrupt_state state)
6483fb4d8502Sjsg {
6484fb4d8502Sjsg WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6485fb4d8502Sjsg state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6486fb4d8502Sjsg
6487fb4d8502Sjsg return 0;
6488fb4d8502Sjsg }
6489fb4d8502Sjsg
gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)6490fb4d8502Sjsg static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6491fb4d8502Sjsg struct amdgpu_irq_src *src,
6492fb4d8502Sjsg unsigned type,
6493fb4d8502Sjsg enum amdgpu_interrupt_state state)
6494fb4d8502Sjsg {
6495fb4d8502Sjsg switch (type) {
6496c349dbc7Sjsg case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
6497fb4d8502Sjsg gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6498fb4d8502Sjsg break;
6499fb4d8502Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6500fb4d8502Sjsg gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6501fb4d8502Sjsg break;
6502fb4d8502Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6503fb4d8502Sjsg gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6504fb4d8502Sjsg break;
6505fb4d8502Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6506fb4d8502Sjsg gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6507fb4d8502Sjsg break;
6508fb4d8502Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6509fb4d8502Sjsg gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6510fb4d8502Sjsg break;
6511fb4d8502Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6512fb4d8502Sjsg gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6513fb4d8502Sjsg break;
6514fb4d8502Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6515fb4d8502Sjsg gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6516fb4d8502Sjsg break;
6517fb4d8502Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6518fb4d8502Sjsg gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6519fb4d8502Sjsg break;
6520fb4d8502Sjsg case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6521fb4d8502Sjsg gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6522fb4d8502Sjsg break;
6523fb4d8502Sjsg default:
6524fb4d8502Sjsg break;
6525fb4d8502Sjsg }
6526fb4d8502Sjsg return 0;
6527fb4d8502Sjsg }
6528fb4d8502Sjsg
gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)6529fb4d8502Sjsg static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev,
6530fb4d8502Sjsg struct amdgpu_irq_src *source,
6531fb4d8502Sjsg unsigned int type,
6532fb4d8502Sjsg enum amdgpu_interrupt_state state)
6533fb4d8502Sjsg {
6534fb4d8502Sjsg int enable_flag;
6535fb4d8502Sjsg
6536fb4d8502Sjsg switch (state) {
6537fb4d8502Sjsg case AMDGPU_IRQ_STATE_DISABLE:
6538fb4d8502Sjsg enable_flag = 0;
6539fb4d8502Sjsg break;
6540fb4d8502Sjsg
6541fb4d8502Sjsg case AMDGPU_IRQ_STATE_ENABLE:
6542fb4d8502Sjsg enable_flag = 1;
6543fb4d8502Sjsg break;
6544fb4d8502Sjsg
6545fb4d8502Sjsg default:
6546fb4d8502Sjsg return -EINVAL;
6547fb4d8502Sjsg }
6548fb4d8502Sjsg
6549fb4d8502Sjsg WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6550fb4d8502Sjsg WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6551fb4d8502Sjsg WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6552fb4d8502Sjsg WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6553fb4d8502Sjsg WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6554fb4d8502Sjsg WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6555fb4d8502Sjsg enable_flag);
6556fb4d8502Sjsg WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6557fb4d8502Sjsg enable_flag);
6558fb4d8502Sjsg WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6559fb4d8502Sjsg enable_flag);
6560fb4d8502Sjsg WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6561fb4d8502Sjsg enable_flag);
6562fb4d8502Sjsg WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6563fb4d8502Sjsg enable_flag);
6564fb4d8502Sjsg WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6565fb4d8502Sjsg enable_flag);
6566fb4d8502Sjsg WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6567fb4d8502Sjsg enable_flag);
6568fb4d8502Sjsg WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6569fb4d8502Sjsg enable_flag);
6570fb4d8502Sjsg
6571fb4d8502Sjsg return 0;
6572fb4d8502Sjsg }
6573fb4d8502Sjsg
gfx_v8_0_set_sq_int_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)6574fb4d8502Sjsg static int gfx_v8_0_set_sq_int_state(struct amdgpu_device *adev,
6575fb4d8502Sjsg struct amdgpu_irq_src *source,
6576fb4d8502Sjsg unsigned int type,
6577fb4d8502Sjsg enum amdgpu_interrupt_state state)
6578fb4d8502Sjsg {
6579fb4d8502Sjsg int enable_flag;
6580fb4d8502Sjsg
6581fb4d8502Sjsg switch (state) {
6582fb4d8502Sjsg case AMDGPU_IRQ_STATE_DISABLE:
6583fb4d8502Sjsg enable_flag = 1;
6584fb4d8502Sjsg break;
6585fb4d8502Sjsg
6586fb4d8502Sjsg case AMDGPU_IRQ_STATE_ENABLE:
6587fb4d8502Sjsg enable_flag = 0;
6588fb4d8502Sjsg break;
6589fb4d8502Sjsg
6590fb4d8502Sjsg default:
6591fb4d8502Sjsg return -EINVAL;
6592fb4d8502Sjsg }
6593fb4d8502Sjsg
6594fb4d8502Sjsg WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,
6595fb4d8502Sjsg enable_flag);
6596fb4d8502Sjsg
6597fb4d8502Sjsg return 0;
6598fb4d8502Sjsg }
6599fb4d8502Sjsg
gfx_v8_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6600fb4d8502Sjsg static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6601fb4d8502Sjsg struct amdgpu_irq_src *source,
6602fb4d8502Sjsg struct amdgpu_iv_entry *entry)
6603fb4d8502Sjsg {
6604fb4d8502Sjsg int i;
6605fb4d8502Sjsg u8 me_id, pipe_id, queue_id;
6606fb4d8502Sjsg struct amdgpu_ring *ring;
6607fb4d8502Sjsg
6608fb4d8502Sjsg DRM_DEBUG("IH: CP EOP\n");
6609fb4d8502Sjsg me_id = (entry->ring_id & 0x0c) >> 2;
6610fb4d8502Sjsg pipe_id = (entry->ring_id & 0x03) >> 0;
6611fb4d8502Sjsg queue_id = (entry->ring_id & 0x70) >> 4;
6612fb4d8502Sjsg
6613fb4d8502Sjsg switch (me_id) {
6614fb4d8502Sjsg case 0:
6615fb4d8502Sjsg amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6616fb4d8502Sjsg break;
6617fb4d8502Sjsg case 1:
6618fb4d8502Sjsg case 2:
6619fb4d8502Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6620fb4d8502Sjsg ring = &adev->gfx.compute_ring[i];
6621fb4d8502Sjsg /* Per-queue interrupt is supported for MEC starting from VI.
6622fb4d8502Sjsg * The interrupt can only be enabled/disabled per pipe instead of per queue.
6623fb4d8502Sjsg */
6624fb4d8502Sjsg if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6625fb4d8502Sjsg amdgpu_fence_process(ring);
6626fb4d8502Sjsg }
6627fb4d8502Sjsg break;
6628fb4d8502Sjsg }
6629fb4d8502Sjsg return 0;
6630fb4d8502Sjsg }
6631fb4d8502Sjsg
gfx_v8_0_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)6632c349dbc7Sjsg static void gfx_v8_0_fault(struct amdgpu_device *adev,
6633c349dbc7Sjsg struct amdgpu_iv_entry *entry)
6634c349dbc7Sjsg {
6635c349dbc7Sjsg u8 me_id, pipe_id, queue_id;
6636c349dbc7Sjsg struct amdgpu_ring *ring;
6637c349dbc7Sjsg int i;
6638c349dbc7Sjsg
6639c349dbc7Sjsg me_id = (entry->ring_id & 0x0c) >> 2;
6640c349dbc7Sjsg pipe_id = (entry->ring_id & 0x03) >> 0;
6641c349dbc7Sjsg queue_id = (entry->ring_id & 0x70) >> 4;
6642c349dbc7Sjsg
6643c349dbc7Sjsg switch (me_id) {
6644c349dbc7Sjsg case 0:
6645c349dbc7Sjsg drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
6646c349dbc7Sjsg break;
6647c349dbc7Sjsg case 1:
6648c349dbc7Sjsg case 2:
6649c349dbc7Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6650c349dbc7Sjsg ring = &adev->gfx.compute_ring[i];
6651c349dbc7Sjsg if (ring->me == me_id && ring->pipe == pipe_id &&
6652c349dbc7Sjsg ring->queue == queue_id)
6653c349dbc7Sjsg drm_sched_fault(&ring->sched);
6654c349dbc7Sjsg }
6655c349dbc7Sjsg break;
6656c349dbc7Sjsg }
6657c349dbc7Sjsg }
6658c349dbc7Sjsg
gfx_v8_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6659fb4d8502Sjsg static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6660fb4d8502Sjsg struct amdgpu_irq_src *source,
6661fb4d8502Sjsg struct amdgpu_iv_entry *entry)
6662fb4d8502Sjsg {
6663fb4d8502Sjsg DRM_ERROR("Illegal register access in command stream\n");
6664c349dbc7Sjsg gfx_v8_0_fault(adev, entry);
6665fb4d8502Sjsg return 0;
6666fb4d8502Sjsg }
6667fb4d8502Sjsg
gfx_v8_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6668fb4d8502Sjsg static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6669fb4d8502Sjsg struct amdgpu_irq_src *source,
6670fb4d8502Sjsg struct amdgpu_iv_entry *entry)
6671fb4d8502Sjsg {
6672fb4d8502Sjsg DRM_ERROR("Illegal instruction in command stream\n");
6673c349dbc7Sjsg gfx_v8_0_fault(adev, entry);
6674fb4d8502Sjsg return 0;
6675fb4d8502Sjsg }
6676fb4d8502Sjsg
gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6677fb4d8502Sjsg static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev,
6678fb4d8502Sjsg struct amdgpu_irq_src *source,
6679fb4d8502Sjsg struct amdgpu_iv_entry *entry)
6680fb4d8502Sjsg {
6681fb4d8502Sjsg DRM_ERROR("CP EDC/ECC error detected.");
6682fb4d8502Sjsg return 0;
6683fb4d8502Sjsg }
6684fb4d8502Sjsg
gfx_v8_0_parse_sq_irq(struct amdgpu_device * adev,unsigned ih_data,bool from_wq)66855ca02815Sjsg static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data,
66865ca02815Sjsg bool from_wq)
6687fb4d8502Sjsg {
6688fb4d8502Sjsg u32 enc, se_id, sh_id, cu_id;
6689fb4d8502Sjsg char type[20];
6690fb4d8502Sjsg int sq_edc_source = -1;
6691fb4d8502Sjsg
6692fb4d8502Sjsg enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
6693fb4d8502Sjsg se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
6694fb4d8502Sjsg
6695fb4d8502Sjsg switch (enc) {
6696fb4d8502Sjsg case 0:
6697fb4d8502Sjsg DRM_INFO("SQ general purpose intr detected:"
6698fb4d8502Sjsg "se_id %d, immed_overflow %d, host_reg_overflow %d,"
6699fb4d8502Sjsg "host_cmd_overflow %d, cmd_timestamp %d,"
6700fb4d8502Sjsg "reg_timestamp %d, thread_trace_buff_full %d,"
6701fb4d8502Sjsg "wlt %d, thread_trace %d.\n",
6702fb4d8502Sjsg se_id,
6703fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
6704fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
6705fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
6706fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
6707fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
6708fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
6709fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
6710fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
6711fb4d8502Sjsg );
6712fb4d8502Sjsg break;
6713fb4d8502Sjsg case 1:
6714fb4d8502Sjsg case 2:
6715fb4d8502Sjsg
6716fb4d8502Sjsg cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
6717fb4d8502Sjsg sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
6718fb4d8502Sjsg
6719fb4d8502Sjsg /*
6720fb4d8502Sjsg * This function can be called either directly from ISR
6721fb4d8502Sjsg * or from BH in which case we can access SQ_EDC_INFO
6722fb4d8502Sjsg * instance
6723fb4d8502Sjsg */
67245ca02815Sjsg if (from_wq) {
6725fb4d8502Sjsg mutex_lock(&adev->grbm_idx_mutex);
6726*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id, 0);
6727fb4d8502Sjsg
6728fb4d8502Sjsg sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
6729fb4d8502Sjsg
6730*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
6731fb4d8502Sjsg mutex_unlock(&adev->grbm_idx_mutex);
6732fb4d8502Sjsg }
6733fb4d8502Sjsg
6734fb4d8502Sjsg if (enc == 1)
6735fb4d8502Sjsg snprintf(type, sizeof(type), "instruction intr");
6736fb4d8502Sjsg else
6737fb4d8502Sjsg snprintf(type, sizeof(type), "EDC/ECC error");
6738fb4d8502Sjsg
6739fb4d8502Sjsg DRM_INFO(
6740fb4d8502Sjsg "SQ %s detected: "
6741fb4d8502Sjsg "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d "
6742fb4d8502Sjsg "trap %s, sq_ed_info.source %s.\n",
6743fb4d8502Sjsg type, se_id, sh_id, cu_id,
6744fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
6745fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
6746fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
6747fb4d8502Sjsg REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
6748fb4d8502Sjsg (sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable"
6749fb4d8502Sjsg );
6750fb4d8502Sjsg break;
6751fb4d8502Sjsg default:
6752fb4d8502Sjsg DRM_ERROR("SQ invalid encoding type\n.");
6753fb4d8502Sjsg }
6754fb4d8502Sjsg }
6755fb4d8502Sjsg
gfx_v8_0_sq_irq_work_func(struct work_struct * work)6756fb4d8502Sjsg static void gfx_v8_0_sq_irq_work_func(struct work_struct *work)
6757fb4d8502Sjsg {
6758fb4d8502Sjsg
6759fb4d8502Sjsg struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work);
6760fb4d8502Sjsg struct sq_work *sq_work = container_of(work, struct sq_work, work);
6761fb4d8502Sjsg
67625ca02815Sjsg gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data, true);
6763fb4d8502Sjsg }
6764fb4d8502Sjsg
gfx_v8_0_sq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6765fb4d8502Sjsg static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
6766fb4d8502Sjsg struct amdgpu_irq_src *source,
6767fb4d8502Sjsg struct amdgpu_iv_entry *entry)
6768fb4d8502Sjsg {
6769fb4d8502Sjsg unsigned ih_data = entry->src_data[0];
6770fb4d8502Sjsg
6771fb4d8502Sjsg /*
6772fb4d8502Sjsg * Try to submit work so SQ_EDC_INFO can be accessed from
6773fb4d8502Sjsg * BH. If previous work submission hasn't finished yet
6774fb4d8502Sjsg * just print whatever info is possible directly from the ISR.
6775fb4d8502Sjsg */
6776fb4d8502Sjsg if (work_pending(&adev->gfx.sq_work.work)) {
67775ca02815Sjsg gfx_v8_0_parse_sq_irq(adev, ih_data, false);
6778fb4d8502Sjsg } else {
6779fb4d8502Sjsg adev->gfx.sq_work.ih_data = ih_data;
6780fb4d8502Sjsg schedule_work(&adev->gfx.sq_work.work);
6781fb4d8502Sjsg }
6782fb4d8502Sjsg
6783fb4d8502Sjsg return 0;
6784fb4d8502Sjsg }
6785fb4d8502Sjsg
gfx_v8_0_emit_mem_sync(struct amdgpu_ring * ring)6786ad8b1aafSjsg static void gfx_v8_0_emit_mem_sync(struct amdgpu_ring *ring)
6787ad8b1aafSjsg {
6788ad8b1aafSjsg amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
6789ad8b1aafSjsg amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6790ad8b1aafSjsg PACKET3_TC_ACTION_ENA |
6791ad8b1aafSjsg PACKET3_SH_KCACHE_ACTION_ENA |
6792ad8b1aafSjsg PACKET3_SH_ICACHE_ACTION_ENA |
6793ad8b1aafSjsg PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6794ad8b1aafSjsg amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6795ad8b1aafSjsg amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6796ad8b1aafSjsg amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6797ad8b1aafSjsg }
6798ad8b1aafSjsg
gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring * ring)6799ad8b1aafSjsg static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
6800ad8b1aafSjsg {
6801ad8b1aafSjsg amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
6802ad8b1aafSjsg amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6803ad8b1aafSjsg PACKET3_TC_ACTION_ENA |
6804ad8b1aafSjsg PACKET3_SH_KCACHE_ACTION_ENA |
6805ad8b1aafSjsg PACKET3_SH_ICACHE_ACTION_ENA |
6806ad8b1aafSjsg PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6807ad8b1aafSjsg amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6808ad8b1aafSjsg amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */
6809ad8b1aafSjsg amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6810ad8b1aafSjsg amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
6811ad8b1aafSjsg amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6812ad8b1aafSjsg }
6813ad8b1aafSjsg
68145ca02815Sjsg
68155ca02815Sjsg /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
68165ca02815Sjsg #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f
gfx_v8_0_emit_wave_limit_cs(struct amdgpu_ring * ring,uint32_t pipe,bool enable)68175ca02815Sjsg static void gfx_v8_0_emit_wave_limit_cs(struct amdgpu_ring *ring,
68185ca02815Sjsg uint32_t pipe, bool enable)
68195ca02815Sjsg {
68205ca02815Sjsg uint32_t val;
68215ca02815Sjsg uint32_t wcl_cs_reg;
68225ca02815Sjsg
68235ca02815Sjsg val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;
68245ca02815Sjsg
68255ca02815Sjsg switch (pipe) {
68265ca02815Sjsg case 0:
68275ca02815Sjsg wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0;
68285ca02815Sjsg break;
68295ca02815Sjsg case 1:
68305ca02815Sjsg wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1;
68315ca02815Sjsg break;
68325ca02815Sjsg case 2:
68335ca02815Sjsg wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2;
68345ca02815Sjsg break;
68355ca02815Sjsg case 3:
68365ca02815Sjsg wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3;
68375ca02815Sjsg break;
68385ca02815Sjsg default:
68395ca02815Sjsg DRM_DEBUG("invalid pipe %d\n", pipe);
68405ca02815Sjsg return;
68415ca02815Sjsg }
68425ca02815Sjsg
68435ca02815Sjsg amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
68445ca02815Sjsg
68455ca02815Sjsg }
68465ca02815Sjsg
68475ca02815Sjsg #define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
gfx_v8_0_emit_wave_limit(struct amdgpu_ring * ring,bool enable)68485ca02815Sjsg static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
68495ca02815Sjsg {
68505ca02815Sjsg struct amdgpu_device *adev = ring->adev;
68515ca02815Sjsg uint32_t val;
68525ca02815Sjsg int i;
68535ca02815Sjsg
68545ca02815Sjsg /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
68555ca02815Sjsg * number of gfx waves. Setting 5 bit will make sure gfx only gets
68565ca02815Sjsg * around 25% of gpu resources.
68575ca02815Sjsg */
68585ca02815Sjsg val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
68595ca02815Sjsg amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
68605ca02815Sjsg
68615ca02815Sjsg /* Restrict waves for normal/low priority compute queues as well
68625ca02815Sjsg * to get best QoS for high priority compute jobs.
68635ca02815Sjsg *
68645ca02815Sjsg * amdgpu controls only 1st ME(0-3 CS pipes).
68655ca02815Sjsg */
68665ca02815Sjsg for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
68675ca02815Sjsg if (i != ring->pipe)
68685ca02815Sjsg gfx_v8_0_emit_wave_limit_cs(ring, i, enable);
68695ca02815Sjsg
68705ca02815Sjsg }
68715ca02815Sjsg
68725ca02815Sjsg }
68735ca02815Sjsg
6874fb4d8502Sjsg static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6875fb4d8502Sjsg .name = "gfx_v8_0",
6876fb4d8502Sjsg .early_init = gfx_v8_0_early_init,
6877fb4d8502Sjsg .late_init = gfx_v8_0_late_init,
6878fb4d8502Sjsg .sw_init = gfx_v8_0_sw_init,
6879fb4d8502Sjsg .sw_fini = gfx_v8_0_sw_fini,
6880fb4d8502Sjsg .hw_init = gfx_v8_0_hw_init,
6881fb4d8502Sjsg .hw_fini = gfx_v8_0_hw_fini,
6882fb4d8502Sjsg .suspend = gfx_v8_0_suspend,
6883fb4d8502Sjsg .resume = gfx_v8_0_resume,
6884fb4d8502Sjsg .is_idle = gfx_v8_0_is_idle,
6885fb4d8502Sjsg .wait_for_idle = gfx_v8_0_wait_for_idle,
6886fb4d8502Sjsg .check_soft_reset = gfx_v8_0_check_soft_reset,
6887fb4d8502Sjsg .pre_soft_reset = gfx_v8_0_pre_soft_reset,
6888fb4d8502Sjsg .soft_reset = gfx_v8_0_soft_reset,
6889fb4d8502Sjsg .post_soft_reset = gfx_v8_0_post_soft_reset,
6890fb4d8502Sjsg .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6891fb4d8502Sjsg .set_powergating_state = gfx_v8_0_set_powergating_state,
6892fb4d8502Sjsg .get_clockgating_state = gfx_v8_0_get_clockgating_state,
6893fb4d8502Sjsg };
6894fb4d8502Sjsg
6895fb4d8502Sjsg static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6896fb4d8502Sjsg .type = AMDGPU_RING_TYPE_GFX,
6897fb4d8502Sjsg .align_mask = 0xff,
6898fb4d8502Sjsg .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6899fb4d8502Sjsg .support_64bit_ptrs = false,
6900fb4d8502Sjsg .get_rptr = gfx_v8_0_ring_get_rptr,
6901fb4d8502Sjsg .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6902fb4d8502Sjsg .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6903fb4d8502Sjsg .emit_frame_size = /* maximum 215dw if count 16 IBs in */
6904fb4d8502Sjsg 5 + /* COND_EXEC */
6905fb4d8502Sjsg 7 + /* PIPELINE_SYNC */
6906fb4d8502Sjsg VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
690792675d14Sjsg 12 + /* FENCE for VM_FLUSH */
6908fb4d8502Sjsg 20 + /* GDS switch */
6909fb4d8502Sjsg 4 + /* double SWITCH_BUFFER,
6910fb4d8502Sjsg the first COND_EXEC jump to the place just
6911fb4d8502Sjsg prior to this double SWITCH_BUFFER */
6912fb4d8502Sjsg 5 + /* COND_EXEC */
6913fb4d8502Sjsg 7 + /* HDP_flush */
6914fb4d8502Sjsg 4 + /* VGT_flush */
6915fb4d8502Sjsg 14 + /* CE_META */
6916fb4d8502Sjsg 31 + /* DE_META */
6917fb4d8502Sjsg 3 + /* CNTX_CTRL */
6918fb4d8502Sjsg 5 + /* HDP_INVL */
691992675d14Sjsg 12 + 12 + /* FENCE x2 */
6920ad8b1aafSjsg 2 + /* SWITCH_BUFFER */
6921ad8b1aafSjsg 5, /* SURFACE_SYNC */
6922fb4d8502Sjsg .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6923fb4d8502Sjsg .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6924fb4d8502Sjsg .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
6925fb4d8502Sjsg .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6926fb4d8502Sjsg .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6927fb4d8502Sjsg .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6928fb4d8502Sjsg .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6929fb4d8502Sjsg .test_ring = gfx_v8_0_ring_test_ring,
6930fb4d8502Sjsg .test_ib = gfx_v8_0_ring_test_ib,
6931fb4d8502Sjsg .insert_nop = amdgpu_ring_insert_nop,
6932fb4d8502Sjsg .pad_ib = amdgpu_ring_generic_pad_ib,
6933fb4d8502Sjsg .emit_switch_buffer = gfx_v8_ring_emit_sb,
6934fb4d8502Sjsg .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
6935fb4d8502Sjsg .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
6936fb4d8502Sjsg .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
6937fb4d8502Sjsg .emit_wreg = gfx_v8_0_ring_emit_wreg,
6938c349dbc7Sjsg .soft_recovery = gfx_v8_0_ring_soft_recovery,
6939ad8b1aafSjsg .emit_mem_sync = gfx_v8_0_emit_mem_sync,
6940fb4d8502Sjsg };
6941fb4d8502Sjsg
6942fb4d8502Sjsg static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6943fb4d8502Sjsg .type = AMDGPU_RING_TYPE_COMPUTE,
6944fb4d8502Sjsg .align_mask = 0xff,
6945fb4d8502Sjsg .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6946fb4d8502Sjsg .support_64bit_ptrs = false,
6947fb4d8502Sjsg .get_rptr = gfx_v8_0_ring_get_rptr,
6948fb4d8502Sjsg .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6949fb4d8502Sjsg .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6950fb4d8502Sjsg .emit_frame_size =
6951fb4d8502Sjsg 20 + /* gfx_v8_0_ring_emit_gds_switch */
6952fb4d8502Sjsg 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6953fb4d8502Sjsg 5 + /* hdp_invalidate */
6954fb4d8502Sjsg 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6955fb4d8502Sjsg VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6956ad8b1aafSjsg 7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
69575ca02815Sjsg 7 + /* gfx_v8_0_emit_mem_sync_compute */
69585ca02815Sjsg 5 + /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
69595ca02815Sjsg 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
6960c349dbc7Sjsg .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6961fb4d8502Sjsg .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6962fb4d8502Sjsg .emit_fence = gfx_v8_0_ring_emit_fence_compute,
6963fb4d8502Sjsg .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6964fb4d8502Sjsg .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6965fb4d8502Sjsg .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6966fb4d8502Sjsg .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6967fb4d8502Sjsg .test_ring = gfx_v8_0_ring_test_ring,
6968fb4d8502Sjsg .test_ib = gfx_v8_0_ring_test_ib,
6969fb4d8502Sjsg .insert_nop = amdgpu_ring_insert_nop,
6970fb4d8502Sjsg .pad_ib = amdgpu_ring_generic_pad_ib,
6971fb4d8502Sjsg .emit_wreg = gfx_v8_0_ring_emit_wreg,
6972ad8b1aafSjsg .emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
69735ca02815Sjsg .emit_wave_limit = gfx_v8_0_emit_wave_limit,
6974fb4d8502Sjsg };
6975fb4d8502Sjsg
6976fb4d8502Sjsg static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
6977fb4d8502Sjsg .type = AMDGPU_RING_TYPE_KIQ,
6978fb4d8502Sjsg .align_mask = 0xff,
6979fb4d8502Sjsg .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6980fb4d8502Sjsg .support_64bit_ptrs = false,
6981fb4d8502Sjsg .get_rptr = gfx_v8_0_ring_get_rptr,
6982fb4d8502Sjsg .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6983fb4d8502Sjsg .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6984fb4d8502Sjsg .emit_frame_size =
6985fb4d8502Sjsg 20 + /* gfx_v8_0_ring_emit_gds_switch */
6986fb4d8502Sjsg 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6987fb4d8502Sjsg 5 + /* hdp_invalidate */
6988fb4d8502Sjsg 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6989fb4d8502Sjsg 17 + /* gfx_v8_0_ring_emit_vm_flush */
6990fb4d8502Sjsg 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6991c349dbc7Sjsg .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6992fb4d8502Sjsg .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
6993fb4d8502Sjsg .test_ring = gfx_v8_0_ring_test_ring,
6994fb4d8502Sjsg .insert_nop = amdgpu_ring_insert_nop,
6995fb4d8502Sjsg .pad_ib = amdgpu_ring_generic_pad_ib,
6996fb4d8502Sjsg .emit_rreg = gfx_v8_0_ring_emit_rreg,
6997fb4d8502Sjsg .emit_wreg = gfx_v8_0_ring_emit_wreg,
6998fb4d8502Sjsg };
6999fb4d8502Sjsg
gfx_v8_0_set_ring_funcs(struct amdgpu_device * adev)7000fb4d8502Sjsg static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
7001fb4d8502Sjsg {
7002fb4d8502Sjsg int i;
7003fb4d8502Sjsg
7004*f005ef32Sjsg adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq;
7005fb4d8502Sjsg
7006fb4d8502Sjsg for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7007fb4d8502Sjsg adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
7008fb4d8502Sjsg
7009fb4d8502Sjsg for (i = 0; i < adev->gfx.num_compute_rings; i++)
7010fb4d8502Sjsg adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
7011fb4d8502Sjsg }
7012fb4d8502Sjsg
7013fb4d8502Sjsg static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
7014fb4d8502Sjsg .set = gfx_v8_0_set_eop_interrupt_state,
7015fb4d8502Sjsg .process = gfx_v8_0_eop_irq,
7016fb4d8502Sjsg };
7017fb4d8502Sjsg
7018fb4d8502Sjsg static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
7019fb4d8502Sjsg .set = gfx_v8_0_set_priv_reg_fault_state,
7020fb4d8502Sjsg .process = gfx_v8_0_priv_reg_irq,
7021fb4d8502Sjsg };
7022fb4d8502Sjsg
7023fb4d8502Sjsg static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
7024fb4d8502Sjsg .set = gfx_v8_0_set_priv_inst_fault_state,
7025fb4d8502Sjsg .process = gfx_v8_0_priv_inst_irq,
7026fb4d8502Sjsg };
7027fb4d8502Sjsg
7028fb4d8502Sjsg static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = {
7029fb4d8502Sjsg .set = gfx_v8_0_set_cp_ecc_int_state,
7030fb4d8502Sjsg .process = gfx_v8_0_cp_ecc_error_irq,
7031fb4d8502Sjsg };
7032fb4d8502Sjsg
7033fb4d8502Sjsg static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = {
7034fb4d8502Sjsg .set = gfx_v8_0_set_sq_int_state,
7035fb4d8502Sjsg .process = gfx_v8_0_sq_irq,
7036fb4d8502Sjsg };
7037fb4d8502Sjsg
gfx_v8_0_set_irq_funcs(struct amdgpu_device * adev)7038fb4d8502Sjsg static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
7039fb4d8502Sjsg {
7040fb4d8502Sjsg adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7041fb4d8502Sjsg adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
7042fb4d8502Sjsg
7043fb4d8502Sjsg adev->gfx.priv_reg_irq.num_types = 1;
7044fb4d8502Sjsg adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
7045fb4d8502Sjsg
7046fb4d8502Sjsg adev->gfx.priv_inst_irq.num_types = 1;
7047fb4d8502Sjsg adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
7048fb4d8502Sjsg
7049fb4d8502Sjsg adev->gfx.cp_ecc_error_irq.num_types = 1;
7050fb4d8502Sjsg adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;
7051fb4d8502Sjsg
7052fb4d8502Sjsg adev->gfx.sq_irq.num_types = 1;
7053fb4d8502Sjsg adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs;
7054fb4d8502Sjsg }
7055fb4d8502Sjsg
gfx_v8_0_set_rlc_funcs(struct amdgpu_device * adev)7056fb4d8502Sjsg static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
7057fb4d8502Sjsg {
7058fb4d8502Sjsg adev->gfx.rlc.funcs = &iceland_rlc_funcs;
7059fb4d8502Sjsg }
7060fb4d8502Sjsg
gfx_v8_0_set_gds_init(struct amdgpu_device * adev)7061fb4d8502Sjsg static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
7062fb4d8502Sjsg {
7063fb4d8502Sjsg /* init asci gds info */
7064c349dbc7Sjsg adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
7065c349dbc7Sjsg adev->gds.gws_size = 64;
7066c349dbc7Sjsg adev->gds.oa_size = 16;
7067c349dbc7Sjsg adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
7068fb4d8502Sjsg }
7069fb4d8502Sjsg
gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device * adev,u32 bitmap)7070fb4d8502Sjsg static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7071fb4d8502Sjsg u32 bitmap)
7072fb4d8502Sjsg {
7073fb4d8502Sjsg u32 data;
7074fb4d8502Sjsg
7075fb4d8502Sjsg if (!bitmap)
7076fb4d8502Sjsg return;
7077fb4d8502Sjsg
7078fb4d8502Sjsg data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7079fb4d8502Sjsg data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7080fb4d8502Sjsg
7081fb4d8502Sjsg WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
7082fb4d8502Sjsg }
7083fb4d8502Sjsg
gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device * adev)7084fb4d8502Sjsg static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7085fb4d8502Sjsg {
7086fb4d8502Sjsg u32 data, mask;
7087fb4d8502Sjsg
7088fb4d8502Sjsg data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
7089fb4d8502Sjsg RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
7090fb4d8502Sjsg
7091fb4d8502Sjsg mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7092fb4d8502Sjsg
7093fb4d8502Sjsg return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
7094fb4d8502Sjsg }
7095fb4d8502Sjsg
gfx_v8_0_get_cu_info(struct amdgpu_device * adev)7096fb4d8502Sjsg static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
7097fb4d8502Sjsg {
7098fb4d8502Sjsg int i, j, k, counter, active_cu_number = 0;
7099fb4d8502Sjsg u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7100fb4d8502Sjsg struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
7101fb4d8502Sjsg unsigned disable_masks[4 * 2];
7102fb4d8502Sjsg u32 ao_cu_num;
7103fb4d8502Sjsg
7104fb4d8502Sjsg memset(cu_info, 0, sizeof(*cu_info));
7105fb4d8502Sjsg
7106fb4d8502Sjsg if (adev->flags & AMD_IS_APU)
7107fb4d8502Sjsg ao_cu_num = 2;
7108fb4d8502Sjsg else
7109fb4d8502Sjsg ao_cu_num = adev->gfx.config.max_cu_per_sh;
7110fb4d8502Sjsg
7111fb4d8502Sjsg amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
7112fb4d8502Sjsg
7113fb4d8502Sjsg mutex_lock(&adev->grbm_idx_mutex);
7114fb4d8502Sjsg for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7115fb4d8502Sjsg for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7116fb4d8502Sjsg mask = 1;
7117fb4d8502Sjsg ao_bitmap = 0;
7118fb4d8502Sjsg counter = 0;
7119*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);
7120fb4d8502Sjsg if (i < 4 && j < 2)
7121fb4d8502Sjsg gfx_v8_0_set_user_cu_inactive_bitmap(
7122fb4d8502Sjsg adev, disable_masks[i * 2 + j]);
7123fb4d8502Sjsg bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7124*f005ef32Sjsg cu_info->bitmap[0][i][j] = bitmap;
7125fb4d8502Sjsg
7126fb4d8502Sjsg for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7127fb4d8502Sjsg if (bitmap & mask) {
7128fb4d8502Sjsg if (counter < ao_cu_num)
7129fb4d8502Sjsg ao_bitmap |= mask;
7130fb4d8502Sjsg counter ++;
7131fb4d8502Sjsg }
7132fb4d8502Sjsg mask <<= 1;
7133fb4d8502Sjsg }
7134fb4d8502Sjsg active_cu_number += counter;
7135fb4d8502Sjsg if (i < 2 && j < 2)
7136fb4d8502Sjsg ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7137fb4d8502Sjsg cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
7138fb4d8502Sjsg }
7139fb4d8502Sjsg }
7140*f005ef32Sjsg gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
7141fb4d8502Sjsg mutex_unlock(&adev->grbm_idx_mutex);
7142fb4d8502Sjsg
7143fb4d8502Sjsg cu_info->number = active_cu_number;
7144fb4d8502Sjsg cu_info->ao_cu_mask = ao_cu_mask;
7145fb4d8502Sjsg cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7146fb4d8502Sjsg cu_info->max_waves_per_simd = 10;
7147fb4d8502Sjsg cu_info->max_scratch_slots_per_cu = 32;
7148fb4d8502Sjsg cu_info->wave_front_size = 64;
7149fb4d8502Sjsg cu_info->lds_size = 64;
7150fb4d8502Sjsg }
7151fb4d8502Sjsg
7152fb4d8502Sjsg const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
7153fb4d8502Sjsg {
7154fb4d8502Sjsg .type = AMD_IP_BLOCK_TYPE_GFX,
7155fb4d8502Sjsg .major = 8,
7156fb4d8502Sjsg .minor = 0,
7157fb4d8502Sjsg .rev = 0,
7158fb4d8502Sjsg .funcs = &gfx_v8_0_ip_funcs,
7159fb4d8502Sjsg };
7160fb4d8502Sjsg
7161fb4d8502Sjsg const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
7162fb4d8502Sjsg {
7163fb4d8502Sjsg .type = AMD_IP_BLOCK_TYPE_GFX,
7164fb4d8502Sjsg .major = 8,
7165fb4d8502Sjsg .minor = 1,
7166fb4d8502Sjsg .rev = 0,
7167fb4d8502Sjsg .funcs = &gfx_v8_0_ip_funcs,
7168fb4d8502Sjsg };
7169fb4d8502Sjsg
gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring * ring)7170fb4d8502Sjsg static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
7171fb4d8502Sjsg {
7172fb4d8502Sjsg uint64_t ce_payload_addr;
7173fb4d8502Sjsg int cnt_ce;
7174fb4d8502Sjsg union {
7175fb4d8502Sjsg struct vi_ce_ib_state regular;
7176fb4d8502Sjsg struct vi_ce_ib_state_chained_ib chained;
7177fb4d8502Sjsg } ce_payload = {};
7178fb4d8502Sjsg
7179fb4d8502Sjsg if (ring->adev->virt.chained_ib_support) {
7180fb4d8502Sjsg ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7181fb4d8502Sjsg offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
7182fb4d8502Sjsg cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
7183fb4d8502Sjsg } else {
7184fb4d8502Sjsg ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7185fb4d8502Sjsg offsetof(struct vi_gfx_meta_data, ce_payload);
7186fb4d8502Sjsg cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
7187fb4d8502Sjsg }
7188fb4d8502Sjsg
7189fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));
7190fb4d8502Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7191fb4d8502Sjsg WRITE_DATA_DST_SEL(8) |
7192fb4d8502Sjsg WR_CONFIRM) |
7193fb4d8502Sjsg WRITE_DATA_CACHE_POLICY(0));
7194fb4d8502Sjsg amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
7195fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));
7196fb4d8502Sjsg amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
7197fb4d8502Sjsg }
7198fb4d8502Sjsg
gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring * ring)7199fb4d8502Sjsg static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
7200fb4d8502Sjsg {
7201fb4d8502Sjsg uint64_t de_payload_addr, gds_addr, csa_addr;
7202fb4d8502Sjsg int cnt_de;
7203fb4d8502Sjsg union {
7204fb4d8502Sjsg struct vi_de_ib_state regular;
7205fb4d8502Sjsg struct vi_de_ib_state_chained_ib chained;
7206fb4d8502Sjsg } de_payload = {};
7207fb4d8502Sjsg
7208fb4d8502Sjsg csa_addr = amdgpu_csa_vaddr(ring->adev);
7209fb4d8502Sjsg gds_addr = csa_addr + 4096;
7210fb4d8502Sjsg if (ring->adev->virt.chained_ib_support) {
7211fb4d8502Sjsg de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
7212fb4d8502Sjsg de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
7213fb4d8502Sjsg de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload);
7214fb4d8502Sjsg cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2;
7215fb4d8502Sjsg } else {
7216fb4d8502Sjsg de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
7217fb4d8502Sjsg de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);
7218fb4d8502Sjsg de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload);
7219fb4d8502Sjsg cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2;
7220fb4d8502Sjsg }
7221fb4d8502Sjsg
7222fb4d8502Sjsg amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));
7223fb4d8502Sjsg amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7224fb4d8502Sjsg WRITE_DATA_DST_SEL(8) |
7225fb4d8502Sjsg WR_CONFIRM) |
7226fb4d8502Sjsg WRITE_DATA_CACHE_POLICY(0));
7227fb4d8502Sjsg amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
7228fb4d8502Sjsg amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));
7229fb4d8502Sjsg amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2);
7230fb4d8502Sjsg }
7231