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Searched refs:phy (Results 1 – 25 of 168) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/i915/display/
H A Dintel_combo_phy_regs.h17 #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ argument
24 #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ argument
27 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) argument
31 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) argument
48 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) argument
53 #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ argument
56 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) argument
59 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) argument
61 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) argument
73 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) argument
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H A Dintel_combo_phy.c55 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
78 enum phy phy) in icl_set_procmon_ref_values() argument
82 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
88 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
92 enum phy phy, i915_reg_t reg, u32 mask, in check_phy_reg() argument
101 phy_name(phy), in check_phy_reg()
110 enum phy phy) in icl_verify_procmon_ref_values() argument
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H A Dintel_snps_phy_regs.h13 #define _SNPS_PHY(phy) _PHY(phy, \ argument
16 #define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \ argument
18 #define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg)) argument
19 #define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \ argument
22 #define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000) argument
28 #define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004) argument
41 #define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008) argument
46 #define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C) argument
50 #define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014) argument
55 #define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018) argument
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H A Dintel_dpio_phy.c232 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) in bxt_get_phy_info() argument
238 return &phy_list[phy]; in bxt_get_phy_info()
242 enum dpio_phy *phy, enum dpio_channel *ch) in bxt_port_to_phy_channel() argument
253 *phy = i; in bxt_port_to_phy_channel()
260 *phy = i; in bxt_port_to_phy_channel()
268 *phy = DPIO_PHY0; in bxt_port_to_phy_channel()
279 enum dpio_phy phy; in bxt_ddi_phy_set_signal_levels() local
287 bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); in bxt_ddi_phy_set_signal_levels()
293 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_levels()
295 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_levels()
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H A Dintel_ddi.c204 enum phy phy = intel_port_to_phy(dev_priv, port); in intel_wait_ddi_buf_active() local
219 if (intel_phy_is_tc(dev_priv, phy)) in intel_wait_ddi_buf_active()
330 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_init_dp_buf_reg() local
344 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { in intel_ddi_init_dp_buf_reg()
894 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); in intel_ddi_main_link_aux_domain() local
913 intel_phy_is_tc(i915, phy))) in intel_ddi_main_link_aux_domain()
983 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_enable_transcoder_clock() local
990 val = TGL_TRANS_CLK_SEL_PORT(phy); in intel_ddi_enable_transcoder_clock()
1112 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in icl_ddi_combo_vswing_program() local
1125 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, in icl_ddi_combo_vswing_program()
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H A Dicl_dsi.c235 enum phy phy; in dsi_program_swing_and_deemphasis() local
239 for_each_dsi_phy(phy, intel_dsi->phys) { in dsi_program_swing_and_deemphasis()
247 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); in dsi_program_swing_and_deemphasis()
250 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
251 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
257 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); in dsi_program_swing_and_deemphasis()
260 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
261 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
267 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
271 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), in dsi_program_swing_and_deemphasis()
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H A Dintel_display_power_well.c243 static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915, in icl_aux_pw_to_phy()
418 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); in icl_combo_phy_aux_power_well_enable() local
425 if (phy != PHY_NONE) in icl_combo_phy_aux_power_well_enable()
426 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), in icl_combo_phy_aux_power_well_enable()
433 !intel_port_is_edp(dev_priv, (enum port)phy)) in icl_combo_phy_aux_power_well_enable()
444 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); in icl_combo_phy_aux_power_well_disable() local
449 if (phy != PHY_NONE) in icl_combo_phy_aux_power_well_disable()
450 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), in icl_combo_phy_aux_power_well_disable()
552 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); in icl_aux_power_well_enable() local
554 if (intel_phy_is_tc(dev_priv, phy)) in icl_aux_power_well_enable()
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H A Dintel_hti.c22 bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy) in intel_hti_uses_phy() argument
24 if (drm_WARN_ON(&i915->drm, phy == PHY_NONE)) in intel_hti_uses_phy()
28 i915->display.hti.state & HDPORT_DDI_USED(phy); in intel_hti_uses_phy()
H A Dintel_dpio_phy.h30 enum dpio_phy *phy, enum dpio_channel *ch);
33 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
34 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
36 enum dpio_phy phy);
38 enum dpio_phy phy);
H A Dintel_cx0_phy.c32 bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy) in intel_is_c10phy() argument
34 if (IS_METEORLAKE(i915) && (phy < PHY_C)) in intel_is_c10phy()
91 enum phy phy = intel_port_to_phy(i915, port); in intel_cx0_bus_reset() local
99 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); in intel_cx0_bus_reset()
109 enum phy phy = intel_port_to_phy(i915, port); in intel_cx0_wait_for_ack() local
118 phy_name(phy), *val); in intel_cx0_wait_for_ack()
124 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), in intel_cx0_wait_for_ack()
131 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), in intel_cx0_wait_for_ack()
143 enum phy phy = intel_port_to_phy(i915, port); in __intel_cx0_read_once() local
151 … Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy)); in __intel_cx0_read_once()
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/openbsd-src/sys/dev/pci/
H A Digc_phy.c19 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_ops_generic() local
23 phy->ops.init_params = igc_null_ops_generic; in igc_init_phy_ops_generic()
24 phy->ops.acquire = igc_null_ops_generic; in igc_init_phy_ops_generic()
25 phy->ops.check_reset_block = igc_null_ops_generic; in igc_init_phy_ops_generic()
26 phy->ops.force_speed_duplex = igc_null_ops_generic; in igc_init_phy_ops_generic()
27 phy->ops.get_info = igc_null_ops_generic; in igc_init_phy_ops_generic()
28 phy->ops.set_page = igc_null_set_page; in igc_init_phy_ops_generic()
29 phy->ops.read_reg = igc_null_read_reg; in igc_init_phy_ops_generic()
30 phy->ops.read_reg_locked = igc_null_read_reg; in igc_init_phy_ops_generic()
31 phy->ops.read_reg_page = igc_null_read_reg; in igc_init_phy_ops_generic()
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H A Dixgbe_phy.c117 uint32_t swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_combined_generic_int()
226 uint32_t swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_write_i2c_combined_generic_int()
317 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_generic() local
322 phy->ops.identify = ixgbe_identify_phy_generic; in ixgbe_init_phy_ops_generic()
323 phy->ops.reset = ixgbe_reset_phy_generic; in ixgbe_init_phy_ops_generic()
324 phy->ops.read_reg = ixgbe_read_phy_reg_generic; in ixgbe_init_phy_ops_generic()
325 phy->ops.write_reg = ixgbe_write_phy_reg_generic; in ixgbe_init_phy_ops_generic()
326 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
327 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
328 phy->ops.setup_link = ixgbe_setup_phy_link_generic; in ixgbe_init_phy_ops_generic()
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H A Dixgbe_x550.c215 if (hw->phy.ops.read_i2c_byte_unlocked) in ixgbe_read_pe()
216 status = hw->phy.ops.read_i2c_byte_unlocked(hw, reg, IXGBE_PE, in ixgbe_read_pe()
236 if (hw->phy.ops.write_i2c_byte_unlocked) in ixgbe_write_pe()
237 status = hw->phy.ops.write_i2c_byte_unlocked(hw, reg, IXGBE_PE, in ixgbe_write_pe()
328 uint32_t swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_check_cs4227()
440 hw->phy.type = ixgbe_phy_x550em_kx4; in ixgbe_identify_phy_x550em()
443 hw->phy.type = ixgbe_phy_x550em_xfi; in ixgbe_identify_phy_x550em()
448 hw->phy.type = ixgbe_phy_x550em_kr; in ixgbe_identify_phy_x550em()
454 hw->phy.type = ixgbe_phy_ext_1g_t; in ixgbe_identify_phy_x550em()
458 hw->phy in ixgbe_identify_phy_x550em()
620 struct ixgbe_phy_info *phy = &hw->phy; ixgbe_init_ops_X550EM() local
2094 struct ixgbe_phy_info *phy = &hw->phy; ixgbe_init_phy_ops_X550em() local
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H A Dixgbe_82599.c121 if (hw->phy.multispeed_fiber) { in ixgbe_init_mac_link_ops_82599()
132 (hw->phy.smart_speed == ixgbe_smart_speed_auto || in ixgbe_init_mac_link_ops_82599()
133 hw->phy.smart_speed == ixgbe_smart_speed_on) && in ixgbe_init_mac_link_ops_82599()
154 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82599() local
162 hw->phy.qsfp_shared_i2c_bus = TRUE; in ixgbe_init_phy_ops_82599()
174 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
175 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
178 ret_val = phy->ops.identify(hw); in ixgbe_init_phy_ops_82599()
184 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) in ixgbe_init_phy_ops_82599()
185 hw->phy.ops.reset = NULL; in ixgbe_init_phy_ops_82599()
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H A Dixgbe_82598.c138 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_ops_82598() local
147 phy->ops.init = ixgbe_init_phy_ops_82598; in ixgbe_init_ops_82598()
179 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598; in ixgbe_init_ops_82598()
202 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82598() local
209 phy->ops.identify(hw); in ixgbe_init_phy_ops_82598()
218 switch (hw->phy.type) { in ixgbe_init_phy_ops_82598()
220 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; in ixgbe_init_phy_ops_82598()
221 phy->ops.check_link = ixgbe_check_phy_link_tnx; in ixgbe_init_phy_ops_82598()
222 phy->ops.get_firmware_version = in ixgbe_init_phy_ops_82598()
226 phy->ops.reset = ixgbe_reset_phy_nl; in ixgbe_init_phy_ops_82598()
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H A Dif_em_soc.c49 gcu_miibus_readreg(struct em_hw *hw, int phy, int reg) in gcu_miibus_readreg() argument
63 data |= (phy << MDIO_COMMAND_PHY_ADDR_OFFSET); in gcu_miibus_readreg()
80 DEVNAME(sc), phy, reg); in gcu_miibus_readreg()
90 DEVNAME(sc), phy, reg); in gcu_miibus_readreg()
97 gcu_miibus_writereg(struct em_hw *hw, int phy, int reg, int val) in gcu_miibus_writereg() argument
111 data |= (phy << MDIO_COMMAND_PHY_ADDR_OFFSET); in gcu_miibus_writereg()
128 DEVNAME(sc), phy, reg); in gcu_miibus_writereg()
H A Digc_api.c75 if (hw->phy.ops.init_params) { in igc_init_phy_params()
76 ret_val = hw->phy.ops.init_params(hw); in igc_init_phy_params()
320 if (hw->phy.ops.check_reset_block) in igc_check_reset_block()
321 return hw->phy.ops.check_reset_block(hw); in igc_check_reset_block()
337 if (hw->phy.ops.get_info) in igc_get_phy_info()
338 return hw->phy.ops.get_info(hw); in igc_get_phy_info()
353 if (hw->phy.ops.reset) in igc_phy_hw_reset()
354 return hw->phy.ops.reset(hw); in igc_phy_hw_reset()
H A Digc_i225.c92 hw->phy.media_type = igc_media_type_copper; in igc_init_mac_params_i225()
135 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_params_i225() local
140 if (hw->phy.media_type != igc_media_type_copper) { in igc_init_phy_params_i225()
141 phy->type = igc_phy_none; in igc_init_phy_params_i225()
145 phy->ops.power_up = igc_power_up_phy_copper; in igc_init_phy_params_i225()
146 phy->ops.power_down = igc_power_down_phy_copper_base; in igc_init_phy_params_i225()
147 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; in igc_init_phy_params_i225()
148 phy->reset_delay_us = 100; in igc_init_phy_params_i225()
149 phy in igc_init_phy_params_i225()
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/openbsd-src/sys/dev/mii/
H A Dukphy_subr.c55 ukphy_status(struct mii_softc *phy) in ukphy_status() argument
57 struct mii_data *mii = phy->mii_pdata; in ukphy_status()
64 bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR); in ukphy_status()
68 bmcr = PHY_READ(phy, MII_BMCR); in ukphy_status()
90 anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR); in ukphy_status()
91 if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 && in ukphy_status()
92 (phy->mii_extcapabilities & in ukphy_status()
94 gtcr = PHY_READ(phy, MII_100T2CR); in ukphy_status()
95 gtsr = PHY_READ(phy, MII_100T2SR); in ukphy_status()
118 mii->mii_media_active |= mii_phy_flowstatus(phy); in ukphy_status()
/openbsd-src/sys/dev/fdt/
H A Dmvsw.c116 uint32_t phy; in mvsw_attach() local
152 phy = OF_getpropint(port, "phy-handle", 0); in mvsw_attach()
153 node = OF_getnodebyphandle(phy); in mvsw_attach()
193 mvsw_smi_read(struct mvsw_softc *sc, int phy, int reg) in mvsw_smi_read() argument
199 MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) | in mvsw_smi_read()
209 mvsw_smi_write(struct mvsw_softc *sc, int phy, int reg, int val) in mvsw_smi_write() argument
216 MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) | in mvsw_smi_write()
239 mvsw_phy_read(struct mvsw_softc *sc, int phy, int reg) in mvsw_phy_read() argument
245 MVSW_SMI_CMD_DEVAD(phy) | MVSW_SMI_CMD_REGAD(reg) | in mvsw_phy_read()
255 mvsw_phy_write(struct mvsw_softc *sc, int phy, int reg, int val) in mvsw_phy_write() argument
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H A Dif_fec.c480 int phy = child->mii_phy; in fec_phy_init() local
486 fec_miibus_writereg(dev, phy, 0x0d, 0x0003); in fec_phy_init()
487 fec_miibus_writereg(dev, phy, 0x0e, 0x805d); in fec_phy_init()
488 fec_miibus_writereg(dev, phy, 0x0d, 0x4003); in fec_phy_init()
489 reg = fec_miibus_readreg(dev, phy, 0x0e); in fec_phy_init()
490 fec_miibus_writereg(dev, phy, 0x0e, reg & ~0x0100); in fec_phy_init()
493 fec_miibus_writereg(dev, phy, 0x0d, 0x0007); in fec_phy_init()
494 fec_miibus_writereg(dev, phy, 0x0e, 0x8016); in fec_phy_init()
495 fec_miibus_writereg(dev, phy, 0x0d, 0x4007); in fec_phy_init()
497 reg = fec_miibus_readreg(dev, phy, 0x0e) & 0xffe3; in fec_phy_init()
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H A Drkpciephy.c164 struct regmap *phy, *pipe; in rk3588_pciephy_enable() local
171 phy = regmap_byphandle(grf); in rk3588_pciephy_enable()
172 if (phy == NULL) in rk3588_pciephy_enable()
179 regmap_write_4(phy, RK3588_PCIE3PHY_GRF_CMN_CON(0), in rk3588_pciephy_enable()
203 regmap_write_4(phy, RK3588_PCIE3PHY_GRF_CMN_CON(0), reg); in rk3588_pciephy_enable()
221 stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY0_STATUS1); in rk3588_pciephy_enable()
227 stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY1_STATUS1); in rk3588_pciephy_enable()
/openbsd-src/sys/dev/pci/drm/include/linux/phy/
H A Dphy.h23 struct phy;
25 struct phy *devm_phy_optional_get(struct device *, const char *);
28 phy_configure(struct phy *phy, union phy_configure_opts *opts) in phy_configure() argument
34 phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) in phy_set_mode_ext() argument
/openbsd-src/sys/dev/ic/
H A Dbwi.c706 struct bwi_phy *phy; in bwi_attach() local
777 phy = &mac->mac_phy; in bwi_attach()
802 if (phy->phy_mode == IEEE80211_MODE_11B || in bwi_attach()
803 phy->phy_mode == IEEE80211_MODE_11G) { in bwi_attach()
809 if (phy->phy_mode == IEEE80211_MODE_11B) { in bwi_attach()
838 } else if (phy->phy_mode == IEEE80211_MODE_11A) { in bwi_attach()
843 panic("unknown phymode %d", phy->phy_mode); in bwi_attach()
1391 struct bwi_phy *phy = &mac->mac_phy; in bwi_mac_setup_tpctl() local
1417 if (phy->phy_mode == IEEE80211_MODE_11A) { in bwi_mac_setup_tpctl()
1443 if (phy->phy_mode == IEEE80211_MODE_11G) { in bwi_mac_setup_tpctl()
[all …]
/openbsd-src/sys/dev/sbus/
H A Dbe.c1158 be_pal_gate(struct be_softc *sc, int phy) in be_pal_gate() argument
1167 if (phy == BE_PHY_INTERNAL) in be_pal_gate()
1175 be_tcvr_read_bit(struct be_softc *sc, int phy) in be_tcvr_read_bit() argument
1181 if (phy == BE_PHY_INTERNAL) { in be_tcvr_read_bit()
1203 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) in be_tcvr_write_bit() argument
1209 if (phy == BE_PHY_INTERNAL) { in be_tcvr_write_bit()
1223 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) in be_mii_sendbits() argument
1228 be_tcvr_write_bit(sc, phy, (data & i) != 0); in be_mii_sendbits()
1232 be_mii_readreg(struct device *self, int phy, int reg) in be_mii_readreg() argument
1241 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); in be_mii_readreg()
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