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Searched refs:ctrl_reg (Results 1 – 7 of 7) sorted by relevance

/openbsd-src/sys/dev/pci/
H A Dixgb_hw.c79 uint32_t ctrl_reg; in ixgb_mac_reset() local
81 ctrl_reg = IXGB_CTRL0_RST | in ixgb_mac_reset()
92 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
94 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
99 ctrl_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_mac_reset()
102 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); in ixgb_mac_reset()
106 ctrl_reg = /* Enable interrupt from XFP and SerDes */ in ixgb_mac_reset()
112 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); in ixgb_mac_reset()
119 return ctrl_reg; in ixgb_mac_reset()
130 uint32_t ctrl_reg; in ixgb_adapter_stop() local
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H A Dif_em_hw.c11664 uint32_t ctrl_reg = 0; in em_configure_k1_ich8lan() local
11686 ctrl_reg = E1000_READ_REG(hw, CTRL); in em_configure_k1_ich8lan()
11688 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); in em_configure_k1_ich8lan()
11694 E1000_WRITE_REG(hw, CTRL, ctrl_reg); in em_configure_k1_ich8lan()
/openbsd-src/sys/dev/pci/drm/i915/display/
H A Dvlv_dsi.c140 i915_reg_t data_reg, ctrl_reg; in intel_dsi_host_transfer() local
152 ctrl_reg = MIPI_LP_GEN_CTRL(port); in intel_dsi_host_transfer()
157 ctrl_reg = MIPI_HS_GEN_CTRL(port); in intel_dsi_host_transfer()
183 intel_de_write(dev_priv, ctrl_reg, in intel_dsi_host_transfer()
957 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ? in intel_dsi_get_hw_state() local
959 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; in intel_dsi_get_hw_state()
/openbsd-src/sys/dev/pci/drm/i915/gvt/
H A Dcmd_parser.c1270 i915_reg_t ctrl_reg; member
1316 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1320 info->ctrl_reg = SPRCTL(info->pipe); in gen8_decode_mi_display_flip()
1382 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
1399 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & in gen8_check_mi_display_flip()
1404 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; in gen8_check_mi_display_flip()
1428 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), in gen8_update_plane_mmio_from_mi_display_flip()
1433 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), in gen8_update_plane_mmio_from_mi_display_flip()
/openbsd-src/sys/dev/pci/drm/i915/gt/
H A Dintel_engine_types.h229 * @ctrl_reg: the enhanced execlists control register, used to load the
232 u32 __iomem *ctrl_reg; member
H A Dintel_execlists_submission.c731 if (execlists->ctrl_reg) { in write_desc()
943 if (execlists->ctrl_reg) in execlists_submit_ports()
944 writel(EL_CTRL_LOAD, execlists->ctrl_reg); in execlists_submit_ports()
3572 execlists->ctrl_reg = intel_uncore_regs(uncore) + in intel_execlists_submission_setup()
/openbsd-src/sys/dev/ic/
H A Dadvlib.c1492 u_int8_t ctrl_reg; in AscISR() local
1500 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); in AscISR()
1501 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | in AscISR()
1530 (ctrl_reg & ASC_CC_SINGLE_STEP)) { in AscISR()