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/netbsd-src/external/gpl2/texinfo/dist/doc/
H A Dpdfcolor.tex3 \def\cmykGreenYellow{0.15 0 0.69 0}
4 \def\cmykYellow{0 0 1 0}
5 \def\cmykGoldenrod{0 0.10 0.84 0}
6 \def\cmykDandelion{0 0.29 0.84 0}
7 \def\cmykApricot{0 0.32 0.52 0}
8 \def\cmykPeach{0 0.50 0.70 0}
9 \def\cmykMelon{0 0.46 0.50 0}
10 \def\cmykYellowOrange{0 0.42 1 0}
11 \def\cmykOrange{0 0.61 0.87 0}
12 \def\cmykBurntOrange{0 0.51 1 0}
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
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/netbsd-src/external/apache2/llvm/dist/clang/include/clang/Basic/
H A DStmtNodes.td9 def Stmt : StmtNode<?, 1>;
10 def NullStmt : StmtNode<Stmt>;
11 def CompoundStmt : StmtNode<Stmt>;
12 def IfStmt : StmtNode<Stmt>;
13 def SwitchStmt : StmtNode<Stmt>;
14 def WhileStmt : StmtNode<Stmt>;
15 def DoStmt : StmtNode<Stmt>;
16 def ForStmt : StmtNode<Stmt>;
17 def GotoStmt : StmtNode<Stmt>;
18 def IndirectGotoStmt : StmtNode<Stmt>;
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H A DDiagnosticGroups.td9 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
10 def ImplicitInt : DiagGroup<"implicit-int">;
13 def Implicit : DiagGroup<"implicit", [
19 def ODR : DiagGroup<"odr">;
20 def : DiagGroup<"abi">;
21 def AbsoluteValue : DiagGroup<"absolute-value">;
22 def MisspelledAssumption : DiagGroup<"misspelled-assumption">;
23 def UnknownAssumption : DiagGroup<"unknown-assumption">;
24 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
25 def : DiagGroup<"aggregate-return">;
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H A DDeclNodes.td12 def Decl : DeclNode<?, "", 1>;
13 def TranslationUnit : DeclNode<Decl>, DeclContext;
14 def PragmaComment : DeclNode<Decl>;
15 def PragmaDetectMismatch : DeclNode<Decl>;
16 def ExternCContext : DeclNode<Decl>, DeclContext;
17 def Named : DeclNode<Decl, "named declarations", 1>;
18 def Namespace : DeclNode<Named, "namespaces">, DeclContext;
19 def UsingDirective : DeclNode<Named>;
20 def NamespaceAlias : DeclNode<Named>;
21 def Label : DeclNode<Named, "labels">;
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H A Darm_neon.td16 def OP_ADD : Op<(op "+", $p0, $p1)>;
17 def OP_ADDL : Op<(op "+", (call "vmovl", $p0), (call "vmovl", $p1))>;
18 def OP_ADDLHi : Op<(op "+", (call "vmovl_high", $p0),
20 def OP_ADDW : Op<(op "+", $p0, (call "vmovl", $p1))>;
21 def OP_ADDWHi : Op<(op "+", $p0, (call "vmovl_high", $p1))>;
22 def OP_SUB : Op<(op "-", $p0, $p1)>;
23 def OP_SUBL : Op<(op "-", (call "vmovl", $p0), (call "vmovl", $p1))>;
24 def OP_SUBLHi : Op<(op "-", (call "vmovl_high", $p0),
26 def OP_SUBW : Op<(op "-", $p0, (call "vmovl", $p1))>;
27 def OP_SUBWHi : Op<(op "-", $p0, (call "vmovl_high", $p1))>;
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DIntrinsicsHexagonDep.td1070 def int_hexagon_A2_abs :
1073 def int_hexagon_A2_absp :
1076 def int_hexagon_A2_abssat :
1079 def int_hexagon_A2_add :
1082 def int_hexagon_A2_addh_h16_hh :
1085 def int_hexagon_A2_addh_h16_hl :
1088 def int_hexagon_A2_addh_h16_lh :
1091 def int_hexagon_A2_addh_h16_ll :
1094 def int_hexagon_A2_addh_h16_sat_hh :
1097 def int_hexagon_A2_addh_h16_sat_hl :
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H A DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td42 def SysRegsList : GenericTable {
54 def lookupSysRegByName : SearchIndex {
59 def lookupSysRegByAltName : SearchIndex {
64 def lookupSysRegByDeprecatedName : SearchIndex {
76 def : SysReg<"ustatus", 0x000>;
77 def : SysReg<"uie", 0x004>;
78 def : SysReg<"utvec", 0x005>;
83 def : SysReg<"uscratch", 0x040>;
84 def : SysReg<"uepc", 0x041>;
85 def : SysReg<"ucause", 0x042>;
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H A DRISCVSchedule.td9 /// Define scheduler resources associated with def operands.
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder
17 def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I
18 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
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H A DRISCVSchedRocket.td14 def RocketModel : SchedMachineModel {
29 def RocketUnitALU : ProcResource<1>; // Int ALU
30 def RocketUnitIMul : ProcResource<1>; // Int Multiply
31 def RocketUnitMem : ProcResource<1>; // Load/Store
32 def RocketUnitB : ProcResource<1>; // Branch
34 def RocketUnitFPALU : ProcResource<1>; // FP ALU
38 def RocketUnitIDiv : ProcResource<1>; // Int Division
39 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
47 def : WriteRes<WriteJmp, [RocketUnitB]>;
48 def : WriteRes<WriteJal, [RocketUnitB]>;
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H A DRISCVSchedSiFive7.td12 def SiFive7Model : SchedMachineModel {
27 def SiFive7PipeA : ProcResource<1>;
28 def SiFive7PipeB : ProcResource<1>;
32 def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
33 def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
36 def SiFive7PipeAB : ProcResGroup<[SiFive7PipeA, SiFive7PipeB]>;
39 def : WriteRes<WriteJmp, [SiFive7PipeB]>;
40 def : WriteRes<WriteJal, [SiFive7PipeB]>;
41 def : WriteRes<WriteJalr, [SiFive7PipeB]>;
42 def : WriteRes<WriteJmpReg, [SiFive7PipeB]>;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/netbsd-src/external/apache2/llvm/dist/clang/include/clang/AST/
H A DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUSearchableTables.td19 def RsrcIntrinsics : GenericTable {
30 def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
50 def Gfx9BufferFormat : GcnBufferFormatTable {
54 def Gfx10PlusBufferFormat : GcnBufferFormatTable {
59 def getGfx9BufferFormatInfo : SearchIndex {
63 def getGfx10PlusBufferFormatInfo : SearchIndex {
69 def : Gfx9BufferFormat< /*FORMAT_8_UNORM*/ 0x01, 8, 1, /*NUM_FORMAT_UNORM*/ 0, /*DA…
70 def : Gfx9BufferFormat< /*FORMAT_8_SNORM*/ 0x11, 8, 1, /*NUM_FORMAT_SNORM*/ 1, /*DA…
71 def : Gfx9BufferFormat< /*FORMAT_8_USCALED*/ 0x21, 8, 1, /*NUM_FORMAT_USCALED*/ 2, /*DA…
72 def : Gfx9BufferFormat< /*FORMAT_8_SSCALED*/ 0x31, 8, 1, /*NUM_FORMAT_SSCALED*/ 3, /*DA…
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRDevices.td35 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
39 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
45 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
51 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
56 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
61 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
66 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
71 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
75 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
80 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSchedule.td12 def ALU : FuncUnit;
13 def IMULDIV : FuncUnit;
19 def IIM16Alu : InstrItinClass;
20 def IIPseudo : InstrItinClass;
22 def II_ABS : InstrItinClass;
23 def II_ADDI : InstrItinClass;
24 def II_ADDIU : InstrItinClass;
25 def II_ADDIUPC : InstrItinClass;
26 def II_ADD : InstrItinClass;
27 def II_ADDU : InstrItinClass;
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H A DMipsScheduleGeneric.td16 def MipsGenericModel : SchedMachineModel {
39 def GenericALU : ProcResource<1> { let BufferSize = 1; }
40 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
42 def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>;
47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
53 def : InstRW<[GenericWriteALU], (instrs COPY)>;
59 def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI,
66 def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
82 def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
88 def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td24 def sub_even : SubRegIndex<32>;
25 def sub_odd : SubRegIndex<32, 32>;
26 def sub_even64 : SubRegIndex<64>;
27 def sub_odd64 : SubRegIndex<64, 64>;
58 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
60 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
62 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
64 def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
66 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
68 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
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/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dvisium.h43 #define def (MASK_DEF | MASK_GR5 | MASK_GR6) macro
234 { "adc.b", mode_dab, class3|(1<<21)|(1), def },
235 { "adc.l", mode_dab, class3|(1<<21)|(4), def },
236 { "adc.w", mode_dab, class3|(1<<21)|(2), def },
237 { "add.b", mode_dab, class3|(0<<21)|(1), def },
238 { "add.l", mode_dab, class3|(0<<21)|(4), def },
239 { "add.w", mode_dab, class3|(0<<21)|(2), def },
240 { "addi", mode_ai, class2, def },
241 { "and.b", mode_dab, class3|(10<<21)|(1), def},
242 { "and.l", mode_dab, class3|(10<<21)|(4), def },
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/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dvisium.h43 #define def (MASK_DEF | MASK_GR5 | MASK_GR6) macro
234 { "adc.b", mode_dab, class3|(1<<21)|(1), def },
235 { "adc.l", mode_dab, class3|(1<<21)|(4), def },
236 { "adc.w", mode_dab, class3|(1<<21)|(2), def },
237 { "add.b", mode_dab, class3|(0<<21)|(1), def },
238 { "add.l", mode_dab, class3|(0<<21)|(4), def },
239 { "add.w", mode_dab, class3|(0<<21)|(2), def },
240 { "addi", mode_ai, class2, def },
241 { "and.b", mode_dab, class3|(10<<21)|(1), def},
242 { "and.l", mode_dab, class3|(10<<21)|(4), def },
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedExynosM4.td19 def ExynosM4Model : SchedMachineModel {
36 def M4UnitA : ProcResource<2>; // Simple integer
37 def M4UnitC : ProcResource<2>; // Simple and complex integer
39 def M4UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
41 def M4UnitE : ProcResource<1>; // CRC (inside C0)
42 def M4UnitB : ProcResource<2>; // Branch
43 def M4UnitL0 : ProcResource<1>; // Load
44 def M4UnitS0 : ProcResource<1>; // Store
45 def M4PipeLS : ProcResource<1>; // Load/Store
47 def M4UnitL1 : ProcResource<1>;
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H A DAArch64SchedExynosM3.td19 def ExynosM3Model : SchedMachineModel {
37 def M3UnitA : ProcResource<2>; // Simple integer
38 def M3UnitC : ProcResource<2>; // Simple and complex integer
39 def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
40 def M3UnitB : ProcResource<2>; // Branch
41 def M3UnitL : ProcResource<2>; // Load
42 def M3UnitS : ProcResource<1>; // Store
43 def M3PipeF0 : ProcResource<1>; // FP #0
45 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
46 def M3UnitFADD0 : ProcResource<1>; // Simple FP
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H A DAArch64RegisterInfo.td22 def sub_32 : SubRegIndex<32>;
24 def bsub : SubRegIndex<8>;
25 def hsub : SubRegIndex<16>;
26 def ssub : SubRegIndex<32>;
27 def dsub : SubRegIndex<32>;
28 def sube32 : SubRegIndex<32>;
29 def subo32 : SubRegIndex<32>;
30 def qhisub : SubRegIndex<64>;
31 def qsub : SubRegIndex<64>;
32 def sube64 : SubRegIndex<64>;
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