| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 156 MVT PartVT, EVT ValueVT, const Value *V,
166 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
172 PartVT, ValueVT, CC)) in getCopyFromParts()
175 if (ValueVT.isVector()) in getCopyFromParts()
176 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
184 if (ValueVT.isInteger()) { in getCopyFromParts()
186 unsigned ValueBits = ValueVT.getSizeInBits(); in getCopyFromParts()
193 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
240 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in getCopyFromParts()
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| H A D | LegalizeTypesGeneric.cpp | 256 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
281 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
466 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
467 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
478 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
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| H A D | FunctionLoweringInfo.cpp | 394 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
395 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
397 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
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| H A D | LegalizeVectorTypes.cpp | 4916 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE() local
4918 ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 148 EVT ValueVT = LD->getValueType(0); in SelectIndexedLoad() local
149 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
153 ValueVT = MVT::i32; in SelectIndexedLoad()
157 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in SelectIndexedLoad()
169 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in SelectIndexedLoad()
471 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
518 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5721 MVT ValueVT = Node->getSimpleValueType(0); in Select() local
5727 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
5730 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
5731 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
5764 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() && in Select()
5795 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other); in Select()
5818 MVT ValueVT = Value.getSimpleValueType(); in Select() local
5823 if (!ValueVT.isVector()) in Select()
5826 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
5827 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 468 MVT PartVT, EVT ValueVT,
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| H A D | RISCVISelLowering.cpp | 8528 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
8529 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
8541 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
8543 EVT ValueEltVT = ValueVT.getVectorElementType(); in splitValueIntoRegisterParts()
8545 unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinSize(); in splitValueIntoRegisterParts()
8568 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
8570 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
8580 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in joinRegisterPartsIntoValue()
8583 EVT ValueEltVT = ValueVT.getVectorElementType(); in joinRegisterPartsIntoValue()
8585 unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinSize(); in joinRegisterPartsIntoValue()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 872 MVT PartVT, EVT ValueVT,
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| H A D | ARMISelLowering.cpp | 4216 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
4217 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
4219 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
4232 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4234 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in joinRegisterPartsIntoValue()
4236 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
4242 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3681 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
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