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Searched refs:VT2 (Results 1 – 25 of 26) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DLegacyPassNameParser.h90 const PassNameParser::OptionInfo *VT2) { in ValCompare() argument
91 return VT1->Name.compare(VT2->Name); in ValCompare()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h117 bool isTruncateFree(EVT VT1, EVT VT2) const override;
128 bool isZExtFree(EVT VT1, EVT VT2) const override;
129 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DMSP430ISelLowering.cpp1396 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
1397 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
1400 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
1408 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
1410 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; in isZExtFree()
1413 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
1414 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.h137 bool isTruncateFree(EVT VT1, EVT VT2) const override;
141 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DBPFISelLowering.cpp199 bool BPFTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
200 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
203 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
215 bool BPFTargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
216 if (!getHasAlu32() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
219 unsigned NumBits2 = VT2.getSizeInBits(); in isZExtFree()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h603 SDVTList getVTList(EVT VT1, EVT VT2);
604 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
605 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
1405 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
1407 EVT VT2, ArrayRef<SDValue> Ops);
1409 EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
1411 EVT VT2, SDValue Op1, SDValue Op2);
1441 EVT VT2, SDValue Op1, SDValue Op2);
1443 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1445 EVT VT2, ArrayRef<SDValue> Ops);
[all …]
H A DTargetLowering.h1483 MVT VT2; in getNumRegisters() local
1485 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); in getNumRegisters()
2652 virtual bool isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree() argument
2653 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.h1203 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1216 bool isZExtFree(EVT VT1, EVT VT2) const override;
1217 bool isZExtFree(SDValue Val, EVT VT2) const override;
1236 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
H A DX86ISelLowering.cpp31817 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
31818 if (!VT1.isScalarInteger() || !VT2.isScalarInteger()) in isTruncateFree()
31821 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
31830 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
31832 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget.is64Bit(); in isZExtFree()
31835 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
31837 if (isZExtFree(VT1, VT2)) in isZExtFree()
31844 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
31926 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { in isNarrowingProfitable()
31928 return !(VT1 == MVT::i32 && VT2 == MVT::i16); in isNarrowingProfitable()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h160 bool isZExtFree(SDValue Val, EVT VT2) const override;
167 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
H A DAMDGPUISelLowering.cpp915 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
916 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp2194 SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) { in CreateStackTemporary() argument
2196 TypeSize VT2Size = VT2.getStoreSize(); in CreateStackTemporary()
2204 Type *Ty2 = VT2.getTypeForEVT(*getContext()); in CreateStackTemporary()
8066 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) { in getVTList() argument
8070 ID.AddInteger(VT2.getRawBits()); in getVTList()
8077 Array[1] = VT2; in getVTList()
8084 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) { in getVTList() argument
8088 ID.AddInteger(VT2.getRawBits()); in getVTList()
8096 Array[1] = VT2; in getVTList()
8104 SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4) { in getVTList() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h98 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DXCoreISelLowering.cpp179 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
185 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h572 bool isTruncateFree(EVT VT1, EVT VT2) const override;
577 bool isZExtFree(EVT VT1, EVT VT2) const override;
578 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DAArch64ISelLowering.cpp10980 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
10981 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
10984 uint64_t NumBits2 = VT2.getFixedSizeInBits(); in isTruncateFree()
11025 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
11026 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
11029 unsigned NumBits2 = VT2.getSizeInBits(); in isZExtFree()
11033 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
11035 if (isZExtFree(VT1, VT2)) { in isZExtFree()
11044 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() && in isZExtFree()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h967 bool isTruncateFree(EVT VT1, EVT VT2) const override;
969 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DPPCISelLowering.cpp16094 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
16095 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
16098 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
16102 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
16119 return TargetLowering::isZExtFree(Val, VT2); in isZExtFree()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h288 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DRISCVISelLowering.cpp916 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
927 return TargetLowering::isZExtFree(Val, VT2); in isZExtFree()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h133 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DHexagonISelLowering.cpp2080 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
2081 if (!VT1.isSimple() || !VT2.isSimple()) in isTruncateFree()
2083 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.h441 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DARMInstrMVE.td4455 foreach VT2 = [ v4i1, v8i1, v16i1 ] in
4456 def : Pat<(VT (predicate_cast (VT2 VCCR:$src))),
4457 (VT (COPY_TO_REGCLASS (VT2 VCCR:$src), VCCR))>;
4474 foreach VT2 = [ v16i8, v8i16, v8f16, v4i32, v4f32, v2i64, v2f64 ] in
4475 def : Pat<(VT (ARMVectorRegCastImpl (VT2 MQPR:$src))),
H A DARMInstrNEON.td7674 foreach VT2 = [ v16i8, v8i16, v8f16, v8bf16, v4i32, v4f32, v2i64, v2f64 ] in
7675 def : Pat<(VT (ARMVectorRegCastImpl (VT2 QPR:$src))), (VT QPR:$src)>;
7678 foreach VT2 = [ v8i8, v4i16, v4f16, v4bf16, v2i32, v2f32, v1i64, f64 ] in
7679 def : Pat<(VT (ARMVectorRegCastImpl (VT2 DPR:$src))), (VT DPR:$src)>;

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