Searched refs:VSCALE (Results 1 – 11 of 11) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1188 VSCALE, enumerator
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| H A D | SelectionDAG.h | 955 return getNode(ISD::VSCALE, DL, VT,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 174 case ISD::VSCALE: return "vscale"; in getOperationName()
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| H A D | DAGCombiner.cpp | 2489 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2497 (N0.getOperand(1).getOpcode() == ISD::VSCALE) && in visitADD()
2498 (N1.getOpcode() == ISD::VSCALE)) { in visitADD()
3541 if (N1.getOpcode() == ISD::VSCALE) { in visitSUB()
3921 if (N0.getOpcode() == ISD::VSCALE) in visitMUL()
8420 if (N0.getOpcode() == ISD::VSCALE) in visitSHL()
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| H A D | SelectionDAG.cpp | 4999 case ISD::VSCALE: in getNode()
5556 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
5618 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
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| H A D | LegalizeIntegerTypes.cpp | 95 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break; in PromoteIntegerResult()
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| H A D | SelectionDAGBuilder.cpp | 3939 ISD::VSCALE, dl, VScaleTy, in visitGetElementPtr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 397 setOperationAction(ISD::VSCALE, XLenVT, Custom); in RISCVTargetLowering()
2086 case ISD::VSCALE: { in LowerOperation()
3787 SlideupAmt = DAG.getNode(ISD::VSCALE, DL, XLenVT, SlideupAmt); in lowerINSERT_SUBVECTOR()
3794 VL = DAG.getNode(ISD::VSCALE, DL, XLenVT, VL); in lowerINSERT_SUBVECTOR()
3921 SlidedownAmt = DAG.getNode(ISD::VSCALE, DL, XLenVT, SlidedownAmt); in lowerEXTRACT_SUBVECTOR()
4024 SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT, in lowerVECTOR_REVERSE()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 334 def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 4963 if (VScale.getOpcode() != ISD::VSCALE) in SelectAddrModeIndexedSVE()
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| H A D | AArch64ISelLowering.cpp | 1117 setOperationAction(ISD::VSCALE, MVT::i32, Custom); in AArch64TargetLowering()
4658 case ISD::VSCALE: in LowerOperation()
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