| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveVariables.cpp | 195 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef() local
196 unsigned SubReg = *SubRegs; in FindLastPartialDef()
218 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef() local
219 SubRegs.isValid(); ++SubRegs) in FindLastPartialDef()
220 PartDefRegs.insert(*SubRegs); in FindLastPartialDef()
249 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegUse() local
250 unsigned SubReg = *SubRegs; in HandlePhysRegUse()
272 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in HandlePhysRegUse() local
273 SubRegs.isValid(); ++SubRegs) in HandlePhysRegUse()
274 PhysRegUse[*SubRegs] = &MI; in HandlePhysRegUse()
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| H A D | CriticalAntiDepBreaker.cpp | 227 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
228 SubRegs.isValid(); ++SubRegs) { in PrescanInstruction()
229 KeepRegs.set(*SubRegs); in PrescanInstruction()
239 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
240 SubRegs.isValid(); ++SubRegs) in PrescanInstruction()
241 KeepRegs.set(*SubRegs); in PrescanInstruction()
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| H A D | MachineInstrBundle.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in finalizeBundle() local
198 unsigned SubReg = *SubRegs; in finalizeBundle()
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| H A D | AggressiveAntiDepBreaker.cpp | 250 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs() local
251 SubRegs.isValid(); ++SubRegs) in GetPassthruRegs()
252 PassthruRegs.insert(*SubRegs); in GetPassthruRegs()
326 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandleLastUse() local
327 unsigned SubregReg = *SubRegs; in HandleLastUse()
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| H A D | IfConversion.cpp | 1963 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamondCommon() local
1964 SubRegs.isValid(); ++SubRegs) in IfConvertDiamondCommon()
1965 ExtUses.insert(*SubRegs); in IfConvertDiamondCommon()
1971 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamondCommon() local
1972 SubRegs.isValid(); ++SubRegs) in IfConvertDiamondCommon()
1973 RedefsByFalse.insert(*SubRegs); in IfConvertDiamondCommon()
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| H A D | BranchFolding.cpp | 1888 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findHoistingInsertPosAndDeps() local
1889 Uses.erase(*SubRegs); // Use sub-registers to be conservative in findHoistingInsertPosAndDeps()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | LivePhysRegs.h | 82 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in addReg()
83 SubRegs.isValid(); ++SubRegs) in addReg()
84 LiveRegs.insert(*SubRegs); in addReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 254 for (const auto &SubReg : SubRegs) { in inheritRegUnits()
267 return SubRegs; in computeSubRegs()
278 if (!SubRegs.insert(std::make_pair(Idx, SR)).second) in computeSubRegs()
296 if (!SubRegs.insert(SR).second) in computeSubRegs()
309 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
320 if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second)) in computeSubRegs()
323 SubRegs.insert(std::make_pair(Comp.second, SRI->second)); in computeSubRegs()
346 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
350 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second; in computeSubRegs()
354 for (const auto &SubReg : SubRegs) { in computeSubRegs()
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| H A D | CodeGenRegisters.h | 185 return SubRegs; in getSubRegs()
278 SubRegMap SubRegs; member
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.td | 40 let SubRegs = [SubReg];
47 let SubRegs = [SubReg];
72 let SubRegs = [SubReg];
80 let SubRegs = [SubReg];
93 let SubRegs = subregs;
104 let SubRegs = subregs;
113 let SubRegs = subregs;
119 let SubRegs = subregs;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VERegisterInfo.td | 19 let SubRegs = subregs;
35 let SubRegs = subregs;
45 let SubRegs = subregs;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 107 uint32_t SubRegs; // Sub-register set, described above member
291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} in mc_subreg_iterator()
598 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 449 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findPotentialNewifiableTFRs() local
450 LastDef[*SubRegs] = &MI; in findPotentialNewifiableTFRs()
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| H A D | HexagonRegisterInfo.td | 53 let SubRegs = subregs;
74 let SubRegs = subregs;
90 let SubRegs = subregs;
144 let SubRegs = [USR_OVF];
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| H A D | HexagonFrameLowering.cpp | 251 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) { in getMax32BitSubRegister() local
253 if (*SubRegs > RegNo) in getMax32BitSubRegister()
254 RegNo = *SubRegs; in getMax32BitSubRegister()
256 if (!RegNo || *SubRegs < RegNo) in getMax32BitSubRegister()
257 RegNo = *SubRegs; in getMax32BitSubRegister()
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| H A D | HexagonInstrInfo.cpp | 2137 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
2138 if (RegB == *SubRegs) in isDependent()
2142 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
2143 if (RegA == *SubRegs) in isDependent()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/ |
| H A D | CSKYRegisterInfo.td | 34 let SubRegs = [subreg];
42 let SubRegs = [subreg];
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiRegisterInfo.td | 17 let SubRegs = subregs;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 36 let SubRegs = subregs;
45 let SubRegs = subregs;
52 let SubRegs = subregs;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | Target.td | 95 // in the SubRegs field of a Register definition. For example:
141 // SubRegs - A list of registers that are parts of this register. Note these
143 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
145 list<Register> SubRegs = [];
147 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
149 // SubRegs.
194 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
198 let SubRegs = subregs;
376 // SubRegs - N lists of registers to be zipped up. Super-registers are
377 // synthesized from the first element of each SubRegs list, the second
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.td | 22 let SubRegs = SUBREGS;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 933 unsigned SubRegs = 0; in copyPhysReg() local
940 SubRegs = 2; in copyPhysReg()
944 SubRegs = 4; in copyPhysReg()
949 SubRegs = 2; in copyPhysReg()
953 SubRegs = 3; in copyPhysReg()
957 SubRegs = 4; in copyPhysReg()
961 SubRegs = 2; in copyPhysReg()
965 SubRegs = 2; in copyPhysReg()
970 SubRegs = 3; in copyPhysReg()
975 SubRegs = 4; in copyPhysReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 521 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES() local
527 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
566 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_UNMERGE_VALUES() local
570 .addReg(SrcReg, 0, SubRegs[I]); in selectG_UNMERGE_VALUES()
573 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]); in selectG_UNMERGE_VALUES()
2602 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex() local
2606 if (static_cast<unsigned>(Offset) >= SubRegs.size()) in computeIndirectRegIndex()
2607 return std::make_pair(IdxReg, SubRegs[0]); in computeIndirectRegIndex()
2608 return std::make_pair(IdxBaseReg, SubRegs[Offset]); in computeIndirectRegIndex()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.td | 27 let SubRegs = [subreg];
39 let SubRegs = [subreg];
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 239 const unsigned SubRegs[]);
1193 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
1196 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1202 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
1205 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1212 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZTuple() local
1215 return createTuple(Regs, RegClassIDs, SubRegs); in createZTuple()
1220 const unsigned SubRegs[]) { in createTuple() argument
1239 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32)); in createTuple()
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