Searched refs:SmallVT (Results 1 – 6 of 6) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 585 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); in ShrinkDemandedOp() local
586 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && in ShrinkDemandedOp()
587 TLI.isZExtFree(SmallVT, Op.getValueType())) { in ShrinkDemandedOp()
590 Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
591 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), in ShrinkDemandedOp()
592 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); in ShrinkDemandedOp()
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| H A D | LegalizeIntegerTypes.cpp | 1359 EVT SmallVT = LHS.getValueType(); in PromoteIntRes_XMULO() local
1381 unsigned Shift = SmallVT.getScalarSizeInBits(); in PromoteIntRes_XMULO()
1391 Mul, DAG.getValueType(SmallVT)); in PromoteIntRes_XMULO()
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| H A D | DAGCombiner.cpp | 8818 EVT SmallVT = N0.getOperand(0).getValueType(); in visitSRL() local
8819 unsigned BitSize = SmallVT.getScalarSizeInBits(); in visitSRL()
8823 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
8826 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, in visitSRL()
8829 getShiftAmountTy(SmallVT))); in visitSRL()
20325 EVT SmallVT = V.getOperand(1).getValueType(); in visitEXTRACT_SUBVECTOR() local
20326 if (!NVT.bitsEq(SmallVT)) in visitEXTRACT_SUBVECTOR()
20335 if (InsIdx * SmallVT.getScalarSizeInBits() == in visitEXTRACT_SUBVECTOR()
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| H A D | SelectionDAGBuilder.cpp | 8953 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); in lowerRangeToAssertZExt() local
8958 DAG.getValueType(SmallVT)); in lowerRangeToAssertZExt()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4025 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal); in PerformDAGCombine() local
4034 DAG.getValueType(SmallVT)); in PerformDAGCombine()
4037 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 595 for (auto SmallVT : SmallerVTs) { in RISCVTargetLowering() local
596 setTruncStoreAction(VT, SmallVT, Expand); in RISCVTargetLowering()
597 setLoadExtAction(ISD::EXTLOAD, VT, SmallVT, Expand); in RISCVTargetLowering()
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