Home
last modified time | relevance | path

Searched refs:SDIV (Results 1 – 25 of 66) sorted by relevance

123

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp341 case ISD::SDIV: in Select()
352 if (N->getOpcode() == ISD::SDIV) { in Select()
364 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h100 case ISD::SDIV:
H A DLanaiISelLowering.cpp106 setOperationAction(ISD::SDIV, MVT::i32, Expand); in LanaiTargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp271 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || in getArithmeticInstrCost()
276 if (ISD == ISD::SDIV || ISD == ISD::SREM) { in getArithmeticInstrCost()
341 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
361 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
383 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
385 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
402 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
406 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
421 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
425 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence in getArithmeticInstrCost()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1276 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1280 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1284 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
1288 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
1293 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1297 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1301 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1305 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
1806 case ISD::SDIV: in maybeLoweredToCall()
H A DARMScheduleSwift.td321 (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
H A DARMISelLowering.cpp208 setOperationAction(ISD::SDIV, VT, Expand); in addTypeForNEON()
287 setOperationAction(ISD::SDIV, VT, Expand); in addMVEVectorTypes()
899 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); in ARMTargetLowering()
900 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); in ARMTargetLowering()
1180 setOperationAction(ISD::SDIV, MVT::i32, LibCall); in ARMTargetLowering()
1185 setOperationAction(ISD::SDIV, MVT::i32, Custom); in ARMTargetLowering()
1188 setOperationAction(ISD::SDIV, MVT::i64, Custom); in ARMTargetLowering()
9407 if (N->getOpcode() != ISD::SDIV) in BuildSDIVPow2()
9900 case ISD::SDIV: in LowerOperation()
10024 case ISD::SDIV: in ReplaceNodeResults()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h235 SDIV, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1928 case ISD::SDIV: in selectDivRem()
1930 DivOpc = Mips::SDIV; in selectDivRem()
2043 if (!selectBinaryOp(I, ISD::SDIV)) in fastSelectInstruction()
2044 return selectDivRem(I, ISD::SDIV); in fastSelectInstruction()
H A DMipsSEISelLowering.cpp240 setOperationAction(ISD::SDIV, MVT::i32, Legal); in MipsSETargetLowering()
287 setOperationAction(ISD::SDIV, MVT::i64, Legal); in MipsSETargetLowering()
339 setOperationAction(ISD::SDIV, Ty, Legal); in addMSAIntType()
1810 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
H A DMipsScheduleP5600.td192 def : InstRW<[P5600WriteAL2Div], (instrs DIV, PseudoSDIV, SDIV)>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp193 case ISD::SDIV: { in Select()
/netbsd-src/sys/external/bsd/sljit/dist/sljit_src/
H A DsljitNativeARM_64.c111 #define SDIV 0x9ac00c00 macro
1275 …FAIL_IF(push_inst(compiler, ((op == SLJIT_DIVMOD_UW ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN… in sljit_emit_op0()
1280 …return push_inst(compiler, ((op == SLJIT_DIV_UW ? UDIV : SDIV) ^ inv_bits) | RD(SLJIT_R0) | RN(SLJ… in sljit_emit_op0()
H A DsljitNativeSPARC_common.c177 #define SDIV (OPC1(0x2) | OPC3(0x0f)) macro
810 …FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? UDIV : SDIV) | D(SLJIT_R0) | S1(SLJIT_R0… in sljit_emit_op0()
/netbsd-src/external/gpl3/gdb/dist/sim/erc32/
H A DChangeLog-2021796 written?), but reversed in the SDIV, SDIVcc, UDIV, UDIVcc cases
901 * exec.c (SDIV, SDIVCC, UDIV, UDIVCC): Define new opcodes.
904 * (dispatch_instruction): Add emulation of SDIV, SDIVCC, UDIV,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp135 setOperationAction(ISD::SDIV, MVT::i8, Promote); in MSP430TargetLowering()
141 setOperationAction(ISD::SDIV, MVT::i16, LibCall); in MSP430TargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp234 case ISD::SDIV: return "sdiv"; in getOperationName()
H A DFastISel.cpp500 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && in selectBinaryOp()
1696 return selectBinaryOp(I, ISD::SDIV); in selectOperator()
H A DLegalizeDAG.cpp3258 case ISD::SDIV: { in ExpandNode()
3259 bool isSigned = Node->getOpcode() == ISD::SDIV; in ExpandNode()
4313 case ISD::SDIV: in ConvertNodeToLibcall()
4488 case ISD::SDIV: in PromoteNode()
4506 case ISD::SDIV: in PromoteNode()
H A DLegalizeVectorOps.cpp368 case ISD::SDIV: in LegalizeOp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp910 case ISD::SDIV: in canOpTrap()
1762 case SDiv: return ISD::SDIV; in InstructionOpcodeToISD()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp208 setOperationAction(ISD::SDIV, XLenVT, Expand); in RISCVTargetLowering()
217 setOperationAction(ISD::SDIV, MVT::i8, Custom); in RISCVTargetLowering()
220 setOperationAction(ISD::SDIV, MVT::i16, Custom); in RISCVTargetLowering()
223 setOperationAction(ISD::SDIV, MVT::i32, Custom); in RISCVTargetLowering()
686 setOperationAction(ISD::SDIV, VT, Custom); in RISCVTargetLowering()
2358 case ISD::SDIV: in LowerOperation()
4573 case ISD::SDIV: in getRISCVWOpcode()
4749 case ISD::SDIV: in ReplaceNodeResults()
4765 ExtOpc = N->getOpcode() == ISD::SDIV ? ISD::SIGN_EXTEND in ReplaceNodeResults()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp149 setOperationAction(ISD::SDIV, MVT::i8, Expand); in AVRTargetLowering()
150 setOperationAction(ISD::SDIV, MVT::i16, Expand); in AVRTargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1142 setOperationAction(ISD::SDIV, VT, Custom); in AArch64TargetLowering()
1295 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); in AArch64TargetLowering()
1296 setOperationAction(ISD::SDIV, MVT::v16i8, Custom); in AArch64TargetLowering()
1297 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); in AArch64TargetLowering()
1298 setOperationAction(ISD::SDIV, MVT::v8i16, Custom); in AArch64TargetLowering()
1299 setOperationAction(ISD::SDIV, MVT::v2i32, Custom); in AArch64TargetLowering()
1300 setOperationAction(ISD::SDIV, MVT::v4i32, Custom); in AArch64TargetLowering()
1301 setOperationAction(ISD::SDIV, MVT::v1i64, Custom); in AArch64TargetLowering()
1302 setOperationAction(ISD::SDIV, MVT::v2i64, Custom); in AArch64TargetLowering()
1400 setOperationAction(ISD::SDIV, VT, Expand); in addTypeForNEON()
[all …]
H A DAArch64TargetTransformInfo.cpp981 case ISD::SDIV: in getArithmeticInstrCost()

123