| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 123 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
488 def: Pat<(sext_inreg I64:$Rs, i32), (A2_sxtw (LoReg $Rs))>;
489 def: Pat<(sext_inreg I64:$Rs, i16), (A2_sxtw (A2_sxth (LoReg $Rs)))>;
490 def: Pat<(sext_inreg I64:$Rs, i8), (A2_sxtw (A2_sxtb (LoReg $Rs)))>;
496 def: Pat<(i32 (trunc I64:$Rs)), (LoReg $Rs)>;
498 def: Pat<(i1 (trunc I64:$Rs)), (S2_tstbit_i (LoReg $Rs), 0)>;
522 (A2_andir (LoReg (C2_mask V2I1:$Pu)), (i32 0x00010001))>;
526 (A2_andir (LoReg (C2_mask V4I1:$Pu)), (i32 0x01010101))>;
538 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
541 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
[all …]
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| H A D | HexagonCopyToCombine.cpp | 767 Register LoReg = LoOperand.getReg(); in emitCombineIR() local
778 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
786 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
793 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
801 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
808 .addReg(LoReg, LoRegKillFlag); in emitCombineIR()
866 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
885 .addReg(LoReg, LoRegKillFlag); in emitCombineRR()
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| H A D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 1127 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); in insertCFIInstructionsAt() local
1129 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); in insertCFIInstructionsAt()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 271 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg, in splitReg() argument
275 LoReg = getSubReg(Reg, AVR::sub_lo); in splitReg()
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| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1873 Register LoReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
1875 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), LoReg) in selectG_TRUNC()
1891 .addReg(LoReg, RegState::Implicit); in selectG_TRUNC()
1914 .addReg(LoReg) in selectG_TRUNC()
2147 Register LoReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
2150 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg) in selectG_CONSTANT()
2157 .addReg(LoReg) in selectG_CONSTANT()
2202 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2207 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), LoReg) in selectG_FNEG()
2220 .addReg(LoReg) in selectG_FNEG()
[all …]
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| H A D | SILoadStoreOptimizer.cpp | 166 Register LoReg; member
1681 assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 || in computeBase()
1703 .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg) in computeBase()
1814 Addr.Base.LoReg = BaseLo.getReg(); in processBaseWithConstOffset()
1862 << MAddr.Base.LoReg << "} Offset: " << MAddr.Offset << "\n\n";); in promoteConstantOffsetToImm()
1918 if (MAddrNext.Base.LoReg != MAddr.Base.LoReg || in promoteConstantOffsetToImm()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4963 unsigned LoReg, ROpc, MOpc; in Select() local
4967 LoReg = X86::AL; in Select()
4972 LoReg = X86::AX; in Select()
4977 LoReg = X86::EAX; in Select()
4982 LoReg = X86::RAX; in Select()
4997 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
5042 unsigned LoReg, HiReg; in Select() local
5055 LoReg = UseMULX ? X86::EDX : X86::EAX; in Select()
5065 LoReg = UseMULX ? X86::RDX : X86::RAX; in Select()
5079 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 308 Register LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
857 .addReg(LoReg); in expandBuildPairF64()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1833 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
1834 if (JumpReg == LoReg) in CMSEPushCalleeSaves()
1836 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
1853 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves() local
1854 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
1859 .addReg(LoReg, RegState::Kill); in CMSEPushCalleeSaves()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6229 Register LoReg = MI.getOperand(0).getReg(); in emitReadCycleWidePseudo() local
6237 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg) in emitReadCycleWidePseudo()
6265 Register LoReg = MI.getOperand(0).getReg(); in emitSplitF64Pseudo() local
6278 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) in emitSplitF64Pseudo()
6300 Register LoReg = MI.getOperand(1).getReg(); in emitBuildPairF64Pseudo() local
6311 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())) in emitBuildPairF64Pseudo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11970 Register LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local
11974 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()
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