| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| H A D | InstructionCost.h | 214 InstructionCost LHS2(LHS);
215 LHS2 += RHS;
216 return LHS2;
221 InstructionCost LHS2(LHS);
222 LHS2 -= RHS;
223 return LHS2;
228 InstructionCost LHS2(LHS);
229 LHS2 *= RHS;
230 return LHS2;
235 InstructionCost LHS2(LHS);
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 2926 Value *LHS2, *RHS2; in visitSelectInst() local
2927 if (SelectPatternFlavor SPF2 = matchSelectPattern(LHS, LHS2, RHS2).Flavor) in visitSelectInst()
2928 if (Instruction *R = foldSPFofSPF(cast<Instruction>(LHS), SPF2, LHS2, in visitSelectInst()
2931 if (SelectPatternFlavor SPF2 = matchSelectPattern(RHS, LHS2, RHS2).Flavor) in visitSelectInst()
2932 if (Instruction *R = foldSPFofSPF(cast<Instruction>(RHS), SPF2, LHS2, in visitSelectInst()
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| H A D | InstCombineCompares.cpp | 2694 Value *LHS2, *RHS2; in matchThreeWayIntCompare() local
2695 if (!match(UnequalVal, m_Select(m_ICmp(PredB, m_Value(LHS2), m_Value(RHS2)), in matchThreeWayIntCompare()
2700 if (LHS2 != LHS) { in matchThreeWayIntCompare()
2702 std::swap(LHS2, RHS2); in matchThreeWayIntCompare()
2705 if (LHS2 != LHS) in matchThreeWayIntCompare()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 669 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, in getAVRCmp() local
696 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp); in getAVRCmp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 2788 const Value *LHS2 = nullptr, *RHS2 = nullptr; in isSignedMinMaxClamp() local
2789 SelectPatternFlavor SPF2 = matchSelectPattern(LHS, LHS2, RHS2).Flavor; in isSignedMinMaxClamp()
2799 In = LHS2; in isSignedMinMaxClamp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5420 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
5422 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
5424 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask); in OptimizeVFPBrcond()
5429 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
11493 Register LHS2 = MI.getOperand(2).getReg(); in EmitInstrWithCustomInserter() local
11500 .addReg(LHS2).addImm(0) in EmitInstrWithCustomInserter()
11510 .addReg(LHS2).addReg(RHS2) in EmitInstrWithCustomInserter()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6087 SDValue LHS1, LHS2; in splitVectorIntBinary() local
6088 std::tie(LHS1, LHS2) = splitVector(Op.getOperand(0), DAG, dl); in splitVectorIntBinary()
6098 DAG.getNode(Op.getOpcode(), dl, HiVT, LHS2, RHS2)); in splitVectorIntBinary()
22764 SDValue LHS1, LHS2; in splitIntVSETCC() local
22765 std::tie(LHS1, LHS2) = splitVector(LHS, DAG, dl); in splitIntVSETCC()
22776 DAG.getNode(ISD::SETCC, dl, HiVT, LHS2, RHS2, CC)); in splitIntVSETCC()
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