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Searched refs:In64BitMode (Results 1 – 25 of 28) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrSNP.td21 Requires<[In64BitMode]>;
26 XD, Requires<[In64BitMode]>;
35 Requires<[In64BitMode]>;
40 Requires<[In64BitMode]>;
43 def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
44 def : InstAlias<"pvalidate\t{%rax|rax}", (PVALIDATE64)>, Requires<[In64BitMode]>;
46 def : InstAlias<"rmpupdate\t{%rax|rax}", (RMPUPDATE)>, Requires<[In64BitMode]>;
47 def : InstAlias<"rmpadjust\t{%rax|rax}", (RMPADJUST)>, Requires<[In64BitMode]>;
H A DX86InstrSVM.td37 Requires<[In64BitMode]>;
45 Requires<[In64BitMode]>;
53 Requires<[In64BitMode]>;
61 "invlpga", []>, TB, Requires<[In64BitMode]>;
66 def : InstAlias<"vmrun\t{%rax|rax}", (VMRUN64), 0>, Requires<[In64BitMode]>;
68 def : InstAlias<"vmload\t{%rax|rax}", (VMLOAD64), 0>, Requires<[In64BitMode]>;
70 def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
72 def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;
H A DX86InstrControl.td26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
54 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
122 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
142 [(brind GR64:$dst)]>, Requires<[In64BitMode]>,
145 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>,
179 [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>,
183 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK;
[all …]
H A DX86InstrVMX.td24 Requires<[In64BitMode]>;
32 Requires<[In64BitMode]>;
52 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
60 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
68 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
76 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
H A DX86InstrMPX.td24 Requires<[In64BitMode]>;
35 Requires<[In64BitMode]>;
42 Requires<[In64BitMode]>;
57 Requires<[In64BitMode]>, NotMemoryFoldable;
69 Requires<[In64BitMode]>, NotMemoryFoldable;
H A DX86InstrSystem.td63 Requires<[In64BitMode]>;
69 Requires<[In64BitMode]>;
130 Requires<[In64BitMode]>;
137 Requires<[In64BitMode]>;
149 Requires<[In64BitMode]>;
156 Requires<[In64BitMode]>;
179 Requires<[In64BitMode]>;
296 OpSize32, Requires<[In64BitMode]>;
298 OpSize32, Requires<[In64BitMode]>;
321 OpSize32, Requires<[In64BitMode]>;
[all …]
H A DX86Subtarget.h521 bool In64BitMode = false; variable
596 return In64BitMode; in is64Bit()
609 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 || in isTarget64BitILP32()
615 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 && in isTarget64BitLP64()
872 bool isTargetWin64() const { return In64BitMode && isOSWindows(); } in isTargetWin64()
874 bool isTargetWin32() const { return !In64BitMode && isOSWindows(); } in isTargetWin32()
H A DX86InstrExtension.td22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
158 Sched<[WriteALU]>, Requires<[In64BitMode]>;
162 Sched<[WriteALULd]>, Requires<[In64BitMode]>;
170 Sched<[WriteALU]>, OpSize16, Requires<[In64BitMode]>;
173 Sched<[WriteALU]>, OpSize32, Requires<[In64BitMode]>;
177 Sched<[WriteALULd]>, OpSize16, Requires<[In64BitMode]>;
180 Sched<[WriteALULd]>, OpSize32, Requires<[In64BitMode]>;
H A DX86Subtarget.cpp232 if (In64BitMode || isTargetWin32()) in isLegalToCallImmediateAddr()
264 if (In64BitMode && !HasX86_64) in initSubtargetFeatures()
274 isTargetNaCl() || In64BitMode) in initSubtargetFeatures()
H A DX86InstrInfo.td998 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
1278 Requires<[In64BitMode]>;
1286 Requires<[In64BitMode]>;
1301 Requires<[In64BitMode]>;
1379 Requires<[In64BitMode]>;
1392 Requires<[In64BitMode]>;
1412 OpSize32, Requires<[In64BitMode]>;
1416 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable;
1421 OpSize32, Requires<[In64BitMode]>;
1424 OpSize32, Requires<[In64BitMode]>;
[all …]
H A DX86InstrShiftRotate.td83 Requires<[In64BitMode]>;
101 Requires<[In64BitMode]>;
118 Requires<[In64BitMode]>;
183 Requires<[In64BitMode]>;
201 Requires<[In64BitMode]>;
218 Requires<[In64BitMode]>;
286 Requires<[In64BitMode]>;
304 Requires<[In64BitMode]>;
321 Requires<[In64BitMode]>;
408 "rcl{q}\t$dst", []>, Requires<[In64BitMode]>;
[all …]
H A DX86InstrAMX.td17 let Predicates = [HasAMXTILE, In64BitMode] in {
77 let Predicates = [HasAMXINT8, In64BitMode] in {
149 let Predicates = [HasAMXBF16, In64BitMode] in {
H A DX86InstrTDX.td18 let SchedRW = [WriteSystem], Predicates = [In64BitMode] in {
H A DX86InstrCompiler.td95 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>;
102 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>;
122 Requires<[In64BitMode]>;
139 Requires<[In64BitMode]>;
165 Requires<[In64BitMode]>;
177 Requires<[In64BitMode]>, Sched<[WriteALU]>;
220 Requires<[In64BitMode]>;
229 Requires<[In64BitMode]>;
370 Requires<[NotLP64, In64BitMode]>;
413 Requires<[NotLP64, In64BitMode]>;
[all …]
H A DX86InstrArithmetic.td32 OpSize32, Requires<[In64BitMode]>;
105 Requires<[In64BitMode]>;
143 Requires<[In64BitMode]>;
311 Requires<[In64BitMode]>;
342 Requires<[In64BitMode]>;
388 Requires<[In64BitMode]>;
423 Requires<[In64BitMode]>;
480 let Predicates = [UseIncDec, In64BitMode] in {
528 let Predicates = [UseIncDec, In64BitMode] in {
976 let Predicates = [In64BitMode] in
[all …]
H A DX86InstrFPStack.td762 PS, Requires<[HasFXSR, In64BitMode]>;
771 PS, Requires<[HasFXSR, In64BitMode]>;
H A DX86InstrMMX.td558 let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
H A DX86.td22 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
H A DX86InstrFormats.td997 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,In64BitMode]>;
H A DX86InstrSSE.td4009 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4020 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4904 TB, Requires<[HasSSE3, In64BitMode]>;
4912 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
4917 Requires<[In64BitMode]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td79 [(retflag)]>, Requires<[In64BitMode]>;
84 Requires<[In64BitMode]>;
88 Requires<[In64BitMode]>;
92 Requires<[In64BitMode]>;
95 Requires<[In64BitMode]>;
163 Requires<[In64BitMode]>;
169 Requires<[In64BitMode]>;
173 Requires<[In64BitMode]>;
176 Requires<[In64BitMode]>;
188 Requires<[In64BitMode]>;
[all …]
H A DPPCInstrVSX.td1304 Requires<[In64BitMode]>;
1310 Requires<[In64BitMode]>;
1322 Requires<[In64BitMode]>;
1328 Requires<[In64BitMode]>;
1355 []>, Requires<[In64BitMode]>;
1359 []>, Requires<[In64BitMode]>;
H A DPPCInstrInfo.td1156 def In64BitMode : Predicate<"Subtarget->isPPC64()">;
5312 let Predicates = [In64BitMode] in
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstrFPU.td105 // S64 - single precision in 32 64bit fp registers (In64BitMode)
107 // D64 - double precision in 32 64bit fp registers (In64BitMode)
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTarget.td1448 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1453 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;

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