| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 529 INSERT_SUBVECTOR, enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 440 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
521 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
585 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
634 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
745 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
1260 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero); in convertToScalableVector()
2300 case ISD::INSERT_SUBVECTOR: in LowerOperation()
2325 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Vec, OpIdx.value(), in LowerOperation()
3707 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ExtVecVT, Vec, SubVec, in lowerINSERT_SUBVECTOR()
3727 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, in lowerINSERT_SUBVECTOR()
[all …]
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| H A D | RISCVISelDAGToDAG.cpp | 1042 case ISD::INSERT_SUBVECTOR: { in Select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 923 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1289 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1297 Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, Hi.getValueType(), Hi, SubVec, in SplitVecRes_INSERT_SUBVECTOR()
2157 case ISD::INSERT_SUBVECTOR: Res = SplitVecOp_INSERT_SUBVECTOR(N, OpNo); break; in SplitVectorOperand()
2396 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Lo, Idx); in SplitVecOp_INSERT_SUBVECTOR()
2398 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, FirstInsertion, Hi, in SplitVecOp_INSERT_SUBVECTOR()
3493 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
3496 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
4527 case ISD::INSERT_SUBVECTOR: Res = WidenVecOp_INSERT_SUBVECTOR(N); break; in WidenVectorOperand()
4637 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT, in WidenVecOp_EXTEND()
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| H A D | LegalizeVectorOps.cpp | 1009 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1068 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
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| H A D | SelectionDAGDumper.cpp | 287 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
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| H A D | DAGCombiner.cpp | 1717 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
19073 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
19937 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
20322 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
21479 SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
21488 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
21491 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0), in visitINSERT_SUBVECTOR()
21497 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
21499 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0, in visitINSERT_SUBVECTOR()
21531 if (NewIdx && hasOperation(ISD::INSERT_SUBVECTOR, NewVT)) { in visitINSERT_SUBVECTOR()
[all …]
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| H A D | SelectionDAG.cpp | 2874 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
4123 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
5874 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
6055 case ISD::INSERT_SUBVECTOR: { in getNode()
10171 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
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| H A D | TargetLowering.cpp | 830 case ISD::INSERT_SUBVECTOR: { in SimplifyMultipleUseDemandedBits()
1041 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedBits()
2571 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
2589 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in SimplifyDemandedVectorElts()
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| H A D | SelectionDAGBuilder.cpp | 630 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
7127 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResultVT, Vec, SubVec, in visitIntrinsicCall()
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| H A D | LegalizeDAG.cpp | 2984 case ISD::INSERT_SUBVECTOR: in ExpandNode()
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| H A D | LegalizeIntegerTypes.cpp | 4928 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 827 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1422 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1500 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1725 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1877 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2010 setTargetDAGCombine(ISD::INSERT_SUBVECTOR); in X86TargetLowering()
5951 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx); in insertSubVector()
5976 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec, in widenSubVector()
6005 if (N->getOpcode() == ISD::INSERT_SUBVECTOR) { in collectConcatOps()
6016 if (Src.getOpcode() == ISD::INSERT_SUBVECTOR && in collectConcatOps()
[all …]
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| H A D | X86ISelDAGToDAG.cpp | 708 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
922 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
925 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
950 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
953 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 121 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
225 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
2102 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
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| H A D | HexagonISelLowering.cpp | 1648 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1698 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3138 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 257 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
365 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom); in SITargetLowering()
366 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom); in SITargetLowering()
367 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom); in SITargetLowering()
368 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom); in SITargetLowering()
371 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom); in SITargetLowering()
372 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom); in SITargetLowering()
373 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom); in SITargetLowering()
374 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom); in SITargetLowering()
580 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
[all …]
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| H A D | AMDGPUISelLowering.cpp | 1564 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1567 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 608 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR) in checkHighLaneIndex()
3461 case ISD::INSERT_SUBVECTOR: { in Select()
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| H A D | AArch64ISelLowering.cpp | 1129 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1171 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1218 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
4566 case ISD::INSERT_SUBVECTOR: in LowerOperation()
8160 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), in WidenVector()
17349 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, Zero); in convertToScalableVector()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 689 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
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