Searched refs:FReg (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | EarlyIfConversion.cpp | 114 unsigned TReg, FReg; member
119 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {} in PHIInfo()
519 PI.FReg = PI.PHI->getOperand(i).getReg(); in canConvertIf()
522 assert(Register::isVirtualRegister(PI.FReg) && "Bad PHI"); in canConvertIf()
526 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles, in canConvertIf()
563 Register FReg) { in hasSameValue() argument
564 if (TReg == FReg) in hasSameValue()
567 if (!TReg.isVirtual() || !FReg.isVirtual()) in hasSameValue()
571 const MachineInstr *FDef = MRI.getUniqueVRegDef(FReg); in hasSameValue()
599 int FIdx = FDef->findRegisterDefOperandIdx(FReg); in hasSameValue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 590 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); in insertSelect() local
592 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
594 FalseReg = FReg; in insertSelect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8116 unsigned FReg = StringSwitch<unsigned>(Constraint.lower()) in getRegForInlineAsmConstraint() local
8150 if (FReg != RISCV::NoRegister) { in getRegForInlineAsmConstraint()
8151 assert(RISCV::F0_F <= FReg && FReg <= RISCV::F31_F && "Unknown fp-reg"); in getRegForInlineAsmConstraint()
8153 unsigned RegNo = FReg - RISCV::F0_F; in getRegForInlineAsmConstraint()
8157 return std::make_pair(FReg, &RISCV::FPR32RegClass); in getRegForInlineAsmConstraint()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3095 const Register FReg = I.getOperand(3).getReg(); in select() local
3106 if (!emitSelect(I.getOperand(0).getReg(), TReg, FReg, AArch64CC::NE, MIB)) in select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6602 unsigned FReg = State.AllocateReg(FPR); in CC_AIX() local
6603 if (FReg) in CC_AIX()
6604 State.addLoc(CCValAssign::getReg(ValNo, ValVT, FReg, LocVT, LocInfo)); in CC_AIX()
6609 assert(FReg && "An FPR should be available when a GPR is reserved."); in CC_AIX()
6626 FReg ? CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, in CC_AIX()
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