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Searched refs:Cycle (Results 1 – 25 of 46) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h89 DenseMap<MachineInstr *, int> Cycle; variable
107 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
109 : Loop(Loop), ScheduledInstrs(ScheduledInstrs), Cycle(std::move(Cycle)), in ModuloSchedule()
126 int getFirstCycle() { return Cycle[ScheduledInstrs.front()]; } in getFirstCycle()
130 int getFinalCycle() { return Cycle[ScheduledInstrs.back()]; } in getFinalCycle()
140 auto I = Cycle.find(MI); in getCycle()
141 return I == Cycle.end() ? -1 : I->second; in getCycle()
H A DScheduleDAG.h546 void setCurCycle(unsigned Cycle) { in setCurCycle() argument
547 CurCycle = Cycle; in setCurCycle()
H A DMachineTraceMetrics.h77 unsigned Cycle = 0; member
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td458 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
521 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
629 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
653 // 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
661 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
678 // 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
686 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
695 // 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
704 // 6 Cycle Load uses a single slice.
710 // 5 Cycle Load uses a single slice.
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineTraceMetrics.cpp792 unsigned Cycle = 0; in updateDepth() local
805 Cycle = std::max(Cycle, DepCycle); in updateDepth()
809 MICycles.Depth = Cycle; in updateDepth()
813 TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height); in updateDepth()
814 LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI); in updateDepth()
816 LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI); in updateDepth()
919 unsigned DepHeight = I->Cycle; in updatePhysDepsUpwards()
938 if (LRU.Cycle <= Height && LRU.MI != &MI) { in updatePhysDepsUpwards()
939 LRU.Cycle = Height; in updatePhysDepsUpwards()
1038 RegUnits[LI.Reg].Cycle = LI.Height; in computeInstrHeights()
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H A DMachinePipeliner.cpp614 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in schedule() local
615 ++Cycle) { in schedule()
616 for (SUnit *SU : Schedule.getInstructions(Cycle)) { in schedule()
618 Cycles[SU->getInstr()] = Cycle; in schedule()
2914 for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) { in finalizeSchedule() local
2915 std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[Cycle]; in finalizeSchedule()
H A DModuloSchedule.cpp2139 static void parseSymbolString(StringRef S, int &Cycle, int &Stage) { in parseSymbolString() argument
2153 CycleTokenAndValue.second.drop_front().getAsInteger(10, Cycle); in parseSymbolString()
2155 dbgs() << " Stage=" << Stage << ", Cycle=" << Cycle << "\n"; in parseSymbolString()
2163 DenseMap<MachineInstr *, int> Cycle, Stage; in runOnLoop() local
2171 parseSymbolString(Sym->getName(), Cycle[&MI], Stage[&MI]); in runOnLoop()
2175 ModuloSchedule MS(MF, &L, std::move(Instrs), std::move(Cycle), in runOnLoop()
H A DIfConversion.cpp287 unsigned Cycle, unsigned Extra, in MeetIfcvtSizeLimit() argument
289 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra, in MeetIfcvtSizeLimit()
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/AST/
H A DASTImporter.h197 using Cycle = llvm::iterator_range<VecTy::const_reverse_iterator>; variable
198 Cycle getCycleAtBack() const { in getCycleAtBack()
200 return Cycle(Nodes.rbegin(), in getCycleAtBack()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DInstruction.h299 bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; } in contains() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp598 bool findCycle(Value *Out, Value *In, ValueSeq &Cycle);
599 void classifyCycle(Instruction *DivI, ValueSeq &Cycle, ValueSeq &Early,
1134 ValueSeq &Cycle) { in findCycle() argument
1155 if (Cycle.count(I)) in findCycle()
1157 Cycle.insert(I); in findCycle()
1158 if (findCycle(I, In, Cycle)) in findCycle()
1160 Cycle.remove(I); in findCycle()
1162 return !Cycle.empty(); in findCycle()
1166 ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) { in classifyCycle() argument
1172 unsigned I, N = Cycle.size(); in classifyCycle()
[all …]
/netbsd-src/crypto/external/bsd/openssl/dist/doc/life-cycles/
H A DREADME.md1 Algorithm Life-Cycle Diagrams
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp439 unsigned Cycle = getTransSwizzle(TransSwz, i); in isLegalUpTo() local
444 if (Vector[Src.second][Cycle] < 0) in isLegalUpTo()
445 Vector[Src.second][Cycle] = Src.first; in isLegalUpTo()
446 if (Vector[Src.second][Cycle] != Src.first) in isLegalUpTo()
500 unsigned Cycle = getTransSwizzle(TransSwz, i); in isConstCompatible() local
503 if (ConstCount > 0 && Cycle == 0) in isConstCompatible()
505 if (ConstCount > 1 && Cycle == 1) in isConstCompatible()
/netbsd-src/sys/arch/sparc/stand/boot/
H A Dversion18 1.13: add additional match function pointer and prom patch Cycle 5 IP
/netbsd-src/sys/external/bsd/acpica/dist/tools/examples/
H A Dextables.c336 [0001] Duty Cycle Offset : 00
337 [0001] Duty Cycle Width : 00
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h62 void notifyExecuted(unsigned Cycle);
/netbsd-src/external/apache2/llvm/dist/llvm/docs/CommandGuide/
H A Dllvm-mca.rst27 Per Cycle (IPC), as well as hardware resource pressure. The analysis and
335 uOps Per Cycle: 1.48
388 **IPC**, **uOps Per Cycle**, and **Block RThroughput** (Block Reciprocal
409 Field 'uOps Per Cycle' is computed dividing the total number of simulated micro
412 data dependencies, the observed 'uOps Per Cycle' should tend to a theoretical
416 Field *uOps Per Cycle* is bounded from above by the dispatch width. That is
418 and 'uOps Per Cycle' are limited by the amount of hardware parallelism. The
422 Cycle (computed by dividing the number of uOps of a single iteration by the
428 are no loop-carried dependencies, the observed `uOps Per Cycle` is expected to
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp36 void WriteRef::notifyExecuted(unsigned Cycle) { in notifyExecuted() argument
38 WriteBackCycle = Cycle; in notifyExecuted()
/netbsd-src/external/gpl3/binutils.old/dist/gas/doc/
H A Dc-lm32.texi105 Cycle counter.
/netbsd-src/external/gpl3/binutils/dist/gas/doc/
H A Dc-lm32.texi105 Cycle counter.
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DBugLifeCycle.rst2 LLVM Bug Life Cycle
/netbsd-src/external/gpl3/gcc.old/dist/libphobos/src/std/range/
H A Dpackage.d3451 struct Cycle(R)
3527 @property Cycle save() in save()
3530 return Cycle(_original, _index); in save()
3606 @property Cycle save() in save()
3609 Cycle ret = this; in save()
3618 template Cycle(R)
3621 alias Cycle = R; variable
3625 struct Cycle(R)
3673 @property inout(Cycle) save() inout @safe in inout() argument
3701 return cast(inout) Cycle(*cast(R*)(p), idx); in opSlice()
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/netbsd-src/external/gpl3/gcc/dist/libphobos/src/std/range/
H A Dpackage.d3883 struct Cycle(R)
3959 @property Cycle save()
3962 return Cycle(_original, _index);
4044 @property Cycle save()
4047 return Cycle(_original, _current.save);
4053 template Cycle(R)
4056 alias Cycle = R;
4060 struct Cycle(R)
4108 @property inout(Cycle) save() inout @safe
4136 return cast(inout) Cycle(*cast(R*)(p), idx);
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/netbsd-src/distrib/syspkg/mk/
H A Dbsd.syspkg.mk408 ${SHCOMMENT} Cycle through some FTP server here ;\
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Darm1136jfs.md255 ;; stat prediction. Cycle count ranges from zero (unconditional branch,

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