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Searched refs:OpCode (Results 1 – 25 of 50) sorted by relevance

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/llvm-project/clang-tools-extra/clang-tidy/readability/
H A DContainerSizeEmptyCheck.cpp291 const auto OpCode = BinaryOp->getOpcode(); in check() local
297 if (Value == 1 && (OpCode == BinaryOperatorKind::BO_EQ || in check()
298 OpCode == BinaryOperatorKind::BO_NE)) in check()
303 if ((OpCode == BinaryOperatorKind::BO_GT && !ContainerIsLHS) || in check()
304 (OpCode == BinaryOperatorKind::BO_LT && ContainerIsLHS) || in check()
305 (OpCode == BinaryOperatorKind::BO_LE && !ContainerIsLHS) || in check()
306 (OpCode == BinaryOperatorKind::BO_GE && ContainerIsLHS)) in check()
312 if ((OpCode == BinaryOperatorKind::BO_GT && ContainerIsLHS) || in check()
313 (OpCode == BinaryOperatorKind::BO_LT && !ContainerIsLHS)) in check()
315 if ((OpCode == BinaryOperatorKind::BO_LE && ContainerIsLHS) || in check()
[all …]
/llvm-project/llvm/lib/Target/DirectX/
H A DDXILOpBuilder.h41 CallInst *createOp(dxil::OpCode Op, ArrayRef<Value *> Args,
46 Expected<CallInst *> tryCreateOp(dxil::OpCode Op, ArrayRef<Value *> Args,
66 static const char *getOpCodeName(dxil::OpCode DXILOp);
71 FunctionType *getOpFunctionType(dxil::OpCode OpCode,
H A DDXILOpBuilder.cpp148 dxil::OpCode OpCode; in constructOverloadName()
334 static FunctionType *getDXILOpFunctionType(dxil::OpCode OpCode,
338 switch (OpCode) {
339 #define DXIL_OP_FUNCTION_TYPE(OpCode, RetType, ...) \
340 case OpCode: \
347 llvm_unreachable("Invalid OpCode?");
368 // Helper function to pack an OpCode and VersionTuple into a uint64_t for use
370 constexpr static uint64_t computeSwitchEnum(dxil::OpCode OpCod
128 dxil::OpCode OpCode; global() member
255 createDXILOpCall(dxil::OpCode OpCode,Type * ReturnTy,Type * OverloadTy,SmallVector<Value * > Args) createDXILOpCall() argument
279 getOverloadTy(dxil::OpCode OpCode,FunctionType * FT) getOverloadTy() argument
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H A DDXILOpLowering.cpp124 replaceFunctionWithOp(Function &F, dxil::OpCode DXILOp, in lowerIntrinsics()
164 Function &F, dxil::OpCode DXILOp, Type *NewRetTy,
282 OpBuilder.tryCreateOp(OpCode::CreateHandle, Args, CI->getName());
329 OpCode::CreateHandleFromBinding, BindArgs, CI->getName());
336 OpCode::AnnotateHandle, AnnotateArgs,
405 OpCode::CheckAccessFullyMapped, {NewEVI},
535 OpCode::BufferLoad, Args, CI->getName(), NewRetTy);
572 ? OpBuilder.tryCreateOp(OpCode::RawBufferLoad,
575 : OpBuilder.tryCreateOp(OpCode::BufferLoad,
600 OpCode
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/llvm-project/llvm/tools/obj2yaml/
H A Dmacho2yaml.cpp375 for (auto OpCode = RebaseOpcodes.begin(); OpCode != RebaseOpcodes.end(); in dumpRebaseOpcodes() local
376 ++OpCode) { in dumpRebaseOpcodes()
379 static_cast<MachO::RebaseOpcode>(*OpCode & MachO::REBASE_OPCODE_MASK); in dumpRebaseOpcodes()
380 RebaseOp.Imm = *OpCode & MachO::REBASE_IMMEDIATE_MASK; in dumpRebaseOpcodes()
388 ULEB = decodeULEB128(OpCode + 1, &Count); in dumpRebaseOpcodes()
390 OpCode += Count; in dumpRebaseOpcodes()
398 ULEB = decodeULEB128(OpCode + 1, &Count); in dumpRebaseOpcodes()
400 OpCode += Count; in dumpRebaseOpcodes()
423 for (auto OpCode = OpcodeBuffer.begin(); OpCode != OpcodeBuffer.end(); in dumpBindOpcodes() local
424 ++OpCode) { in dumpBindOpcodes()
[all …]
/llvm-project/mlir/lib/Rewrite/
H A DByteCode.cpp82 enum OpCode : ByteCodeField { enum
352 void append(OpCode opCode) { bytecode.push_back(opCode); } in append()
775 writer.append(OpCode::ApplyConstraint, constraintToMemIndex[op.getName()]); in generate()
797 writer.append(OpCode::ApplyRewrite, externalRewriterToMemIndex[op.getName()]); in generate()
816 writer.append(OpCode::AreRangesEqual); in generate()
822 writer.append(OpCode::AreEqual, lhs, op.getRhs(), op.getSuccessors()); in generate()
825 writer.append(OpCode::Branch, SuccessorRange(op.getOperation())); in generate()
829 writer.append(OpCode::AreEqual, op.getAttribute(), op.getConstantValue(), in generate()
834 writer.append(OpCode::CheckOperandCount, op.getInputOp(), op.getCount(), in generate()
840 writer.append(OpCode::CheckOperationName, op.getInputOp(), in generate()
[all …]
/llvm-project/llvm/lib/Target/ARM/
H A DARMBranchTargets.cpp98 unsigned OpCode = ARM::t2BTI; in addBTI() local
112 OpCode = ARM::t2PACBTI; in addBTI()
121 << (OpCode == ARM::t2BTI ? "BTI" : "PACBTI") in addBTI()
124 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII.get(OpCode)) in addBTI()
/llvm-project/llvm/utils/TableGen/
H A DDXILEmitter.cpp51 int OpCode; // ID of DXIL operation
110 OpCode = R->getValueAsInt("OpCode");
341 OS << "DXIL_OPCODE(" << Op.OpCode << ", " << Op.OpName << ")\n"; in emitDXILOperationAttr()
403 OS << "DXIL_OP_ATTRIBUTES(dxil::OpCode::" << Op.OpName << ", "; in emitDXILOperationTable()
437 OS << "#define DXIL_OP_FUNCTION_TYPE(OpCode, RetType, ...)\n"; in emitDXILOperationTable()
440 OS << "DXIL_OP_FUNCTION_TYPE(dxil::OpCode::" << Op.OpName; in emitDXILOperationTable()
464 OS << "DXIL_OP_INTRINSIC(dxil::OpCode::" << Op.OpName in emitDXILOperationTable()
518 OS << "static const OpCodeProperty *getOpCodeProperty(dxil::OpCode Op) "
524 OS << Prefix << " { dxil::OpCode
39 int OpCode; // ID of DXIL operation global() member
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/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVInstPrinter.cpp110 const unsigned OpCode = MI->getOpcode(); in printInst() local
113 if (OpCode == SPIRV::OpDecorate) { in printInst()
115 } else if (OpCode == SPIRV::OpExtInstImport) { in printInst()
117 } else if (OpCode == SPIRV::OpExtInst) { in printInst()
121 const MCInstrDesc &MCDesc = MII.get(OpCode); in printInst()
131 switch (OpCode) { in printInst()
161 switch (OpCode) { in printInst()
H A DSPIRVMCCodeEmitter.cpp112 const uint64_t OpCode = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()
114 const uint32_t FirstWord = (NumWords << 16) | OpCode; in encodeInstruction()
113 const uint64_t OpCode = getBinaryCodeForInstr(MI, Fixups, STI); encodeInstruction() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMIRFormatter.cpp35 bool AMDGPUMIRFormatter::parseImmMnemonic(const unsigned OpCode,
41 switch (OpCode) { in parseImmMnemonic()
36 parseImmMnemonic(const unsigned OpCode,const unsigned OpIdx,StringRef Src,int64_t & Imm,ErrorCallbackType ErrorCallback) const parseImmMnemonic() argument
H A DAMDGPUMIRFormatter.h40 virtual bool parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx,
/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DMacOSKeychainAPIChecker.cpp506 BinaryOperator::Opcode OpCode = CondBSE->getOpcode(); in evalAssume() local
507 if (OpCode != BO_EQ && OpCode != BO_NE) in evalAssume()
515 bool ErrorIsReturned = (OpCode == BO_EQ && RHS != NoErr) || in evalAssume()
516 (OpCode == BO_NE && RHS == NoErr); in evalAssume()
H A DCheckObjCDealloc.cpp421 BinaryOperator::Opcode OpCode = CondBSE->getOpcode(); in evalAssume() local
423 if (OpCode != BO_EQ) in evalAssume()
426 if (OpCode != BO_NE) in evalAssume()
/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp164 unsigned OpCode = MI.getOpcode(); in InsertSPConstInst()
167 if (OpCode==XCore::STWFI) { in InsertSPConstInst()
179 switch (OpCode) { in InsertSPConstInst()
169 unsigned OpCode = MI.getOpcode(); InsertSPConstInst() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DMIRFormatter.h50 virtual bool parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, in parseImmMnemonic() argument
/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp149 unsigned &OpCode) { in initNames2RegMasks()
154 OpCode = InstrInfo->getValue(); in initNames2RegMasks()
501 bool parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
504 bool parseMachineOperandAndTargetFlags(const unsigned OpCode,
527 bool parseTargetImmMnemonic(const unsigned OpCode, const unsigned OpIdx,
555 bool parseInstruction(unsigned &OpCode, unsigned &Flags);
1066 unsigned OpCode, Flags = 0; in parse()
1067 if (Token.isError() || parseInstruction(OpCode, Flags)) in parse()
1081 if (parseMachineOperandAndTargetFlags(OpCode, Operands.size(), MO, TiedDefIdx)) in parse()
1171 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode); in parse()
140 parseInstrName(StringRef InstrName,unsigned & OpCode) parseInstrName() argument
1064 unsigned OpCode, Flags = 0; parse() local
1457 parseInstruction(unsigned & OpCode,unsigned & Flags) parseInstruction() argument
1844 parseTargetImmMnemonic(const unsigned OpCode,const unsigned OpIdx,MachineOperand & Dest,const MIRFormatter & MF) parseTargetImmMnemonic() argument
2897 parseMachineOperand(const unsigned OpCode,const unsigned OpIdx,MachineOperand & Dest,std::optional<unsigned> & TiedDefIdx) parseMachineOperand() argument
3006 parseMachineOperandAndTargetFlags(const unsigned OpCode,const unsigned OpIdx,MachineOperand & Dest,std::optional<unsigned> & TiedDefIdx) parseMachineOperandAndTargetFlags() argument
[all...]
/llvm-project/llvm/include/llvm/DebugInfo/LogicalView/Core/
H A DLVReader.h231 LVOperation *createOperation(LVSmall OpCode, ArrayRef<LVUnsigned> Operands) { in LV_CREATE_OBJECT()
232 return new (AllocatedOperation.Allocate()) LVOperation(OpCode, Operands); in LV_CREATE_OBJECT()
/llvm-project/llvm/lib/IR/
H A DValue.cpp61 unsigned OpCode = 0; in Value() local
63 OpCode = SubclassID - InstructionVal; in Value()
64 if (OpCode == Instruction::Call || OpCode == Instruction::Invoke || in Value()
65 OpCode == Instruction::CallBr) in Value()
/llvm-project/llvm/lib/DebugInfo/PDB/Native/
H A DNativeFunctionSymbol.cpp69 switch (Annot.OpCode) { in inlineSiteContainsAddress()
/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVModuleAnalysis.cpp539 const unsigned OpCode = MI.getOpcode(); in addRequirements()
540 if (OpCode == SPIRV::OpString) { in addRequirements()
542 } else if (OpCode == SPIRV::OpExtInst && MI.getOperand(2).isImm() && in checkSatisfiable()
556 } else if (OpCode == SPIRV::OpName || OpCode == SPIRV::OpMemberName) { in checkSatisfiable()
558 } else if (OpCode == SPIRV::OpEntryPoint) { in checkSatisfiable()
567 } else if (OpCode == SPIRV::OpFunction) { in checkSatisfiable()
569 } else if (OpCode == SPIRV::OpTypeForwardPointer) { in checkSatisfiable()
1610 const auto OpCode = MI.getOpcode();
1611 const unsigned LayoutNum = LayoutToInstMap[OpCode];
429 const unsigned OpCode = MI.getOpcode(); processOtherInstrs() local
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/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyIndVar.cpp1158 unsigned OpCode) const;
1384 unsigned OpCode) const { in getSCEVByOpCode()
1385 switch (OpCode) { in getSCEVByOpCode()
1662 const unsigned OpCode = NarrowUse->getOpcode(); in widenWithVariantUse() local
1664 if (OpCode != Instruction::Add && OpCode != Instruction::Sub && in widenWithVariantUse()
1665 OpCode != Instruction::Mul) in widenWithVariantUse()
1736 if (OpCode != Instruction::Add) in widenWithVariantUse()
/llvm-project/llvm/include/llvm/CodeGen/MIRParser/
H A DMIParser.h103 bool parseInstrName(StringRef InstrName, unsigned &OpCode);
/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3699 unsigned OpCode = 0; in expandBranchImm()
3702 OpCode = Mips::BNE; in expandBranchImm()
3705 OpCode = Mips::BEQ; in expandBranchImm()
3708 OpCode = Mips::BEQL; in expandBranchImm()
3712 OpCode = Mips::BNEL; in expandBranchImm()
3723 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, in expandBranchImm()
3727 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, in expandBranchImm()
3741 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, in expandBranchImm()
3745 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI); in expandBranchImm()
3763 unsigned OpCode in expandMem16Inst()
3696 unsigned OpCode = 0; expandBranchImm() local
3760 unsigned OpCode = Inst.getOpcode(); expandMem16Inst() local
3887 unsigned OpCode = Inst.getOpcode(); expandMem9Inst() local
4612 unsigned OpCode; expandSge() local
4703 unsigned OpCode; expandSgtImm() local
4749 unsigned OpCode; expandSle() local
[all...]
/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp976 const unsigned OpCode = MCI.getOpcode(); in requiresSlot() local
978 const bool NoSlotReqd = Hexagon::A4_ext == OpCode || in requiresSlot()
979 (IsTiny && Hexagon::A2_nop == OpCode) || in requiresSlot()
980 (IsTiny && Hexagon::J4_hintjumpr == OpCode); in requiresSlot()

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